NSC 5962-8968201LA, 5962-89682013A, 5962-8968201KA, 54AC646SDMQB-RH, 54AC646MDA Datasheet
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54AC646
Octal Transceiver/Register with TRI-STATE
®
Outputs
General Description
The ’AC646 consist of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on theAor B bus
will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in
Figures 1, 2, 3, 4
.
Features
n Independent registers for A and B buses
n Multiplexed real-time and stored data transfers
n TRI-STATE outputs
n 300 mil slim dual-in-line package
n Outputs source/sink 24 mA
n ’ACT646 has TTL compatible inputs
n Standard Microcircuit Drawing (SMD)
—’AC646: 5962-89682
Logic Symbols
Pin Names Description
A
0–A7
Data Register A Inputs
Data Register A Outputs
B
0–B7
Data Register B Inputs
Data Register B Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Transmit/Receive Inputs
G
Output Enable Input
DIR Direction Control Input
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100231-1
IEEE/IEC
DS100231-2
August 1998
54AC646 Octal Transceiver/Register with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100231 www.national.com
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100231-3
Pin Assignment
for LCC
DS100231-4
Real Time Transfer
A-Bus to B-Bus
DS100231-7
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
DS100231-8
FIGURE 2.
Storage from
Bus to Register
DS100231-9
FIGURE 3.
Transfer from
Register to Bus
DS100231-10
FIGURE 4.
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Function Table
Inputs Data I/O (Note 1) Function
G
DIR CPAB CPBA SAB SBA A0–A7B0–B
7
H X H or L H or L X X Isolation
HX
N
X X X Input Input Clock AnData into A Register
HX X
N
X X Clock BnData into B Register
LH X X L X A
n
to Bn—Real Time (Transparent Mode)
LH
N
X L X Input Output Clock AnData into A Register
L H H or L X H X A Register to B
n
(Stored Mode)
LH
N
X H X Clock AnData into A Register and Output to B
n
LL X X X L Bnto An—Real Time (Transparent Mode)
LL X
N
X L Output Input Clock BnData into B Register
L L X H or L X H B Register to A
n
(Stored Mode)
LL X
N
X H Clock BnData into B Register and Output to A
n
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
N
=
LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the
bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
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