NSC 5962R8769201VFA, 5962R8769201VEA, 5962R8769201V2A, 5962-8769201FA, 5962-8769201EA Datasheet
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54AC251•54ACT251
8-Input Multiplexer with TRI-STATE
®
Output
General Description
The ’AC/’ACT251 is a high-speed 8-input digital multiplexer.
It provides, in one package, the ability to select one bit of
data from up to eight sources. It can be used as universal
function generator togenerate any logic function of four variables. Both true and complementary outputs are provided.
Features
n ICCreduced by 50
%
n Multifunctional capability
n On-chip select logic decoding
n Inverting and noninverting TRI-STATE outputs
n Outputs source/sink 24 mA
n ’ACT251 has TTL-compatible inputs
n Standard Military Drawing (SMD)
—’AC251: 5962-87692
—’ACT251: 5962-89599
Logic Symbols
Pin Names Description
S
0–S2
Select Inputs
OE
TRI-STATE Output Enable Input
I
0–I7
Multiplexer Inputs
Z TRI-STATE Multiplexer Output
Z
Complementary TRI-STATE Multiplexer
Output
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100284-1
IEEE/IEC
DS100284-2
August 1998
54AC251
•
54ACT251 8-Input Multiplexer with TRI-STATE Output
© 1998 National Semiconductor Corporation DS100284 www.national.com
Connection Diagrams Functional Description
This device is a logical implementation of a single-pole,
8-position switch with the switch position controlled by the
state of three Select inputs, S
0,S1,S2
. Both true and
complementary outputs are provided. The Output Enable input ( OE) is active LOW. When it is activated, the logic function provided at the output is:
Z=OE
•
(I
0
•
S
0
•
S
1
•
S2+I
1
•
S
0
•
S
1
•
S2+
I
2
•
S
0
•
S
1
•
S2+I
3
•
S
0
•
S
1
•
S2+
I
4
•
S
0
•
S
1
•
S2+I
5
•
S
0
•
S
1
•
S2+
I
6
•
S
0
•
S
1
•
S2+I
7
•
S
0
•
S
1
•
S2)
When the Output Enable is HIGH, both outputs are in the
high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices
together. When the outputs of the TRI-STATE devices are
tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the
maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active-LOW portion of the enable voltages.
Truth Table
Inputs Outputs
OE
S
2
S
1
S
0
Z Z
HXXXZZ
LLLLI
0
I
0
LLLHI1I
1
LLHLI2I
2
LLHHI3I
3
LHLLI4I
4
LHLHI5I
5
LHHLI6I
6
LHHHI7I
7
H
=
HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
Pin Assignment
for DIP and Flatpak
DS100284-3
Pin Assignment
for LCC
DS100284-4
www.national.com 2
Logic Diagram
DS100284-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com3
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