NSC 5962R8955201VFA, 5962R8955201VEA, 5962R8955201V2A, 5962-8955201FA, 5962-8955201EA Datasheet

54AC175•54ACT175
Quad D Flip-Flop

General Description

The ’AC/’ACT175 is a high-speed quad D flip-flop. The de­vice is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D in­puts is stored during the LOW-to-HIGH clock transition. Both
true and complemented outputs of each flip-flop are pro­vided. AMaster Reset input resets all flip-flops, independent
of the Clock or D inputs, when LOW.

Features

n Edge-triggered D-type inputs

n Buffered positive edge-triggered clock
n Asynchronous common reset
n True and complement output
n Outputs source/sink 24 mA
n ’ACT175 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)

—’AC175: 5962-89552
—’ACT175: 5962-89693

Logic Symbols

Pin Names Description

D

0–D3

Data Inputs
CP Clock Pulse Input
MR

Master Reset Input
Q

0–Q3

True Outputs
Q

0–Q3

Complement Outputs

Connection Diagrams

FACT®is a registeredtrademark of Fairchild Semiconductor Corporation.

DS100278-1

IEEE/IEC

DS100278-2

Pin Assignment

for DIP and Flatpak

DS100278-3

Pin Assignment for LCC

DS100278-4

August 1998

54AC175

•

54ACT175 Quad D Flip-Flop

© 1998 National Semiconductor Corporation DS100278 www.national.com

Functional Description

The ’AC/’ACT175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW-to-HIGH clock
(CP) transition, causing individual Q and Q outputs to follow.
A LOW input on the Master Reset (MR) will force all Q out­puts LOWand Q outputs HIGH independent ofClock or Data
inputs. The ’AC/’ACT175 is useful for general logic applica­tions where a common Master Reset and Clock are
acceptable.

Truth Table

Inputs Outputs

@

tn,MR=H

@

t

n+1

D

n

Q

n

Q

n

LLH
HHL

H

=

HIGH Voltage Level
L=LOW Voltage Level
t

n

=

Bit Time before Clock Pulse
t

n+1

=

Bit Time after Clock Pulse

Logic Diagram

DS100278-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

CC

) −0.5V to +7.0V

DC Input Diode Current (I

IK

)

V

I

=

−0.5V −20 mA

V

I

=

V

CC

+ 0.5V +20 mA

DC Input Voltage (V

I

) −0.5V to VCC+ 0.5V

DC Output Diode Current (I

OK

)

V

O

=

−0.5V −20 mA

V

O

=

V

CC

+ 0.5V +20 mA

DC Output Voltage (V

O

) −0.5V to VCC+ 0.5V

DC Output Source

or Sink Current (I

O

)

±

50 mA

DC V

CC

or Ground Current

per Output Pin (I

CC

or I

GND

)

±

50 mA

Storage Temperature (T

STG

) −65˚C to +150˚C

Junction Temperature (T

J

)

CDIP 175˚C

Recommended Operating
Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V
’ACT 4.5V to 5.5V

Input Voltage (V

I

) 0VtoV

CC

Output Voltage (VO) 0VtoV

CC

Operating Temperature (TA)

54AC/ACT −55˚C to +125˚C

Minimum Input Edge Rate (∆V/∆t)

’AC Devices
V

IN

from 30%to 70%of V

CC

V

CC

@

3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

’ACT Devices
V

IN

from 0.8V to 2.0V

V

CC

@

4.5V, 5.5V 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom­mend operation of FACT

®

circuits outside databook specifications.

DC Characteristics for ’AC Family Devices

54AC

Symbol Parameter V

CC

T

A

=

−55˚C to +125˚C Units Conditions

(V) Guaranteed Limits

V

IH

Minimum High Level 3.0 2.1 V

OUT

=

0.1V

Input Voltage 4.5 3.15 V or V

CC

− 0.1V

5.5 3.85

V

IL

Maximum Low Level 3.0 0.9 V

OUT

=

0.1V

Input Voltage 4.5 1.35 V or V

CC

− 0.1V

5.5 1.65

V

OH

Minimum High Level 3.0 2.9 I

OUT

=

−50 µA

Output Voltage 4.5 4.4 V

5.5 5.4
(Note 2)

V

IN

=

V

IL

or V

IH

3.0 2.4 I

OH

=

−12 mA

4.5 3.7 V I

OH

=

−24 mA

5.5 4.7 I

OH

=

−24 mA

V

OL

Maximum Low Level 3.0 0.1 I

OUT

=

50 µA

Output Voltage 4.5 0.1 V

5.5 0.1
(Note 2)

V

IN

=

V

IL

or V

IH

3.0 0.50 I

OL

=

12 mA

4.5 0.50 V I

OL

=

24 mA

5.5 0.50 I

OL

=

24 mA

I

IN

Maximum Input 5.5

±

1.0 µA V

I

=

V

CC

, GND
Leakage Current
(Note 3)

I

OLD

Minimum Dynamic 5.5 50 mA V

OLD

=

1.65V Max

I

OHD

Output Current 5.5 −50 mA V

OHD

=

3.85V Min

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