NSC 5962-9324201QKA, 54ABT652J-QML, 54ABT652E-QML Datasheet

54ABT652
Octal Transceivers and Registers with TRI-STATE

®

Outputs

General Description

The ’ABT652 consists of bus transceiver circuits with D-type
flip-flops, andcontrolcircuitry arranged for multiplexed trans­mission of data directly from the input bus or from the inter­nal registers. Data on the A or B bus will be clocked into the
registers as the appropriate clock pin goes to HIGH logic
level. Output Enable pins (OEAB, OEBA) are provided to
control the transceiver function.

Features

n Independent registers for A and B buses

n Multiplexed real-time and stored data
n A and B output sink capability of 48 mA, source

capability of 24 mA

n Guaranteed latchup protection
n High impedance glitch free bus loading during entire

power up and power down cycle

n Nondestructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9324201

Ordering Code:

Commercial Package Package Description

Number

54ABT652J-QML J24A 24-Lead Ceramic Dual-in-line
54ABT652W-QML W24C 24-Lead Cerpack
54ABT652E-QML E28A 28-Lead Ceramic Leadless Chip Carrier, Type C

Connection Diagram

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Pin Assignment for

DIP and Flatpack

DS100220-1

August 1998

54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs

© 1998 National Semiconductor Corporation DS100220 www.national.com

Connection Diagram (Continued)

Pin Assignment for LCC

DS100220-48

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Pin Descriptions

Pin Names Description

A

0–A7

Data Register A Inputs/TRI-STATE Outputs

B

0–B7

Data Register B Inputs/TRI-STATE Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Select Inputs
OEAB, OEBA

Output Enable Inputs

Logic Diagram

Functional Description

In the transceiver mode, data present at the HIGH imped­ance port may be stored in either the A or B register or both.

The select (SAB, SBA) controls can multiplex stored and
real-time.

The examples in

Figure 1

demonstrate the four fundamental
bus-management functions that can be performed with the
’ABT652C.

Data on the A or B data bus, or both can be stored in the in­ternal D flip-flop by LOW to HIGH transitions at the appropri-

ate Clock Inputs (CPAB, CPBA) regardless of the Select or
Output Enable Inputs. When SAB and SBA are in the real
time transfer mode, it is also possible to store data without
using the internal D flip-flops by simultaneously enabling
OEAB and OEBA. In this configuration each Output rein­forces its Input. Thus when all other data sources to the two
sets of bus lines are in a HIGH impedance state, each set of
bus lines will remain at its last state.

DS100220-3

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Functional Description (Continued)

Note A: Real-Time

Transfer Bus B to Bus A

DS100220-4

OEAB OEBA CPAB CPBA SAB SBA

LLXXXL

Note C: Storage

DS100220-6

OEAB OEBA CPAB CPBA SAB SBA

XHNXXX
LXXNXX
LHNNXX

Note B: Real-Time

Transfer Bus A to Bus B

DS100220-5

OEAB OEBA CPAB CPBA SAB SBA

HHXXLX

Note D: Transfer Storage

Data to A or B

DS100220-7

OEAB OEBA CPAB CPBA SAB SBA

H L HorL HorL H H

FIGURE 1.

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Functional Description (Continued)

Inputs Inputs/Outputs (Note 1) Operating Mode

OEAB OEBA

CPAB CPBA SAB SBA A0thru A

7

B0thru B

7

L H H or L H or L X X Input Input Isolation
L H N N X X Store A and B Data
X H N H or L X X Input Not Specified Store A, Hold B
H H N N X X Input Output Store A in Both Registers
L X H or L N X X Not Specified Input Hold A, Store B
L L N N X X Output Input Store B in Both Registers
L L X X X L Output Input Real-Time B Data to A Bus
L L X H or L X H Store B Data to A Bus
H H X X L X Input Output Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and

Stored B Data to A Bus

H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial

N=LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at

the bus pins will be stored on every LOW to HIGH transition on the clock inputs.

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Absolute Maximum Ratings (Note 2)

Storage Temperature −65˚C to +150˚C
Ambient Temperature under Bias −55˚C to +125˚C
Junction Temperature under Bias

Ceramic −55˚C to +175˚C

V

CC

Pin Potential to

Ground Pin −0.5V to +7.0V
Input Voltage (Note 3) −0.5V to +7.0V
Input Current (Note 3) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disable or

or Power-Off State −0.5V to +5.5V

in the HIGH State −0.5V to V

CC

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

DC Latchup Source Current −500 mA

Over Voltage Latchup (I/O) 10V

Recommended Operating
Conditions

Free Air Ambient Temperature

Military −55˚C to +125˚C

Supply Voltage

Military +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100 mV/ns

Note 2: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.

Note 3: Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

Symbol Parameter ABT652 Units V

CC

Conditions

Min Typ Max

V

IH

Input HIGH Voltage 2.0 V Recognized HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min I

IN

=

−18 mA (Non I/O Pins)

V

OH

Output HIGH 54ABT 2.5 V Min I

OH

=

−3 mA, (A

n,Bn

)

Voltage 54ABT 2.0 I

OH

=

−24 mA, (A

n,Bn

)

V

OL

Output LOW 54ABT 0.55 V Min I

OL

=

48 mA, (A

n,Bn

)

Voltage

I

IH

Input HIGH Current 2 µA Max V

IN

=

2.7V (Non-I/O Pins) (Note 4)

V

IN

=

V

CC

(Non-I/O Pins)

I

BVI

Input HIGH Current 7 µA Max V

IN

=

7.0V (Non-I/O Pins)

Breakdown Test

I

BVIT

Input HIGH Current 100 µA Max V

IN

=

5.5V (A

n,Bn

)

Breakdown Test (I/O)

I

IL

Input LOW Current −2 µA Max V

IN

=

0.5V (Non-I/O Pins) (Note 4)

V

IN

=

0.0V (Non-I/O Pins)

I

IH+IOZH

Output Leakage Current 50 µA 0V–5.5V V

OUT

=

2.7V (A

n,Bn

);

OEBA=2.0V and OEAB=GND=2.0V

IIL+I

OZL

Output Leakage Current −50 µA 0V–5.5V V

OUT

=

0.5V (A

n,Bn

);

OEBA=2.0V and OEAB=GND=2.0V

I

OS

Output Short-Circuit Current −50 −180 mA Max V

OUT

=

0V (A

n,Bn

)

I

CEX

Output HIGH Leakage Current 50 µA Max V

OUT

=

V

CC(An,Bn

)

I

CCH

Power Supply Current 250 µA Max All Outputs HIGH

I

CCL

Power Supply Current 30 mA Max All Outputs LOW

I

CCZ

Power Supply Current 250 µA Max Outputs TRI-STATE;

All others at V

CC

or GND

I

CCT

Additional ICC/Input 2.5 mA Max V

I

=

V

CC

− 2.1V

All others at V

CC

or GND

Note 4: Guaranteed but not tested.
Note 5: For 8 outputs toggling, I

CCD

<

1.4 mA/MHz.

Note 6: Guaranteed, but not tested.

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