NSC 100343FMQB, 100343DMQB Datasheet

100343 Low Power 8-Bit Latch
General Description
The 100343 contains eight D-type latches, individual inputs, (D
n
), outputs (Qn), a commonenable pin (E), and a latch en­able pin (LE). A Q output follows its D input when both E and LE are LOW.When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to E or LE going HIGH.
The 100343 outputs are designed to drive a 50termination resistor to −2.0V. All inputs have 50 kpull-down resistors.
Features
n Low power operation n 2000V ESD protection n Voltage compensated operating range=−4.2V to −5.7V n Available to MIL-STD-883
Logic Symbol
Pin Names Description
D
0–D7
Data Inputs
E
Enable Input
LE
Latch Enable Input
Q
0–Q7
Data Inputs
NC No Connect
DS100298-1
August 1998
100343 Low Power 8-Bit Latch
© 1998 National Semiconductor Corporation DS100298 www.national.com
Connection Diagrams
Logic Diagram
Truth Table
Inputs Outputs
D
n
E LE Q
n
LLL L HLL H X H X Latched (Note 1) X X H Latched (Note 1)
H=HIGH voltage level
L=LOW voltage level
X=Don’t care
Note 1: Retains data present before either LE or E went HIGH
24-Pin DIP
DS100298-2
24-Pin Quad Cerpak
DS100298-3
DS100298-5
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Absolute Maximum Ratings (Note 2)
Storage Temperature (T
STG
) −65˚C to +150˚C
Maximum Junction Temperature (T
J
)
Ceramic +175˚C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 3) 2000V
Recommended Operating Conditions
Case Temperature (TC)
Military −55˚C to +125˚C
Supply Voltage (V
EE
) −5.7V to −4.2V
Note 2: Absolute maximum ratings are those values beyond which the de­vice may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version DC Electrical Characteristics
V
EE
=
−4.2V to −5.7V, V
CC
=
V
CCA
=
GND, T
C
=
−55˚C to +125˚C
Symbol Parameter Min Max Units T
C
Conditions Notes
V
OH
Output HIGH Voltage −1025 −870 mV 0˚C to V
IN
=
V
IH
(Max)
or V
IL
(Min)
Loading with
50to −2.0V
1, 2, 3
+125˚C
−1085 −870 mV −55˚C
V
OL
Output LOW Voltage −1830 −1620 mV 0˚C to
+125˚C
−1830 −1555 mV −55˚C
V
OHC
Output HIGH Voltage −1035 mV 0˚C to V
IN
=
V
IH
(Max)
or V
IL
(Min)
Loading with
50to −2.0V
1, 2, 3
+125˚C
−1085 mV −55˚C
V
OLC
Output LOW Voltage −1610 mV 0˚C to
+125˚C
−1555 mV −55˚C
V
IH
Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal for All Inputs 1, 2, 3, 4
+125˚C
V
IL
Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal for All Inputs 1, 2, 3, 4
+125˚C
I
IL
Input LOW Current 0.50 µA −55˚C to V
EE
=
−4.2V 1, 2, 3
+125˚C V
IN
=
V
IL
(Min)
I
IH
Input HIGH Current 240 µA 0˚C to V
EE
=
−5.7V
V
IN
=
V
IH
(Max)
1, 2, 3
+125˚C
340 µA −55˚C
I
EE
Power Supply Current −55˚C to Inputs Open
−100 −35 mA +125˚C V
EE
=
−4.2V to −4.8V 1, 2, 3
−105 −35 V
EE
=
−4.2V to −5.7V
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be consideredaworstcase condition at cold temperatures.
Note 5: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 7: Guaranteed by applying specified input condition and testing V
OH/VOL
.
Military Version AC Electrical Characteristics
V
EE
=
−4.2V to −5.7V, V
CC
=
V
CCA
=
GND
Symbol Parameter T
C
=
−55˚C T
C
=
+25˚C T
C
=
+125˚C Units Conditions Notes
Min Max Min Max Min Max
t
PLH
Propagation Delay 0.50 2.70 0.50 2.30 0.50 2.80 ns
Figures 1, 2, 3
(Notes 8, 9,
10, 12)
t
PHL
Dnto Output
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