NSC 5962-9153601VXA, 5962-9153601VYA, 5962-9153601MYA, 5962-9153601MXA, 100331MW8 Datasheet

100331
Low Power Triple D Flip-Flop

General Description

The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com­mon Clock (CP

C

), and Master Set (MS) and Master Reset

(MR) inputs. Each flip-flophas individual Clock (CP

n

), Direct

Set (SD

n

) and Direct Clear (CDn) inputs. Data enters a mas-

ter when both CP

n

and CPCare LOW and transfers to a

slave when CP

n

or CPC(or both) go HIGH. The Master Set,

Master Reset and individual CD

n

and SDninputs override

the Clock inputs. All inputs have 50 kΩ pull-down resistors.

Features

n 35%power reduction of the 100131
n 2000V ESD protection
n Pin/function compatible with 100131
n Voltage compensated operating range=−4.2V to −5.7V
n Available to industrial grade temperature range
n Available to Standard Microcircuit Drawing (SMD)

5962-9153601

Logic Symbol

Pin Names Description

CP

0

–CP

2

Individual Clock Inputs

CP

C

Common Clock Input

D

0–D2

Data Inputs

CD

0

–CD

2

Individual Direct Clear Inputs

SD

n

Individual Direct Set Inputs
MR Master Reset Input
MS Master Set Input
Q

0-Q2

Data Outputs
Q

0–Q2

Complementary Data Outputs

Connection Diagrams

DS100300-1

24-Pin DIP

DS100300-2

24-Pin Quad Cerpak

DS100300-3

August 1998

100331 Low Power Triple D Flip-Flop

© 1998 National Semiconductor Corporation DS100300 www.national.com

Logic Diagram

Truth Tables
Synchronous Operation

(Each Flip-Flop)

Inputs Outputs

D

n

CPnCPCMS MR Qn(t+1)

SD

n

CD

n

L

N

LLL L

H

N

LLL H

LL

N

LL L

HL

N

LL H
XLLLL Qn(t)
X H X L L Qn(t)
X X H L L Qn(t)

H=HIGH Voltage Level
L=LOW Voltage Level
X=Don’t Care
U=Undefined
t=Time before CP Positive Transition
t+1=Time after CP Positive Transition

N

=

LOW to HIGH Transition

Asynchronous Operation

(Each Flip-Flop)

Inputs Outputs

D

n

CPnCPCMS MR Qn(t+1)

SD

n

CD

n

XX XH L H
XX X L H L
XX XHH U

DS100300-5

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Above which the useful life may be impaired

Storage Temperature (T

STG

) −65˚C to +150˚C

Maximum Junction Temperature (T

J

)

Ceramic +175˚C

Pin Potential to

Ground Pin (V

EE

) −7.0V to +0.5V

Input Voltage (DC) V

EE

to +0.5V

Output Current

(DC Output HIGH) −50 mA

ESD (Note 2) ≤ 2000V

Recommended Operating
Conditions

Case Temperature (TC)

Military −55˚C to +125˚C

Supply Voltage (V

EE

) −5.7V to −4.2V

Note 1: Absolute maximum ratings are those values beyond which the de­vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Military Version

DC Electrical Characteristics

V

EE

=

−4.2V to −5.7V, V

CC

=

V

CCA

=

GND, T

C

=

−55˚C to +125˚C

Symbol Parameter Min Max Units T

C

Conditions Notes

V

OH

Output HIGH Voltage −1025 −870 mV 0˚C to V

IN

=

V

IH

(Max)

or V

IL

(Min)

Loading with

50Ω to −2.0V

(Notes 3,

4, 5)

+125˚C

−1085 −870 mV −55˚C

V

OL

Output LOW Voltage −1830 −1620 mV 0˚C to

+125˚C

−1830 −1555 mV −55˚C

V

OHC

Output HIGH Voltage −1035 mV 0˚C to V

IN

=

V

IH

(Min)

or V

IL

(Max)

Loading with

50Ω to −2.0V

(Notes 3,

4, 5)

+125˚C

−1085 mV −55˚C

V

OLC

Output LOW Voltage −1610 mV 0˚C to

+125˚C

−1555 mV −55˚C

V

IH

Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal

(Notes 3,

4, 5, 6)

+125˚C for all Inputs

V

IL

Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal

(Notes 3,

4, 5, 6)

+125˚C for all Inputs

I

IL

Input LOW Current 0.50 µA −55˚C to V

EE

=

−4.2V

(Notes 3,

4, 5)

+125˚C V

IN

=

V

IL

(Min)

I

IH

Input HIGH Current 240 µA 0˚C to V

EE

=

−5.7V

V

IN

=

V

IH

(Max)

(Notes 3,

4, 5)

+125˚C

340 µA −55˚C

I

EE

Power Supply Current −130 −50 mA −55˚C to Inputs Open

(Notes 3,

4, 5)

+125˚C

Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (toguaranteejunctiontemperatureequals−55˚C),thentestingimmediately
without allowing for the junction temperature to stabilize due toheatdissipationafterpower-up.Thisprovides“coldstart”specswhichcanbeconsideredaworstcase
condition at cold temperatures.

Note 4: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2, 3, 7 and 8.
Note 5: Sampled tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7 and 8.
Note 6: Guaranteed by applying specified input condition and testing V

OH/VOL

.

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