NPC SM8212B Datasheet
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS-1
OVERVIEW
The SM8212B is a POCSAG-standard (Post Office Code
Standardization Advisory Group) signal processor LSI,
which conforms to CCIR recommendation 584 concerning standard international wireless calling codes.
The SM8212B supports call messages in either tone,
numerical or character outputs at signal speeds of 512,
1200 or 2400 bps. The signal input stage features a built-in
filter.
Each of the addresses (max. 8) can be assigned to any
frame, which also makes the device configurable for many
additional services. Each address can be independently set
ON/OFF.
Furthermore, built-in buffer memory means decoded
information can be fetched in sync with the microcontroller clock, thereby reducing the microcontroller CPU
time required.
Intermittent-duty method (battery saving (BS) method)
control signals, compatible with PLL operation, and
Molybdenum-gate CMOS structure makes possible the
construction of low-voltage operation, low power dissipation systems.
The SM8212B is available in 16-pin SSOPs.
FEATURES
- Conforms to POCSAG standard for pagers
- 512, 1200 or 2400 bps signal speed
- Multiframe compatible (each address individually
controllable)
- 8 addresses × 4 sub-address (total of 32 addresses)
control
- Built-in buffer memory
- Supports tone, numeric or character call messages
- Built-in input signal filter, with filter ON/OFF and 4
selectable filter characteristics
- PLL-compatible battery saving method (BS1, BS2,
BS3 outputs)
- BS1 (RF control main output signal) 61-step setup
time setting
- BS3 (PLL setup signal) 61-step setup time setting
- BS2 (RF DC-level adjustment signal) before/during
reception selectable adjustment timing
- 1-bit and 2-bit burst error auto-correction function
- 25 to 75% duty factor signal coverage
- 8 rate error detection condition settings
- 76.8 kHz system clock (crystal oscillator)
- 76.8 or 38.4 kHz clock output pin
- Built-in oscillator capacitor and feedback resistor
- 2.0 to 3.5 V operating supply voltage
- Molybdenum-gate CMOS process realizes low power
dissipation
- 16-pin SSOP
PINOUTS
(16-pin SSOP)
PACKAGE DIMENSIONS
(Unit: mm)
16-pin SSOP (SM8212BM)
SM8212B
POCSAG Decoder For Multiframe Pagers
ATTN
BS1
BS2
BS3
VDD
SDI
SDO
SCKXVSS
XT
XTN
AREA
CLKOVSS
SIGNAL
RSTN
8212BM
1
8
9
16
4.4 0.2
6.2 0.3
0.6TYP
6.8 0.3
0.80.36 0.1
1.5 0.1
0.05 0.05
+ 0.10
0.15
- 0.05
010
0.4 0.2
NIPPON PRECISION CIRCUITS-2
SM8212B
BLOCK DIAGRAM
Timing Control
Flag Register
Address Register
Data Comparator
Receive Data Register
Preamble Pattern
Sync Code
Idle Code
Error Correction
Digital PLL
Buffer Register
SIGNAL
AREA
VDD
VSS
XVSS
SDI
SDO
SCK
CLKO
BS1
BS2
BS3
ATTN
RSTN
XT
XTN
Buffer Register
Timer
Clock Control
Main Control
Circuit
Each Working Block
Each Switch
and Register
(Ring)
NIPPON PRECISION CIRCUITS-3
SM8212B
Pin number Pin name i/o Description
1 BS1 o RF control main output signal
2 BS2 o RF DC-level adjustment signal
3 BS3 o PLL setup signal
4 SIGNAL i NRZ signal input pin
5 XVSS - Crystal oscillator ground. Capacitor connected between XVSS and VDD
6 XT i Oscillator input pin
7 XTN o Oscillator output pin
8 VSS - Ground
9 CLKO o 76.8 or 38.4 kHz clock output
10 RSTN i Hardware clear (reset)
11 AREA o Sync code detection output (HIGH for minimum 1 sec. on detection)
12 SCK i CPU-to-decoder data transfer sync clock
13 SDO o Status and received data output to CPU
14 SDI i Data input from CPU (including ID data)
15 ATTN o Interrupt detect signal output pin (Ready for data transmission when LOW)
16 VDD - Supply voltage
i = Input, o = Output
SM8212B Paging Receiver Block Diagram
RF
Waveform
Recovery
POCSAG
Decoder
SP
Melody
IC
PLL Circuit
CPU Unit
ID
ROM
D/D Converter LCD Driver
LCD
Supply Unit
SM8212
Alert
PIN DESCRIPTION
NIPPON PRECISION CIRCUITS-4
SM8212B
SPECIFICATIONS
Absolute Maximum Ratings
Recommended Operating Conditions
DC Characteristics
Parameter Symbol Condition Rating Unit
Supply voltage range V
DD -0.3 to 7.0 V
Input voltage range V
IN VSS-0.3 to VDD+0.3 V
Storage temperature range T
STG -40 to 125 °C
Power dissipation P
W 250 mW
Soldering temperature T
SLD 255 °C
Soldering time
tSLD 10 sec.
(VSS=0V)
Rating
Parameter Symbol Condition MIN TYP MAX Unit
Supply voltage V
DD 2.0 - 3.5 V
Operating temperature T
OPR -20 70 °C
(VSS=0V)
Rating
Parameter Pin Symbol Condition MIN TYP MAX Unit
Operating current consumption VDD I
DD1 VDD=3.0V (Note1) 3.0 6.0 µA
(IDLE mode) V
DD=2.0V (Note 1) 2.0 4.0
Standby supply current VDD I
DD2 VDD=3.0V (Note 2) 2.0 4.0 µA
V
DD=2.0V (Note 2) 1.5 3.0
Input voltage All input pins V
IH 0.8*VDD V
V
IL 0.2*VDD
Output current All outputs IOH VOH=2.6V, VDD=3.0V 0.6 1.4 mA
except XTN I
OL VOL=0.4V, VDD=3.0V 1.0 2.2
Output current All outputs I
OH VOH=1.6V, VDD=2.0V 0.3 0.7 mA
except XTN I
OL VOL=0.4V, VDD=2.0V 0.7 1.5
(Recommended operating conditions unless otherwise noted)
(Note 1) When killed CLKO output
(Note 2) Oscillator circuit is working
The consumption current is slightly higher when RSTN is going LOW.
NIPPON PRECISION CIRCUITS-5
SM8212B
AC Characteristics
Rating
Parameter Synbol MIN TYP MAX Unit Condition
XT clock frequency f
CYXT -250ppm 76.8 +250ppm kHz
XT clock duty cycle D
XT 25 75 %
SCK clock pulsewidth t
PWSC 2 150 µs
5 1900 µs 512bps
SCK clock interval (except WRITE mode) t
CYSC 5 830 µs 1200bps
5 415 µs 2400bps
SCK clock interval (WRITE mode) t
CYSC 5 830 µs
SDI data setup time t
SSDI 1 µs
SDI data hold time t
HSDI 1 µs
SDO data setup time t
SSDO 3 µs
SDO data hold time t
HSDO 0 µs
ATTN signal setup time t
SATT 0 µs
ATTN signal hold time t
HATT 1 µs
CLKO clock rise time t
RCLK 500 ns No load
CLKO clock fall time t
FCLK 500 ns No load
CLKO clock delay time D
CLKO 1 µs
RSTN pulsewidth t
PWRS 1ms
(Recommended operating conditions unless otherwise noted)
ATTN
SCK
SDI
12332
INPUT
DATA 1
INPUT
DATA 2
INPUT
DATA 3
INPUT
DATA 32
1/ 2*VDD
tPWSC
tSSDI tHSDI
tCYSC
tHATT
Parameter/address set timing
ATTN
SCK
Decoder Mode
SDI
128
Decoder
Setting1
Decoder
Setting 2
Decoder
Setting 8
1/ 2*VDD
Next ModeCurrent Mode
tCYSC
tHSDItSSDI
tPWSC
tHATT
Auxiliary operating mode set timing
START command : 66 bit time max
Others : 2 bit time max
NIPPON PRECISION CIRCUITS-6
SM8212B
ATTN
SCK
SDO
SDI
1289
READ
COMMAND 1
READ
COMMAND 2
READ
COMMAND 8
Don't
Care 1
Don't
Care 2
READ
COMMAND 9
STATUS
DATA 1
1/ 2*VDD
16
STATUS
DATA 8
READ
COMMAND 16
Don't
Care 8
tSSDO
tHSDO
tCYSC
tHSDItSSDI
tPWSC
Status data read timing
ATTN
SCK
SDO
SDI
12332
OUTPUT
DATA 1
OUTPUT
DATA 2
OUTPUT
DATA 3
OUTPUT
DATA 32
1/ 2*VDD
tCYSC
tPWSC
tSSDO tHSDO
tSATT
tHATT
Received data transfer timing
CLKO
(38.4kHz Mode)
CLKO
(76.8kHz Mode)
0.7*VDD
0.3*VDD
1/ 2*VDD
1/ 2*VDD
0.7*VDD
0.3*VDD
tRCLKtFCLK
tRCLKtFCLK
CLKO clock output timing
(XT)
(76.8kHz )
0.7*VDD
0.3*VDD
1/ 2*VDD
DCLKO
αβ
DXT =
α
α+β
NIPPON PRECISION CIRCUITS-7
SM8212B
Sync Code Part
1 Batch
Frame Part
01
234
567
1 Code Word
Sync Code Part
SC
SC
7
0
Sync Code Word
1
32
Address bits Function bits Check bits
Message bits
12
19 20 21 22 31
32
0
1
Even-parity bit
Even-parity bit
Check bits
Address signal
Message signal
1 Frame (= 2 Code Words)
Preamble 1st Batch 2nd Batch
Frame No.
Continuous 575-bit "1, 0" bit pattern
Sync
Code
Sync
Code
Figure 1. Receive signal format
Bit number Bit value Bit number Bit value Bit number Bit value Bit number Bit value
1091170251
2 1 10 1 18 0 26 1
3 1 11 0 19 0 27 0
4 1 12 1 20 1 28 1
5 1 13 0 21 0 29 1
6 1 14 0 22 1 30 0
7 0 15 1 23 0 31 0
8 0 16 0 24 1 32 0
Table 1. Sync code format
FUNCTIONAL DESCRIPTION
1. Receive Format
The sync signal is a continuous code word in the received
signal, used for word synchronization. It comprises 31 bits
in an M-series bit pattern plus one even-parity bit, making
a 32-bit signal. The sync code word pattern is shown in
table 1.
(1) Sync signal (SC)
Unless otherwise specified, values in diagrams without
parentheses are for 512 bps, in ( ) are for 1200 bps, and in
[ ] are for 2400 bps. “M” represents the value of PL5
(MSB) to PL0 (LSB), and “N” represents the value of RF5
(MSB) to RF0 (LSB).
The receive format conforms to CCIR RPC No. 1
(POCSAG).
NIPPON PRECISION CIRCUITS-8
SM8212B
Each code word comprises 32 bits as shown in table 2.
Bit number
1 (MSB) 2 to 19 20 to 21 22 to 31 32 (LSB)
Address
Signal
Code word
Message
Signal
Function20 21
00
A call
01
B call
10
C call
11
D call
Function bits
0
1
Address bits
Message bits
Check bits Even-parity bit
Check bits Even-parity bit
1. The MSB is the address/message code word control bit. It is 0 for an address signal, and 1 for a message signal.
2. Bits 2 to 21 contain the address or message information.
3. Bits 22 to 31 are BCH(31,21) format generated check bits, where BCH(n,k) = BCH(word length, number of information bits).
4. The LSB is an even-parity bit for bits 1 to 31.
Table 2. Code word format
This conversion expands a 7-digit decimal call number
into a 21-bit binary call sign, as shown in figure 2.
After expansion, the high-order 18 bits are assigned to
bits 2 to 19 (address signal), and the low-order 3 bits are
the user-defined frame identification pattern, which is
stored in ID-ROM. The two function bits define which of
four call functions is active.
(3) Call number to call sign conversion
1234567
123456789101112131415161718192021
MSB LSB
7-digit decimal call signal (gap code) (8 to 2000000)
21-bit binary conversion
Call sign
0
1 2 19 20 21 323122
Frame
identification
pattern
Even-parity bit
(for bits 1 to 31)
BCH(31, 21) generated check bits
Flag : "0" = Adderss signal
Function bits
Bits 2 to 19 (18 bits)
Bits 22 to 31 (10 bits)
P
Figure 2. Call number to call sign conversion
(2) Code words (address and message signals)
NIPPON PRECISION CIRCUITS-9
SM8212B
(4) Idle signal
Bit number Bit value Bit number Bit value Bit number Bit value Bit number Bit value
1091171251
2 1 10 0 18 1 26 0
3 1 11 0 19 0 27 0
4 1 12 0 20 0 28 1
5 1 13 1 21 0 29 0
6 0 14 0 22 0 30 1
7 1 15 0 23 0 31 1
8 0 16 1 24 1 32 1
Table 3. Idle code format
(5) Receive signal duty factor
(6) Error Correction and Detection
During preamble detection, the preamble pattern (1,0) is
recognized at duty factors from 25% (min) to 75% (max)
of the (1,0) preamble cycle.
Item Description
Preamble Pattern Detection Selectable 1 to 8 rate errors in 6 to 544 bits
Synchronization Code word Detection 2 random errors in 32 bits
Self Address Code word Detection 2 random errors in 32 bits
Message Code word 1-bit and 2-bit burst errors in 31 bits
Table 4. Error correction
The SM8212B performs error correction (or detection)
on each code word as described in table 4. Note that there
are 8 selectable error correction conditions for the preamble pattern.
An error is deemed to have occurred when 2 or more signal edges occur within 1-bit unit time, and a rate error is
deemed to have occurred when the number of errors
exceeds the counter value. Refer to the “Preamble Mode”
section for a discussion of the error counter.
In the POCSAG format, for pager systems that send
numeric data, the message information content varies and
as a result an idle signal or another address signal is inserted
after the message to indicate the end of the message.
That is, if no address word or message word exists for a
frame within a batch or for a code word within a frame, the
idle pattern, shown in table 3, is transmitted in its place.
Then during message signal reception, the message ends
when the idle signal is detected.
The SM8212B, however, supports 2 methods of determining the end of message. Namely, message ends when
either an idle signal or another address is received (POCSAG format), or solely by an interrupt signal from the
CPU.
NIPPON PRECISION CIRCUITS-10
SM8212B
The SM8212B controls the intermittent-duty operation
of the RF stage, which reduces battery consumption, and
outputs three control signals (BS1, BS2, BS3). The function each signal controls in each mode is described below.
BS1 (RF-control main output signal)
The RF stage is active when BS1 is HIGH. The rising-edge setup time for receive timing is set by flags
RF0 to RF5 (61 steps). The maximum setup time is
25.417 ms at 2400 bps, 50.833 ms at 1200 bps and
119.141 ms at 512 bps. Note that 3E and 3F are
invalid settings for BS1.
BS2 (RF DC-level adjustment signal)
BS2 is used to control the discharge of the receive signal DC-cut capacitor. The function of BS2 is determined by flag BS2, as described below.
-When flag “BS2 option” is 0, pin BS2 goes HIGH
together with BS1 and then goes LOW again after the
BS1 setup time in idle mode. In preamble and lock
(during address/message reception) mode, it keeps
LOW.
-When flag “BS2 option” is 1, pin BS2 goes HIGH
during lock mode sync code receive timing and idle
mode signal receive timing. In preamble mode, it
keeps LOW.
BS3 (PLL setup signal)
BS3 is used to control PLL operation when the PLL is
used. The rising-edge setup time for receive timing is
set by flags PL0 to PL5 (61 steps). The maximum
setup time is 25.833 ms at 2400 bps, 51.667 ms at
1200 bps and 121.094 ms at 512 bps. Note that 3F is
an invalid setting for BS3.
Note also that the setup times should be set such that
(BS3 rising-edge setup time) > (BS1 rising-edge setup
time).
2. Battery Saving (BS1, BS2, BS3)
SYN
ICW
MES
ADD
ICW
MES
ICW
ADD
MES
MES
MES
MES
ICW
ICW
ICW
ADD
MES
SYN
MES
MES
MES
MES
ICW
ICW
ADD
MES
MES
MES
MES
ICW
ADD
MES
SYN
ADD
MES
01234567 01 345672
01234567 01 345672
SYN
MES
ADD
SYN
MES
MES
ICW
ICW
ICW
ICW
MES
MES
MES
MES
MES
MES
MES
MES
SYN
MES
MES
MES
ICW
ADD
MES
MES
MES
ICW
ADD
MES
ICW
ICW
ICW
MES
MES
Self address
1.953*Nms (0.833*Nms)
[0.417*Nms]
1.953*Mms
(0.833*Mms) [0.417*Mms]
1.953*Nms (0.833*Nms)
[0.417*Nms]
1.953*Mms
(0.833*Mms) [0.417*Mms]
BREAK detection to reception stop (32 bit max.)
Receive code
BS1
BREAK command
BS2
(flag BS2 option = 0)
BS2
(flag BS2 option = 1)
BS3
Receive code
BS1
BS2
(flag BS2 option = 0)
BS2
(flag BS2 option = 1)
BS3
Figure 3. BS1, BS2 and BS3 timing (LOCK mode, frame 3)
Address does not match
Self address
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