NPC SM5906AF Datasheet

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SM5906AF

Shock-proof Memory Controller for Video CD Players

Overview

– 2-channel processing
– Serial data input

• 2s complement, 16-bit/MSB first

• Right-justified format

• Wide capture function
(up to 4 × speed input rate)

• Selectable 16/24/32-bit clock

– System clock input

• 384fs (16.9344 MHz)

– Shock-proof memory controller

• Selectable CD-DA/V-CD/SVC mode

• 2 external DRAM configurations selectable

1 × 16M DRAM (4M × 4 bits, refresh cycle =
2048 cycle)
1 × 4M DRAM (1M × 4 bits)

– Microcontroller interface

• Serial command write and status read-out

• Data residual detector:

11-bit operation, 16-bit output
(Bits 13 to 15 bit are fixed LOW.)

• Forced mute

– Extension I/O

Microcontroller interface for external control

using 3 extension I/O pins
– +2.7 to +3.6 V operating voltage range
– Schmitt inputs

All input pins (including I/O pins) except CLK

(system clock)
– Reset signal noise elimination

Approximately 3.8 µs or longer (65 system

clock pulses) continuous LOW-level reset

- 48-pin QFP package (0.5 mm pin pitch)

Pinout

(Top View)

The SM5906AF is a shock-proof memory controller
LSI for video CD players. The operating mode can
be set to CD-DA mode, V-CD mode, or Super V-CD

mode, and external memory can be selected from 2
options (4M, 16M). It operates from a 2.7 to 3.6 V
supply voltage range.

Features

Ordering Information

SM5906AF 48pin QFP

38
39
40
41
42
43
44
45
46
47
48

123456789

10

11

13

14

15

16

17

18

19

20

21

22

23

26

27

28

29

30

31

32

33

34

35

36

A9
A8
A7
A6
A5
A4
A0
A1
A2
A3

VSS4

YMLD
YDMUTE
ZSENSE
NRESET
YBLKCK
YFLAG
ZC2PO
ZSRDATA
ZSCK
ZLRCK
VDD2

VDD1

UC1

UC2

UC3

NTEST1

TEST2

CLK

YC2PO

YSRDATA

YLRCK

YSCK

VSS3

A10

NWED1D0D3D2

NCAS

NRAS

YMCLK

YMDATA

12

VSS1

24

VSS2

37

VDD4

25

VDD3

SM5906AF

JAPAN

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SM5906AF

Package dimensions

(Unit: mm)

48-pin QFP

Pin description

0.1

1.7max

0.5

9

0.4
7

0.1

9

0.4

7

0.1

0.18

0.05

0.1

1.4 0.1

0.125

0.025

0.5

0.5 0.2

Pin number Pin name I/O Function Setting

HL

1 VDD1 – VDD supply pin
2 UC1 Iu/O Microcontroller interface extension I/O 1
3 UC2 Iu/O Microcontroller interface extension I/O 2
4 UC3 Iu/O Microcontroller interface extension I/O 3
5 NTEST1 Iu Test pin Test
6 TEST2 Id Test pin Test
7 CLK I 16.9344 MHz clock input
8 YC2PO I Serial input C2PO data

9 YSRDATA I Serial input data
10 YLRCK I Serial input LR clock Left channel Right channel
11 YSCK I Serial input bit clock
12 VSS1 – Ground
13 VDD2 – VDD supply pin
14 ZLRCK O Serial output LR clock Left channel Right channel
15 ZSCK O Serial output bit clock

Iu : Input pin with pull-up resistor, Id : Input pin with pull-down resistor
Iu/O : Input/Output pin (With pull-up resistor when in input mode)

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SM5906AF

Pin description

Pin number Pin name I/O Function Setting

HL

16 ZSRDATA O Serial output data
17 ZC2PO O Serial output C2PO data
18 YFLAG I Signal processor IC RAM overflow flag
19 YBLKCK I Subcode block clock signal
20 NRESET I System reset pin Reset
21 ZSENSE O Microcontroller interface status output
22 YDMUTE I Forced mute pin Mute
23 YMLD I Microcontroller interface latch clock
24 VSS2 – Ground
25 VDD3 – VDD supply pin
26 YMDATA I Microcontroller interface serial data
27 YMCLK I Microcontroller interface shift clock
28 NRAS O DRAM RAS control
29 NCAS O DRAM CAS control
30 D2 Iu/O DRAM data input/output 2
31 D3 Iu/O DRAM data input/output 3
32 D0 Iu/O DRAM data input/output 0
33 D1 Iu/O DRAM data input/output 1
34 NWE O DRAM WE control
35 A10 O DRAM address 10
36 VSS3 – Ground
37 VDD4 – VDD supply pin
38 A9 O DRAM address 9
39 A8 O DRAM address 8
40 A7 O DRAM address 7
41 A6 O DRAM address 6
42 A5 O DRAM address 5
43 A4 O DRAM address 4
44 A0 O DRAM address 0
45 A1 O DRAM address 1
46 A2 O DRAM address 2
47 A3 O DRAM address 3
48 VSS4 – Ground

Iu : Input pin with pull-up resistor, Id : Input pin with pull-down resistor
Iu/O : Input/Output pin (With pull-up resistor when in input mode)

Parameter Pin Symbol Condition Rating Unit

Min Typ Max

Current consumption VDD I

DD (*A)SHPRF ON 4.5 9.0 mA

(*A)Through mode 1.5 3.0 mA

Input voltage CLK H level V

IH1 0.8VDD V

L level V

IL1 0.2VDD V

(*2,3,5) H level V

IH2 VDD – 0.3 V

L level V

IL2 0.6 V

(*4) H level V

IH3 0.8VDD V

L level V

IL3 0.2VDD V

Output voltage (*5) H level V

OH1 IOH = – 1.0 mA VDD – 0.4 V

L level V

OL1 IOL = 1.0 mA 0.4 V

(*6) H level V

OH2 IOH = – 1.0 mA VDD – 0.4 V

L level V

OL2 IOL = 1.0 mA 0.4 V

Input current (*4) I

IH VIN = VDD 10 25 80 µA

(*3,5) I

IL VIN = 0V 10 25 80 µA

Input leakage current (*1,2,5) I

LH VIN = VDD 1.0 µA

(*1,2,4) I

LL VIN = 0V 1.0 µA

(*A) VDD1 = VDD2 = VDD3 = VDD4 = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded,
SHPRF: Shock-proof,
typical values are for V

DD1 = VDD2 = VDD3 = VDD4 = 3 V.

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SM5906AF

Parameter Symbol Rating Unit

Supply voltage V

DD – 0.3 to 4.0 V

Input voltage V

I VSS – 0.3 to VDD + 0.3 V

Storage temperature T

STG – 55 to 125 ˚C

Power dissipation P

D 340 mW

Soldering temperature T

SLD 255 ˚C

Soldering time

tSLD 10 sec

(VSS1 = VSS2 = VSS3 = VSS4 = 0V, VDD1, VDD2, VDD3, VDD4 pin voltage = VDD)

Note. Refer to pin summary on the next page.
Values also apply for supply inrush and switch-off.

Parameter Symbol Rating Unit

Supply voltage V

DD 2.7 to 3.6 V

Operating temperature T

OPR – 10 to 70 ˚C

(VSS1 = VSS2 = VSS3 = VSS4 = 0V, VDD1, VDD2, VDD3, VDD4 pin voltage = VDD)

Electrical characteristics

Recommended operating conditions

DC characteristics

Standard voltage:(VDD1 = VDD2 = VDD3 = VDD4 = 2.7 to 3.6V, VSS1 = VSS2 = VSS3 = VSS4 = 0V, Ta = – 10 to 70˚C)

Absolute maximum ratings

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SM5906AF

<Pin summary>

(*1) Pin function Clock input pin

Pin name CLK

(*2) Pin function Schmitt input pins

Pin name YSRDATA, YLRCK, YSCK, YC2PO, YFLAG, NRESET,

YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK

(*3) Pin function Schmitt input pin with pull-up

Pin name NTEST1

(*4) Pin function Schmitt pin with pull-down

Pin name TEST2

(*5) Pin function I/O pins (Schmitt input with pull-up in input state)

Pin name UC1, UC2, UC3, D0, D1, D2, D3

(*6) Pin function Outputs

Pin name ZSCK, ZLRCK, ZSRDATA, ZC2PO, ZSENSE, NCAS, NWE,

NRAS, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10

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SM5906AF

CWH

t

CWL

t

CY

t

0.5V

DD

CLK

AC characteristics

Standard voltage: VDD1 = VDD2 = VDD3 = VDD4 = 2.7 to 3.6V, VSS1 = VSS2 =VSS3 =VSS4 =0V, Ta = –10 to 70 ˚C
(*) Typical values are for fs = 44.1 kHz

System clock (CLK pin)

Parameter Symbol Condition Rating Unit

System clock Min Typ Max

Clock pulsewidth (HIGH level)

tCWH 26 29.5 50 ns

Clock pulsewidth (LOW level)

tCWL 26 29.5 50 ns

Clock pulse cycle

tCY 384fs 58 59 100 ns

System clock input

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SM5906AF

Parameter Symbol Rating Unit Condition

Min Typ Max

YSCK pulsewidth (HIGH level)

tBCWH 75 ns

YSCK pulsewidth (LOW level)

tBCWL 75 ns

YSCK pulse cycle

tBCY 150 ns

YSRDATA setup time

tDS 50 ns

YSRDATA hold time

tDH 50 ns

Last YSCK rising edge to YLRCK edge

tBL 50 ns

YLRCK edge to first YSCK rising edge

tLB 50 ns

0 4fs Memory system ON

YLRCK pulse frequency (MSON=H)

See note below. fs fs Memory system OFF

(MSON=L)

YC2PO setup time

tES 1 µs

YC2PO hold time

tEH 1 µs

Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input

data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode
operation.

YSCK

YSRDATA

YLRCK

BCY

t

DS

t

DH

t

BCWH

t

BCWL

t

LB

t

BL

t

0.5

V

DD

0.5

V

DD

0.5

V

DD

t

LR/4

t

LR/2

t

LR/2

t ESt

EH

t ESt

EH

t

LR/4

YLRCK

YC2PO

Serial input (YSRDATA, YLRCK, YSCK YC2PO pins)

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SM5906AF

Parameter Symbol Rating Unit

Min Typ Max

YMCLK LOW-level pulsewidth

tMCWL 30 + 2tCY ns

YMCLK HIGH-level pulsewidth

tMCWH 30 + 2tCY ns

YMDATA setup time

tMDS 30 + tCY ns

YMDATA hold time

tMDH 30 + tCY ns

YMLD LOW-level pulsewidth

tMLWL 30 + 2tCY ns

YMLD setup time

tMLS 30 + tCY ns

YMLD hold time

tMLH 30 + tCY ns

Rise time

tr 100 ns

Fall time

tf 100 ns

ZSENSE output delay

tPZS 100 + 3tCY ns

Note. tCY is the system clock (CLK) input (384fs) cycle time.

tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz

YMDATA

YMCLK

ZSENSE

YMLD

YMDATA

YMCLK

YMLD

MDS

t

MDH

t

MCWL

t

MLS

t

MCWH

t

MLH

t

MLWL

t

PZS

t

0.5VDD0.5V

DD

0.5V

DD

0.5V

DD

0.5V

DD

0.5V

DD

0.3VDD 0.3VDD

0.7VDD 0.7VDD

f

t

r

t

Reset input (NRESET pin)

Parameter Symbol Rating Unit

Min Typ Max

First HIGH-level after supply voltage rising edge

tHNRST 0 tCY (Note)

NRESET pulsewidth

tNRST 64 tCY (Note)

Note. tCY is the system clock (CLK) input (384fs) cycle time.

tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz

NRESET

VDD

HNRST

t t

NRST

Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins)

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SM5906AF

Parameter Symbol Condition Rating Unit

Min Typ Max

ZSCK pulsewidth

tSCOW 15 pF load 1/96fs

ZSCK pulse cycle

tSCOY 15 pF load 1/48fs

ZSRDATA, ZLRCK, ZC2PO

tDHL 15 pF load 0 60 ns

output delay time

tDLH 15 pF load 0 60 ns

DRAM access timing (NRAS, NCAS, NWE, A0 to A10, D0 to D3)

Parameter Symbol Condition Rating Unit

Min Typ Max

NRAS pulsewidth

tRASL 15 pF load 4 tCY(note)

tRASH 15 pF load 2 tCY

NRAS falling edge to NCAS falling edge tRCD 15 pF load 2 tCY

NCAS pulsewidth tCASH 15 pF load 4 tCY

tCASL 15 pF load 2 tCY

NRAS Setup time tRADS 15 pF load 1 tCY

falling edge to address Hold time tRADH 15 pF load 1 tCY

NCAS Setup time tCADS 15 pF load 1 tCY

falling edge to address Hold time tCADH 15 pF load 2 tCY

NCAS Setup time tCWDS 15 pF load 3 tCY

falling edge to data write Hold time tCWDH 15 pF load 2 tCY

NCAS Input setup tCRDS 40 ns

rising edge to data read Input hold

tCRDH 0ns

NWE pulsewidth

tWEL 15 pF load 5 tCY

NWE falling edge to NCAS falling edge tWCS 15 pF load 3 tCY

Refresh cycle 4M CD-DA MODE 3.0 ms

(fs = 44.1 kHz playback)

DRAM VCD MODE 2.6 ms

tREF × 1 SVC MODE 1.3 ms

Memory system ON

16M CD-DA MODE 5.9 ms

Read sequence operation

DRAM VCD MODE 5.2 ms

(RDEN=H)

× 1 SVC MODE 2.6 ms

Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz

ZSCK

ZSRDATA

0.5V

DD

DLH

ZLRCK

0.5V

DD

DHL

tt

DLH

SCOW

tt

SCOW

t

SCOY

t

ZC2PO

Serial output (ZSRDATA, ZLRCK, ZSCK ZC2PO pins)