NPC SM5901AF Datasheet

NIPPON PRECISION CIRCUITS INC.

SM5901AF

compression and non compression type anti-shock
memory controller with built-in 1M DRAM

preliminary

Overview

- 2-channel processing

- Serial data input

•2s complement, 16-bit/MSB first, rear-packed
format

- System clock input

•384fs (16.9344 MHz)

- Anti-shock memory controller

- ADPCM compression method

•4-level compression mode selectable
4-bit compression mode 2.78 s/Mbit
5-bit compression mode 2.22 s/Mbit
6-bit compression mode 1.85 s/Mbit
Full-bit non compression mode 0.70 s/Mbit

•External memory can be connected
2×1M DRAM (256K×4 bits)

Internal and external 1M DRAMs

1×1M DRAM (256K×4 bits)

Only internal 1M DRAM

- Compression mode selectable

- Microcontroller interface

•Serial command write and state read-out

•Data residual quantity detector:

15-bit operation, 16-bit output

•Digital attenuator
Full-bit setting

•Soft attenuator function
Noiseless attenuation-level switching
(256- step switching in 23 ms max.)

•Soft mute function
Mute ON in 23 ms max.
Direct return after soft mute release

•Forced mute

- Extension I/O
Microcontroller interface for external control
using 5 extension I/O pins

- +2.7 to +3.3 V wide operating voltage range

- Schmitt inputs
All input pins (including I/O pins) except CLK
(system clock)

- Reset signal noise elimination
Approximately 3.8 µs or longer (65 system
clock pulses) continuous LOW-level reset

- 44-pin QFP package (0.8 mm pin pitch)

The SM5901 is a compression and non compres­sion type anti-shock memory controller with built-in
1M DRAM LSI for compact disc players. The com­pression level can be set in 4 levels, and external

1M DRAM can be connected to expand the memo­ry to 2M bits. Digital attenuator, soft mute and relat­ed functions are also incorporated. It operates from
a 2.7 to 3.3 V wide supply voltage range.

Features

SM5901AF

preliminary

Package dimensions

(Unit: mm)

44-pin QFP

13.20 0.30

+

-

13.20 0.30

+

-

10.00 0.20

+

-

10.00 0.20

+

-

2.05 0.10

+

-

0.15 - 0.05

+0.10

0 to 8

+

-

0.80 0.20

0.80

0.35

2.30MAX

0.05MIN

1.60

Pinout

(Top View)

1
2
3
4
5
6
7
8

9
10
11

1213141516171819202122

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

VDD2

UC1
UC2
UC3
UC4

VSS2
NTEST1
NTEST2

CLK

VSS1

YSRDATA

NWE
D1
D0
D3
D2
NCAS2
NTEST4
YMCLK
YMDATA
YMLD
YDMUTE

YLRCK

YSCK

ZSCK

ZLRCK

ZSRDATA

YFLAG

YFCLK

YBLKCK

NRESET

ZSENSE

VDD1

A3A2A1A0A4A5A6A7A8

NTEST3

NRAS

SM590

1AF

SM5901AF

preliminary

Pin number Pine name I/O Function Setting

HL

1 VDD2 - VDD supply pin
2 UC1 Ip/O Microcontroller interface extension I/O 1
3 UC2 Ip/O Microcontroller interface extension I/O 2
4 UC3 Ip/O Microcontroller interface extension I/O 3
5 UC4 Ip/O Microcontroller interface extension I/O 4
6 VSS2 - Ground
7 NTEST1 Ip Test pin Test
8 NTEST2 Ip Test pin Test

9 CLK I 16.9344 MHz clock input
10 VSS1 - Ground
11 YSRDATA I Audio serial input data
12 YLRCK I Audio serial input LR clock Left channel Right channel
13 YSCK I Audio serial input bit clock
14 ZSCK O Audio serial output bit clock
15 ZLRCK O Audio serial output LR clock Left channel Right channel
16 ZSRDATA O Audio serial output data
17 YFLAG I Signal processor IC RAM overflow flag Overflow
18 YFCLK I Crystal-controlled frame clock
19 YBLKCK I Subcode block clock signal
20 NRESET I System reset pin Reset
21 ZSENSE O Microcontroller interface status output
22 VDD1 - VDD supply pin
23 YDMUTE I Forced mute pin Mute
24 YMLD I Microcontroller interface latch clock
25 YMDATA I Microcontroller interface serial data
26 YMCLK I Microcontroller interface shift clock
27 NTEST4 Ip Test pin Test
28 NCAS2 O DRAM CAS control
29 D2 I/O DRAM data input/output 2
30 D3 I/O DRAM data input/output 3
31 D0 I/O DRAM data input/output 0
32 D1 I/O DRAM data input/output 1
33 NWE O DRAM WE control
34 NRAS O DRAM RAS control
35 NTEST4 Ip Test pin Test
36 A8 O DRAM address 8
37 A7 O DRAM address 7
38 A6 O DRAM address 6
39 A5 O DRAM address 5
40 A4 O DRAM address 4
41 A0 O DRAM address 0
42 A1 O DRAM address 1
43 A2 O DRAM address 2
44 A3 O DRAM address 3

Ip : Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when a input mode)
And in case that only internal 1M DRAM is used, 28, 33, 34, 36 to 44 pin are high impedance, and 29 to 32 pin are input pull up mode.

Pin description

SM5901AF

preliminary

Parameter Symbol Rating Unit

Supply voltage V

DD - 0.3 to 4.6 V

Input voltage V

I VSS - 0.3 to VDD + 0.3 V

Storage temperature T

STG - 55 to 125 ˚C

Power dissipation P

D 600 mW

Soldering temperature T

SLD 255 ˚C

Soldering time

tSLD 10 sec

(VSS = 0V, VDD pin voltage = VDD)

(*1) Refer to pin summary on the next page.
Note. Values also apply for supply inrush and switch-off.

Parameter Symbol Rating Unit

Supply voltage V

DD 2.7 to 3.3 V

Operating temperature T

OPR 0 to 70 ˚C

(VSS = 0V, VDD pin voltage = VDD)

Parameter Pin Symbol Condition Rating Unit

Min Typ Max

Current consumption VDD I

DD (*A)SHPRF ON 60 mA

(*A)Through mode 60 mA

Input voltage CLK H level V

IH1 0.7VDD V

L level V

IL1 0.3VDD V

V

INAC AC coupling 0.3 VP-P

(*2,3,4,5) H level VIH2 0.7VDD V

L level V

IL2 0.3VDD V

Output voltage (*4,6) H level V

OH1 IOH = - 0.5 mA VDD - 0.4 V

L level V

OL1 IOL = 1 mA 0.4 V

(*5) H level V

OH2 IOH = - 0.5 mA VDD - 0.4 V

L level V

OL2 IOL = 1 mA 0.4 V

Input current CLK I

IH1 VIN = VDD 15 30 60 µA

I

IL1 VIN = 0V 15 30 60 µA

(*3,4) I

IL2 VIN = 0V 1.5 3 15 µA

Input leakage current (*2,3,4,5) I

LH1 VIN = VDD 1.0 µA

(*2,5) I

LL VIN = 0V 1.0 µA

Output leakage current (*7) I

ZH VOUT = VDD 1.0 µA

I

ZL VOUT= 0V 1.0 µA

(*A) VDD = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded,
SHPRF: Shock-proof,
typical values are for VDD = 3 V.

Electrical characteristics

Recommended operating conditions

DC characteristics

Standard voltage: (VDD = 2.7 to 3.3 V, VSS = 0 V, Ta = 0 to 70˚C)

Absolute maximum ratings

SM5901AF

preliminary

(*1) Pin function Clock input pin (AC input)

Pin name CLK

(*2) Pin function Schmitt input pins

Pin name YSRDATA, YLRCK, YSCK, YFLAG, YFCLK, NRESET,

YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK

(*3) Pin function Schmitt input pin with pull-up

Pin name NTEST1, NTEST2, NTEST3, NTEST4

(*4) Pin function I/O pins (Schmitt input with pull-up in input state)

Pin name UC1, UC2, UC3, UC4

(*5) Pin function I/O pins (Schmitt input in input state)

Pin name D0, D1, D2, D3

(*6) Pin function Outputs

Pin name ZSCK, ZLRCK, ZSRDATA, ZSENSE

(*7) Pin function Outputs

Pin name NCAS2, NWE, NRAS, A0, A1, A2, A3, A4, A5, A6, A7, A8

<Pin summary>

SM5901AF

preliminary

Parameter Symbol Condition Rating Unit

System clock Min Typ Max

Clock pulsewidth (HIGH level)

tCWH 26 29.5 125 ns

Clock pulsewidth (LOW level)

tCWL 26 29.5 125 ns

Clock pulse cycle

tCY 384fs 56 59 250 ns

CWH

t

CWL

t

CY

t

0.5V

DD

CLK

Parameter Symbol Rating Unit Condition

Min Typ Max

YSCK pulsewidth (HIGH level)

tBCWH 75 ns

YSCK pulsewidth (LOW level)

tBCWL 75 ns

YSCK pulse cycle

tBCY 150 ns

YSRDATA setup time

tDS 50 ns

YSRDATA hold time

tDH 50 ns

Last YSCK rising edge to YLRCK edge

tBL 50 ns

YLRCK edge to first YSCK rising edge

tLB 50 ns

0 2fs Memory system ON

YLRCK pulse frequency (MSON=H)

See note below. fs fs Memory system OFF

(MSON=L)

Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input

data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode
operation.

YSCK

YSRDATA

YLRCK

BCY

t

DS

t

DH

t

BCWH

t

BCWL

t

LB

t

BL

t

0.5V

DD

0.5V

DD

0.5V

DD

Serial input (YSRDATA, YLRCK, YSCK pins)

AC characteristics

Standard voltage: VDD = 2.7 to 3.3 V, VSS = 0 V, Ta = 0 to 70 °C
(*) Typical values are for fs = 44.1 kHz

System clock (CLK pin)

System clock input

SM5901AF

preliminary

Parameter Symbol Rating Unit

Min Typ Max

YMCLK LOW-level pulsewidth

tMCWL 30 + 2tCY ns

YMCLK HIGH-level pulsewidth

tMCWH 30 + 2tCY ns

YMDATA setup time

tMDS 30 + tCY ns

YMDATA hold time

tMDH 30 + tCY ns

YMLD LOW-level pulsewidth

tMLWL 30 + 2tCY ns

YMLD setup time

tMLS 30 + tCY ns

YMLD hold time

tMLH 30 + tCY ns

Rise time

tr 100 ns

Fall time

tf 100 ns

ZSENSE output delay

tPZS 100 + 3tCY ns

Note. tCY is the system clock cycle time (59ns typ).

YMDATA

YMCLK

ZSENSE

YMLD

YMDATA

YMCLK

YMLD

MDS

t

MDH

t

MCWL

t

MLS

t

MCWH

t

MLH

t

MLWL

t

PZS

t

0.5VDD0.5V

DD

0.5V

DD

0.5V

DD

0.5V

DD

0.5V

DD

0.3VDD 0.3VDD

0.7VDD 0.7VDD

f

t

r

t

Reset input (NRESET pin)

Parameter Symbol Rating Unit

Min Typ Max

First HIGH-level after supply voltage rising edge

tHNRST 0 tCY (Note)

NRESET pulsewidth

tNRST 64 tCY (Note)

Note. tCY is the system clock (CLK) input (384fs) cycle time.

tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz

NRESET

VDD

HNRST

t t

NRST

Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins)

SM5901AF

preliminary

Parameter Symbol Condition Rating Unit

Min Typ Max

ZSCK pulsewidth

tSCOW 15 pF load 1/96fs

ZSCK pulse cycle

tSCOY 15 pF load 1/48fs

ZSRDATA and ZLRCK output delay time

tDHL 15 pF load 0 60 ns
tDLH 15 pF load 0 60 ns

DRAM access timing (NRAS, NCAS2, NWE, A0 to A8, D0 to D3)

Parameter Symbol Condition Rating Unit

Min Typ Max

NRAS pulsewidth

tRASL 15 pF load 5 tCY(note)
tRASH 15 pF load 3 tCY

NRAS falling edge to NCAS2 falling edge tRCD 15 pF load 2 tCY

NCAS2 pulsewidth tCASH 15 pF load 5 tCY

tCASL 15 pF load 3 tCY

NRAS Setup time tRADS 15 pF load 1 tCY

falling edge to address Hold time tRADH 15 pF load 1 tCY

NCAS2 Setup time tCADS 15 pF load 1 tCY

falling edge to address Hold time tCADH 15 pF load 5 tCY

NCAS2 Setup time tCWDS 15 pF load 3 tCY

falling edge to data write Hold time tCWDH 15 pF load 3 tCY

NCAS2 Input setup tCRDS 40 ns

rising edge to data read Input hold

tCRDH 40 ns

NWE pulsewidth

tWEL 15 pF load 6 tCY

NWE falling edge to NCAS2 falling edge tWCS 15 pF load 3 tCY

Non compression 1.4 ms

Refresh cycle

1M 6-bit compression 3.7 ms

(fs = 44.1 kHz playback)

DRAM 5-bit compression 4.4 ms

tREF 4-bit compression 5.5 ms

Memory system ON

Non compression 2.7 ms

Decode sequence operation

4M 6-bit compression 7.3 ms

(RDEN=H)

DRAM 5-bit compression 8.8 ms

4-bit compression 10.9 ms

Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz

ZSCK

ZSRDATA

0.5V

DD

DLH

ZLRCK

0.5V

DD

DHL

tt

DLH

SCOW

tt

SCOW

t

SCOY

t

Serial output (ZSRDATA, ZLRCK, ZSCK pins)

SM5901AF

preliminary

NCAS2

(DRAM2 SELECT)

A0 to A9

D0 to D3
(WRITE)

NRAS

D0 to D3

(READ)

NWE

(WRITE)

tCY3

WCS

t

CY

t

6

CRDH

t

CRDS

t

CWDH

t

CWDS

t

CY

t3

CY

t3

CY

t5

CADH

t

CADS

t

RADH

t

RADS

t

CY

t1

CY

t1

CY

t1

CY

t5

CY

t3

CY

t2

t

RCD

t

CASL CASH

t

RASH

t

CY

t

3

CY

t5

RASL

t

WEL

t

DRAM access timing (when external DRAM is used)

SM5901AF

preliminary

Control
Input 1

Control
Input 2

Microcont-

roller

Interface

General

Port

Output Interface Input Interface

Attenuator Input Buffer

Decoder Encoder

1M DRAM

SM5901

YBLKCK

YFCLK
YFLAG

YMDATA

YMCLK

YMLD

ZSENSE

UC1 to UC4

YDMUTE

NRESET

NTEST

1, 2, 3, 4

CLK

NRAS

NCAS2

NWE

A0 to A8

D0 to D3

Through

Mode

Compression

Mode

ZLRCK

ZSCK

ZSRDATA

YLRCK

YSCK

YSRDATA

DRAM Interface

Block diagram