The SM5852FS is a digital signal processor IC that
performs DDBB (digital dynamic bass boost)
processing for use in digital audio reproduction
equipment. It is designed for use with a 44.1 kHz
sampling frequency.
FEATURES
■
2-channel processing
■
Improved DDBB mode channel separation
■
6 input-level dependent dynamic gain
characteristics
■
Serial input/output interface
2s complement, MSB first, 16-bit
1LRCIIpInput data sample rate (fs) clock input
2BCKIIpBit clock input
3DIIpSerial data input
4CLKIClock input
5VSS–Ground
6RSTNIpSystem reset initialization. Reset when LOW.
7TESTNIpTest mode input. Testing when LOW.
8MUTENIpMute input. Muting when LOW.
9DOUTOSerial data output
10BCKOOBit clock output
11LRCOOOutput data sample rate (fs) clock output
12VDD–3.2 to 5.5 V supply
13OPTIpNot used. Tie HIGH for normal operation.
14MOD1Ip
15MOD2Ip
16DB/DSIp
1
Gain characteristics switch inputs.
MOD1MOD2DB/DSGain mode
LOWLOWLOW18 dB
LOWLOWHIGH16 dB
LOWHIGHLOW14 dB
LOWHIGHHIGH12 dB
HIGHLOWLOW10 dB
HIGHLOWHIGH6 dB
HIGHHIGHLOWOff
HIGHHIGHHIGHOff
Description
1. Ip = Input pin with pull-up resistor. Accordingly, they can be left open for HIGH-level input.
RSTN should be set LOW at power-ON and after
reacquiring synchronization. Note that if RSTN is
LOW for longer than 1 µs, a through-current flows in
the internal dynamic circuits because the internal
clock is stopped. The through-current has no rated
value, so the reset pulse should be kept as short as
possible at all times other than at power-ON.
tRST
tRST
1.5V
1.5V
NIPPON PRECISION CIRCUITS—6
Serial input timing
SM5852FS
ParameterSymbolCondition
BCKI pulsewidtht
BCKI cycle timet
DI setup timet
DI hold timet
LRCI setup timet
LRCI hold timet
BCKI
tBCIWtBCIW
DI
BCIW
BCIY
DIS
DIH
LIS
LIH
tBCIY
Rating
Unit
mintypmax
100––ns
200––ns
75––ns
75––ns
75––ns
75––ns
1.5V
1.5V
tDIS
LRCI
tLIS
tDIH
1.5V
tLIH
DB/DS, OPT
ParameterSymbolCondition
Minimum pulsewidtht
mintypmax
W
2/fs––ns
Rating
Unit
When DB/DS or OPT change state, the input level must be constant for a minimum of 2/fs (2 × LRCI cycle
time). Input levels of duration less than 2/fs may be ignored.
The DDBB function emphasizes the low-frequency
components of the input signal by picking out the
low-frequency components and passing them
through a DDBB 3rd-order IIR low-pass filter and
then changing the gain for the low-frequency
components.
Two independent DDBB filters are used, one for
each the left and right channels, to maintain full
channel separation. The DDBB boost is determined
by DB/DS, MOD1 and MOD2.
MOD1MOD2DB/DSGain mode
LOWLOWLOW18 dB
LOWLOWHIGH16 dB
LOWHIGHLOW14 dB
LOWHIGHHIGH12 dB
HIGHLOWLOW10 dB
HIGHLOWHIGH6 dB
HIGHHIGHLOWOff
HIGHHIGHHIGHOff
Soft Muting
DB/DS Switching Shock Noise
The soft muting function is also activated to
eliminate switching shock noise when DB/DS
changes state. When DB/DS changes state, the
attenuation changes to −∞ dB, the internal circuit
settings are activated and then soft muting is
released. Therefore, a maximum time of
approximately 46.4 ms is required to change the
compression mode. Of course, if the attenuation is
already −∞ dB after soft muting using MUTEN, then
no time is required to change compression mode.
Reset Initialization
RSTN should be set LOW at power-ON and after
reacquiring synchronization. Note that if RSTN is
LOW for longer than 1 µs, a through-current flows in
the LSI’s internal dynamic circuits because the
internal clock is stopped. The through-current has no
rated value, so the reset pulse should be kept as short
as possible at all times other than at power-ON.
When RSTN goes from LOW to HIGH, initialization
hold is released and the initialization routine first
resets the internal data over an interval of 4fs. During
the initialization routine, the output data is forcibly
muted so that there is no output signal.
Soft muting is active when MUTEN is LOW. When
MUTEN is LOW, the attenuation changes smoothly
from 0 to −∞ dB in 1024/fs, or approximately 23.2
ms.
When MUTEN goes HIGH, soft muting is released
and the attenuation changes smoothly from −∞ to 0
dB, again taking approximately 23.2 ms.
Also, if a MUTEN transition occurs while the
attenuation is changing, the attenuation then changes
smoothly in the direction specified by the new level
of MUTEN.
NIPPON PRECISION CIRCUITS—10
SM5852FS
INPUT/OUTPUT TIMING
Input Timing
LRCO
BCKO
MSB
Lch
LSB
MSB
Rch
LSB
DOUT
There must be a minimum of 16 BCKI clock cycles to read in a single word of data.
Data on DI is input in sync with the falling edge of BCKI in 16-bit serial, MSB first, 2s complement
format.
Output Timing
LRCO
BCKO
MSB
Lch
DOUT
Shaded areas represent intervals of invalid data.
LSB
MSB
Rch
LSB
NIPPON PRECISION CIRCUITS—11
APPLICATON CIRCUIT
SM5852FS
X'tal(16.9344 MHz)
SONY
CXD1125
1130
1135
PSSL SLOB
XTAI
LRCK
C210
DATA
LRCI
BCKI
DI
SM5852FS
CLK
RSTN
TESTN
MUTEN
DB/DS
MOD2
MOD1
OPT
LRCO
BCKO
DOUT
XTI
CKO
LRCI
BCKI
DIN
XTO
SM5841
Microcontroller
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warr anty that such applications will be suitab le for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2 chome
Koto-ku, Tokyo 135-8430, Japan
NIPPON PRECISION CIRCUITS INC.
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9623BE 1998.08
NIPPON PRECISION CIRCUITS—12
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