High-fidelity Digital Audio, Multi-function Digital Filter
OVERVIEW
The SM5847AF is a 4/8-times oversampling (interpolation), 2-channel, linear-phase FIR, multi-function digital filter for digital audio reproduction
equipment. It features independent left and rightchannel digital deemphasis filters and soft muting
function.
The input/output interface supports input data in
16/18/20/24-bit words, and output data in
18/20/22/24-bit words in either 4-times or 8-times
oversampling selectable output mode.
FEATURES
■
Left/right-channel (2-channel processing)
■
4-times/8-times oversampling (interpolation)
• 8-times interpolation filter
- 3-stage linear-phase FIR configuration
1st stage (fs to 2fs): 169-tap
2nd stage (2fs to 4fs): 29-tap
3rd stage (4fs to 8fs): 17-tap
-≤ ±0.00002 dB passband ripple (0 to
0.4535fs)
-≥ 117 dB stopband attenuation (0.5465fs to
7.4535fs)
• 4-times interpolation filter
- 2-stage linear-phase FIR configuration
1st stage (fs to 2fs): 169-tap
2nd stage (2fs to 4fs): 29-tap
The internal system clock operates at either 192fs or
256fs selectable speed (where fs is the audio sampling frequency). Plus, the divide-by 1, 2, or 4
counter settings means that external clocks of 768fs/
384fs/192fs (192fs input) and 1024fs/512fs/256fs
(256fs input) are supported.
The SM5847AF operates from a single 3 to 5 V supply, and is available in 44-pin QFP packages.
• 2s complement, MSB first
• 3 selectable formats
- LR alternating, 16/18/20/24-bit serial, rightjustified data
- LR alternating, 24-bit serial, left-justified
data
- LR simultaneous, 24-bit serial, left-justified
data
■
Output data format
• 2s complement, MSB first, LR simultaneous
• 18/20/22/24-bit serial
• BCKO burst (NPC format)
■
Dither round-off processing
• Dither round-off ON/OFF selectable
■
25-bit internal data word length
■
Internal system clock
• 192fs/256fs selectable
• Maximum operating frequency
192fs mode:37 MHz max (5 V)
20.7 MHz max (3 V)
256fs mode: 27.6 MHz max (5 V)
25 MHz max (3 V)
■
Jitter-free function
• Jitter-free/Sync mode selectable
■
Crystal oscillator circuit built-in
■
3 to 5 V supply
■
44-pin plastic QFP
■
CMOS process
ORDERING INFORMATION
De vicePack ag e
SM5847AF44-pin QFP
NIPPON PRECISION CIRCUITS—1
PINOUT
(T op V iew)
SM5847AF
OMD
DOR
DOL
WCKO
BCKO
VSS
VSSAC
VDDAC
VDD
DG
NC
PACKAGE DIMENSIONS
(Unit: mm)
44-pin plastic QFP
MUTEL
DITHN
MUTER
42
43
44
1
2
3
4
5
6
7
8
9
10
11
1213141516171819202122
VSS
CKO
VDD
FSEL2
41
SM58 4
7AF
XTO
FSEL1
40
XTI
VSS
39
VSS
VDD
38
VDD
DEMPL
DEMPR
36
37
LRCI
DI/INF2N
CKDV2
CKDV1
34
35
NC
BCKI
33
RSTN
32
SYNCN
31
OW2N
30
OW1N
29
VDD
28
VSS
27
IW2N/DIR
26
IW1N/DIL
25
INF1N
24
CKSLN
23
NC
0.30
+
−
12.80
+
10.00 0.30
+
0.17 0.05
+
12.80
0.30
−
+
10.00 0.30
−
0.17
+
0.05
−
(1.40)
−
0 to 10
0.35
4
−
C 0.7
+
0.10
−
0.20 M
0.60
+
0.20
−
(1.40)
−
0.80
0.15
+
−
0.15 0.05
0.20
+
−
1.50 0.10
NIPPON PRECISION CIRCUITS—2
BLOCK DIAGRAM
SM5847AF
XTI
XTO
CKO
CKSLN
CKDV1
CKDV2
SYNCN
RSTN
DEMPL
DEMPR
FSEL1
FSEL2
MUTEL
MUTER
System
Clock
Timing
Controller
Deemphasis
Controller
Mute
Controller
LRCI
BCKI
Input Data
Interface
Filter and
Attenuation
Arithmetic
Block
Output Data
Interface
Block
DI/INF2N
IW1N/DIL
IW2N/DIR
INF1N
DITHN
VDD
VSS
VDDAC
VSSAC
OMD
OW1N
OW2N
DG
BCKO
DOL
WCKO
DOR
NIPPON PRECISION CIRCUITS—3
SM5847AF
PIN DESCRIPTION
NumberNameI/ODescription
1
1OMDIp
2DORO
3DOLO
4WCKOO
5BCKOO
6VS S–Ground
7VSSAC–Ground
8V D D AC–Supply voltage
9V D D–Supply voltage
10D GO
11N C–No internal connection (must be open)
12CKOO
13VS S–Ground
14V D D–Supply voltage
15X TOOOscillator output
16XTIIOscillator input/master clock input
17VS S–Ground
18V D D–Supply voltage
19LRCII
20DI/INF2NI
21BCKII
22N C–No internal connection (must be open)
23N C–No internal connection (must be open)
24CKSLNIp
25INF1NIp
26IW1N/DILIp
27IW2N/DIRIp
28VS S–Ground
29V D D–Supply voltage
30OW1NIp
31OW2NIp
32SYNCNIp
33RSTNIp
34CKDV1Ip
35CKDV2Ip
36DEMPRIp
37DEMPLIp
38V D D–Supply voltage
39VS S–Ground
40FSEL1Ip
41FSEL2Ip
42MUTELIp
43MUTERIp
44DITHNIp
1. Schmitt input, TTL level
2. TTL level
Ip = Pull-up input
Output data rate (4fs/8fs) select pin
2
Right-channel data output
2
Left-channel data output
2
Word clock output
2
Bit clock output
2
Deglitched signal output
2
Master clock output
1
Input data sample rate (fs) clock input
1
Data input/input format select pin 2
1
Bit clock input
2
Master clock frequency (192fs/256fs) select pin
2
Input format select pin 1
1
Input data word length select pin 1/left-channel data input
1
Input data word length select pin 2/right-channel data input
2
Output data word length select pin 1
2
Output data word length select pin 2
2
Sync mode select pin
1
Reset input
1
Internal system clock frequency divider set pin 1
1
Internal system clock frequency divider set pin 2
1
Right-channel deemphasis ON/OFF pin
1
Left-channel deemphasis ON/OFF pin
1
Deemphasis filter sample rate (fs) select pin 1
1
Deemphasis filter sample rate (fs) select pin 2
1
Left-channel mute ON/OFF pin
1
Right-channel mute ON/OFF pin
1
Output data dither ON/OFF pin
NIPPON PRECISION CIRCUITS—4
−
+
(°
−
−
°
≤
°
°
−
°C
−
−
−
−
−
−
−
SM5847AF
SPECIFICATIONS
Absolute Maximum Ratings
V
= V
SS
Supply voltage range
Input voltage rangeV
Storage temperature rangeT
Po w er dissipationP
1. Supply lines for VDD and VDD AC, and ground lines for VSS and VSSAC, should be connected on the printed circuit board to prevent device breakdo wn due to potential difference when the power is applied.
= 0 V, V
SSAC
ParameterSymbolConditionRatingUnit
1
DD
= V
DDAC
V
DD
, V
DDAC
I
stg
D
70
C900
≤ 85
C700
0.3 to 6.5V
V
SS
0.3 to V
55 to 125
0.3V
DD
C
mW
Recommended Operating Conditions
V
= V
SS
Supply voltage range
Operating temperature rangeT
1. The minimum required operating voltage and consequent operating temperature vary with the maximum operating frequency and sampling mode
selected, as shown in the following table.
V
= V
SS
Sampling frequency
1. Mode with internal frequency divider ratio set to 1 (CKDV1 = CK DV2 = L OW) .
The crystal oscillator frequency or external clock input master clock frequency ratings are described in the preceding tables, but it is the internal system clock frequency rating, set by the internal frequency divider
(CKDV1, CKDV2), that must be satisfied. The master clock frequency is a multiple of the sampling frequency
fs.
CKDV1 = CKDV2 = LOW (internal system clock frequency = XTI input frequency),
VSS = V
256fs (CKSLN = LOW, CKDV1 = LOW, CKDV2 = LOW)
System clock frequencyf
192fs (CKSLN = HIGH, CKDV1 = LOW , CKDV2 = LOW)
System clock frequencyf
= 0 V, Ta = −40 to 85 °C
SSAC
ParameterSymbolCondition
SYS1
SYS2
VDD = V
VDD = V
VDD = V
Ta = −40 to 70 °C
VDD = V
= 4.50 to 5.25 V0.256–27.6
DDAC
= 3.00 to 5.25 V0.256–2 5
DDAC
= 4.75 to 5.25 V,
DDAC
= 3.00 to 5.25 V0.384–20.7
DDAC
Rating
mintypmax
0.384–3 7
Unit
MHz
MHz
NIPPON PRECISION CIRCUITS—7
SM5847AF
Serial input timing (BCKI, LRCI, DI/INF2N, IW1N/DIL, IW2N/DIR)
VSS = V
BCKI pulse cyclet
BCKI HIGH-level pulsewidtht
BCKI LOW-level pulsewidtht
DI, DIL, DIR setup timet
DI, DIL, DIR hold timet
Last BCKI rising edge to LRCI edget
LRCI edge to first BCKI rising edget
= 0 V, Ta = −40 to 85 °C
SSAC
ParameterSymbolCondition
IBCY
BCWH
BCWL
DS
DH
BL
LB
Rating
Unit
mintypmax
Note 155––
nsNote 280––
Note 3100––
Note 125––
nsNote 235––
Note 345––
Note 125––
nsNote 235––
Note 345––
Note 110––
nsNote 220––
Note 330––
Note 110––
nsNote 220––
Note 330––
Note 110––
nsNote 220––
Note 330––
Note 110––
nsNote 220––
Note 330––
1. CKSLN = HIGH (192fs), VDD = V
2. CKSLN = LOW (256fs), VDD = V
CKSLN = HIGH (192fs), VDD = V
3. CKSLN = LOW (256fs), V
DD
= V
BCKI
DI
DIL
DIR
LRCI
= 4.75 to 5.25 V, Ta = −40 to 70 °C
DDAC
= 4.50 to 5.25 V
DDAC
= 3.00 to 4.75 V
DDAC
= 3.00 to 4.50 V
DDAC
tDS
tIBCY
tBCWHtBCWL
tDH
tBL
NIPPON PRECISION CIRCUITS—8
1.5V
1.5V
tLB
1.5V
Reset timing (RSTN)
SM5847AF
VDD = V
= 3.00 to 5.25 V, VSS = V
DDAC
= 0 V, Ta = −40 to 85 °C
SSAC
ParameterSymbolCondition
RSTN LOW-level reset pulsewidtht
1. t
is equal to 1/f
MCK
XTI
or 1/f
. For example, t
OSC
RST
= 54 ns when f
RST
= 37 MHz.
XTI
RSTN
Output timing (CKO, BCKO, WCKO, DOL, DOR, DG)
VDD = V
XTI falling edge to CKO falling edge delayt
BCKO falling edge to WCKO, DOL, DOR,
DG delay
B C K O r ising edge to W CK O falling edget
W CK O falling edge to BCKO rising edget
BC KO per iodt
BC KO HIGH-level pulsewidtht
B CK O L OW -level pulsewidtht
DOL, DOR setup timet
DOL, DOR hold timet
B C K O r ising edge to W CK O falling edget
W CK O falling edge to BCKO rising edget
BC KO per iodt
BC KO HIGH-level pulsewidtht
B CK O L OW -level pulsewidtht
DOL, DOR setup timet
DOL, DOR hold timet
= 4.75 to 5.25 V, VSS = V
DDAC
= 0 V, Ta = −40 to 70 °C, CL = 50 pF
SSAC
ParameterSymbolCondition
XTO
VDD = V
DDAC
Ta = −40 to 85 °C
t
BDO
WOH
Output mode: 8fs
WOS
OBCY
OBCH
OBCL
ODS
ODH
WOH
WOS
OBCY
OBCH
OBCL
ODS
ODH
OMD = HIGH (fs = 192 kHz)
External clock input:
XTI = 27 ns (37 MHz),
CKSLN = HIGH (192fs)
Divider ratio: 1
CK DV1 = CKDV2 = LOW
Output data length: 24 bits
OW1N = OW2N = LOW