NPC SM5165AV Datasheet

−

SM5165AV

NIPPON PRECISION CIRCUITS INC.

OVERVIEW

The SM5165AV is a PLL synthesizer IC developed
for application in pagers and fabricated using NPC’s
Molybdenum-gate CMOS process. It incorporates
independently-controlled reference frequency and
operating frequency dividers, and operates from a
low-voltage supply to realize low power dissipation.

FEATURES

■

Up to 90 MHz operating frequency
(V

= V

DD1

■

Up to 100 MHz operating frequency
(V

= V

DD1

■

Supply voltages

•V

DD1

(prescaler, counters)

•V

DD3

■

40 to 16376 reference frequency divider ratio
range (with 1/8 prescaler built-in)

■

1056 to 262143 operating frequency divider ratio
range

■

Power-save function for reduced power
dissipation

■

10 to 60 ° C operating temperature range

■

16-pin VSOP

■

Molybdenum-gate CMOS process

= 0.95 V)

DD2

= 1.00 V)

DD2

= V

= 0.95 to 1.5 V

DD2

= 2.0 to 3.3 V (charge pump)

PLL Synthesizer IC

PINOUT

PACKAGE DIMENSIONS

Unit: mm

16-pin VSOP

(TOP VIEW)

VDD1

FIN
VSS

RO

TEST

DO

DB
NC

16pin VSOP

1

8

4.4 0.2

6.4 0.2

5165
AV

16

XIN
XOUT
LE
CLK
DATA
OPR
VDD2

9

VDD3

APPLICATIONS

■

Pagers

ORDERING INFOMATION

Device Package

SM5165AV 16pin VSOP

0.22

5.1 0.2

+ 0.10

- 0.05

+ 0.10

- 0.05

0.15

010

0.65

1.15 0.1

0.10 0.05

NIPPON PRECISION CIRCUITS—1

0.5 0.2

∗

BLOCK DIAGRAM

SM5165AV

XIN

XOUT

VDD2

VDD2

AREA

DATA

CLK

SELECTER

LE

∗

OPR

VDD1

FIN

PIN DESCRIPTION

1/8

PRESCALER

VDD1

11 BIT

R COUNTER

AREA

11 BIT LATCH

LATCH

22 BIT

SHIFT REGISTER

18 BIT LATCH

VDD1

AREA

Protection diodes are connected to VDD3. Logic level : V

18 BIT

N COUNTER

LEVEL

SHIFTER

PHASE

DETECTOR

LEVEL

SHIFTER

GENERATOR

VDD2

AREA

SHIFTER

WINDOW

to V

DD2

DD3

LEVEL

VDD3

AREA

BOOSTER

S. G.

CHARGE

PUMP

TEST
RO

VDD3

DB

DO

VDD2

AREA

VSS

Number Name I/O Description

1 VDD1 – Reference frequency and comparator frequency prescaler and counter 1 V supply

2 FIN I

3 VSS1 – Ground pin

4ROO

5 TEST I

6DOO

7 DB O Booster signal output for faster locking
8 NC – No connection
9 VDD3 – Phase comparator, charge pump and booster signal 3 V supply

10 VDD2 –

11 OPR I

12 DATA I Control data input pin
13 CLK I Control data clock input pin
14 LE I Control data latch enable signal input pin
15 XOUT O Reference frequency divider crystal oscillator connection pins. Alternatively, an external clock input can

16 XIN I

Operating frequency divider input pin.
Feedback resistor b uilt-in f or AC-coupled inputs.

Test output.
LOW-level output for (1, 0) test bit patter. Leave open for normal operation.

Test pin.
Pull-down resistor built-in. Leave open or connect to ground for normal operation.

Phase detector output pin.
Built-in charge pump and tristate output means that this output can be connected to a low-pass filter.
The output polarity is preset for connection to a passive filter.

Shift register and latch 1 V supply.
Should be kept at the same potential as VDD1.

Power-save control pin.
Operation when HIGH, standby mode when LOW.

be connected to XIN. The clock is also output on XOUT.
Feedback resistor b uilt-in f or AC-coupled inputs.

NIPPON PRECISION CIRCUITS—2

SPECIFICATIONS

Absolute Maximum Ratings

V

= 0 V

SS

Parameter Symbol Condition Rating Unit

Supply voltage

Input voltage range

Storage temperature range T
Power dissipation P
Soldering temperature T
Soldering time t

V

V

V
V

DD1,2

DD3

IN1

IN2

stg

D

sld

sld

−

−

−

−

−

°

°

−

° C

SM5165AV

0.3 to 2.0 V

0.3 to 7.0 V
FIN, XIN, TEST V
OPR, CLK, DATA, LE V

SS

SS

0.3 to V

0.3 to V

+ 0.3 V

DD1,2

+ 0.3 V

DD3

40 to 125

150 mW
255

10 s

C

C

Recommended Operating Conditions

V

= 0 V

SS

Parameter Symbol Condition Rating Unit

V

Supply voltage

Storage temperature range T

DD1,2

V

DD3

stg

Electrical Characteristics

V

= 0 V, V

SS

VDD1, VDD2 operating current
consumption

VDD3 operating current consumption I
VDD2 standby current I
VDD3 standby current I

FIN maximum operating input frequency f

XIN maximum operating input frequency f
FIN minimum operating input frequency f
XIN minimum operating input frequency f

FIN input amplitude V

XIN input amplitude V
OPR, CLK, DATA, LE LOW-level input

voltage

DD1

= V

= 0.95 to 1.5 V, V

DD2

DD3

Parameter Symbol Condition

Note 1. – 0.70 1.10

I

DD1

Note 2. – 0.75 1.20

DD2

DD3

Note 3.

DD4

max1

max2

300 mVp-p sine
wave

300 mVp-p sine wave. Note 4. 16 – – MHz
300 mVp-p sine wave – – 40 MHz

min1

300 mVp-p sine wave. Note 4. – – 9 M Hz

min2

V

DD1,2

AC coupling

FIN

V

DD1,2

AC coupling
f

XIN

V

IL

= 16 MHz, AC coupling 0.3 – – Vp-p

XIN

= 2.0 to 3.3 V, T

V

DD1,2

1.50 V
V

DD1,2

1.50 V

= 0.95 to 1.50 V, f

= 1.00 to 1.50 V, f

FIN

FIN

= − 10 to 60 ° C

a

= 0.95 to

= 1.00 to

= 90 MHz,

= 100 MHz,

0.95 to 1.5 V

2.0 to 3.3 V
10 to 60

Rating

Unit

min typ max

mA

–10–µA
– 0.1 – µA
– 0.01 10.0 µA

90 – –

MHz

100 – –

0.3 – –
Vp-p

0.3 – –

– – 0.2V

DD2

V

NIPPON PRECISION CIRCUITS—3