Noty an86f Linear Technology

Application Note 86

January 2001

A Standards Lab Grade 20-Bit DAC with 0.1ppm/°C Drift

The Dedicated Art of Digitizing One Part Per Million

Jim Williams
J. Brubaker
P. Copley
J. Guerrero
F. Oprescu

INTRODUCTION

Significant progress in high precision, instrumentation
grade D-to-A conversion has recently occurred. Ten years
ago 12-bit D-to-A converters (DACs) were considered
premium devices. Today, 16-bit DACs are available and
increasingly common in system design. These are true
precision devices with less than 1LSB linearity error and
1ppm/°C drift.1 Nonetheless, there are DAC applications
that require even higher performance. Automatic test
equipment, instruments, calibration apparatus, laser trim­mers, medical electronics and other applications often
require DAC accuracy beyond 16 bits. 18-bit DACs have
been produced in circuit assembly form, although they are
expensive and require frequent calibration. 20 and even
23+ (0.1ppm!) bit DACs are represented by manually
switched Kelvin-Varley dividers. These devices, although
amazingly accurate, are large, slow and extremely costly.
Their use is normally restricted to standards labs.2 A
useful development would be a practical, 20-bit (1ppm)
DAC that is easily constructed and does not require
frequent calibration.

20-Bit DAC Architecture

Figure 1 diagrams the architecture of a 20-bit (1ppm) DAC.
This scheme is based on the availability of a true 1ppm
analog-to-digital converter with scale and zero drifts be­low 0.02ppm/°C. This device, the LTC®2400, is used as a
feedback element in a digitally corrected loop to realize a
20-bit DAC.

3

In practice, the “slave” 20-bit DAC’s output is monitored
by the “master” LTC2400 A-to-D, which feeds digital
information to a code comparator. The code comparator

differences the user input word with the LTC2400 output,
presenting a corrected code to the slave DAC. In this
fashion, the slave DAC’s drifts and nonlinearity are con­tinuously corrected by the loop to an accuracy determined
by the A-to-D converter and V

4

. The sole DAC require-

REF

ment is that it be monotonic. No other components in the
loop need to be stable.

V

REF

20-BIT

USER

INPUT

CODE

COMPARATOR

CORRECTED

CODE

DIGITAL

CODE

Figure 1. Conceptual Loop-Based 20-Bit DAC. Digital
Comparison Allows A-to-D to Correct DAC Errors. LTC2400
A-to-D’s Low Uncertainty Characteristics Permit 1ppm
Output Accuracy

, LTC and LT are registered trademarks of Linear Technology Corporation.

Note 1: See Appendix A, “A History of High Accuracy Digital-to-Analog
Conversion,” for a review of high accuracy digital-to-analog conver­sion.

Note 2: Consult Appendix C, “Verifying Data Converter Linearity to
1ppm,” for discussion on Kelvin-Varley dividers. Also, see Appendix A,
“A History of High Accuracy Digital-to-Analog Conversion.”

Note 3: The LTC2400 analog-to-digital converter is profiled in
Appendix␣ B, “The LTC2400—A Monolithic 24-Bit Analog-to-Digital
Converter.”

Note 4: D-to-A converters have been placed in loops to make A-to-D
converters for a long time. Here, an A-to-D converter feeds back a loop
to form a D-to-A converter. There seems a certain justified symmetry
to this development. Turnabout is indeed fair play.

FEEDBACK

CODE

20-BIT

“SLAVE”

DAC

LTC2400

“MASTER”

A-TO-D

V

IN

20-BIT
(1PPM)
ANALOG
OUTPUT

V

OUT

AN86 F01

AN86-1

Application Note 86

This loop has a number of desireable attributes. As men­tioned, accuracy limitations are set by the A-to-D con­verter and its reference. No other components need be
stable. Additionally, loop behavior averages low order bit
indexing and jitter, obviating the loop’s inherent small­signal instability. Finally, classical remote sensing may be
used or digitally based sensing is possible by placing the
A-to-D converter at the load. The A-to-D’s SO-8 package
and lack of external components makes this digitally
incarnated Kelvin sensing scheme practical.

5

Circuitry Details

Figure 2 is a detailed schematic of the 1ppm DAC. The
slave DAC is comprised of two DACs. The upper 16 bits of
the code comparator’s output are fed to a 16-bit DAC
(“MSB DAC”), while the lower bits are converted by a
separate DAC (“LSB DAC”). Although a total of 32 bits are
presented to the two DACs, there are 8 bits of overlap,
assuring loop capture under all conditions. The composite

20-BIT

USER

INPUT

CODE

COMMAND

INPUTS FROM

CODE COMPARATOR

CODE

COMPARATOR

(SEE APPENDIX D

FOR DETAILS)

CORRECTED
CODE OUT—
24-BIT WORD

+

LT1001

–

A4

24-BIT

FEEDBACK

CODE

5V 5V

SERIAL
DIGITAL
OUT

LTC2400

A-TO-D

5V

DACs’ resultant 24-bit resolution provides 4 bits of index­ing range below the 20th bit, ensuring a stable LSB of
1ppm of scale. A1 and A2 transform the DAC’s output
currents into voltages, which are summed at A3. A3’s
scaling is arranged so that the correction loop can always
capture and correct any combination of zero- and full­scale errors. A3’s output, the circuit output, feeds the
LTC2400 A-to-D. The LT®1010 provides buffering to drive
loads and cables. The A-to-D’s digital output is differenced
against the input word by the code comparator, which
produces a corrected code. This corrected code is applied
to the MSB and LSB DACs, closing a feedback loop.6 The
loop’s integrity is determined by A-to-D converter and
voltage reference errors.7 The resistor and diodes at the
5V powered A-to-D protect it from inadvertent A3 outputs
(power up, transient, lost supply, etc.). A4 is a reference
inverter and A5 provides a clean ground potential to both
DACs.

(SEE APPENDIX I

REF

FOR OPTIONS)

REF

IN

CS

1k

1N5817

1N5817

100pF

5V

LD
WR

ML

BYTE

REF

R

R

LTC1599

CLVL CLR

5V

REF R

OSRFS

–

A5

LT1001

FB

I

OUT

–

I

* = 1% METAL FILM

DATA

INPUTS

+

DATA

INPUTS

BYTE

LD
WR

5V

CLVL

LTC1599

ROSCLR

V

REF

REFML

5V

R

FB

I

OUT

–

I

Figure 2. Detail of 1ppm DAC. Composite DAC Is Comprised of Two DAC Values Summed
at Output Amplifier. LTC2400 A-to-D and Code Comparator Furnish Stabilizing Feedback

Note 5: One wonders what Lord Kelvin’s response would be to the

digizatation of his progeny. Such uncertainties are the residue of progress.
Note 6: The code comparator is detailed in Appendix D, “A Processor

Based Code Comparator.”

MSB DAC

100pF

–

A1

LT1001

+

2k*

+

LT1001

15V

A3

OUTPUT

AMPLIFIER

LT1010

–

LSB DAC

100pF

–

LT1001

4.12M*

A2

0.1µF

4.12M*

–15V

2k*

+

Note 7: Voltage reference options are discussed in Appendix I,
“Voltage References.” For tutorial on the LTC2400, refer to
Appendix␣ B.

OUTPUT

AN86 F02

AN86-2

Application Note 86

Linearity Considerations

A-to-D linearity determines overall DAC linearity. The
A-to-D has about ±2ppm nonlinearity. In applications
where this error is permissible, it may be ignored. If 1ppm
linearity is required, it is obtainable by correcting the
residual linearity error with software techniques. Details
on LTC2400 linearity and this feature are presented in
Appendices D and E.

DC Performance Characteristics

Figure 3 is a plot of linearity vs output code. The data
shows linearity is within 1ppm over all codes.8 Output
noise, measured in a 0.1Hz to 10Hz bandpass, is seen in
Figure 4 to be about 0.2LSB.9 This measurement is
somewhat corrupted by equipment limitations, which set
a noise floor of about 0.2µV.

Dynamic Performance

The A-to-D’s conversion rate combines with the loop’s
sampled data characteristic and slow amplifiers to dictate
relatively slow DAC response. Figure 5’s slew response
requires about 150 microseconds.

Figure 6 shows full-scale DAC settling time to within 1ppm
(±5µV) requires about 1400 milliseconds. A smaller step
(Figure 7) of 500µV needs only 100 milliseconds to settle
within 1ppm.

10

Conclusion

Summarized 1ppm DAC specifications appear in Figure 9.
These specifications should be considered guidelines, as
the options and variations noted will affect performance.
Consult the appropriate appendices for design specifics
and trade-offs.

1.0
INDICATED MEASUREMENT RESULTS

0.5

0

SHADED REGION DELINEATES

LINEARITY ERROR (ppm)

–0.5

MEASUREMENT UNCERTAINTY DUE TO
DAC OUPUT NOISE AND
INSTRUMENTATION LIMITATIONS

–1.0

0

262,144 524,288 786,432 1,048,576

DIGITAL INPUT CODE

Figure 3. Linearity Plot Shows No
Error Outside 1ppm for All Codes

AN86 F03

500nV/DIV

2s/DIV AN86 F04.tif

Figure 4. Output Noise Indicates Less Than 1µV,
About 0.2LSB. Measurement Noise Floor, Due
to Equipment Limitations, Is 0.2µV

Note 8: Establishing and maintaining confidence in a 1ppm linearity

measurement is uncomfortably close to the state of the art. The
technique used is shown in Appendix C, “Verifying Data Converter
Linearity to 1ppm.”

Note 9: Noise measurement considerations appear in Appendix H,
“Microvolt Level Noise Measurement.”

Note 10: Measuring DAC settling time to 1ppm is by no means
straightforward, even at the relatively slow speed involved here. See
Appendix G, “Measuring DAC Settling Time.”

AN86-3

Application Note 86

1V/DIV

50µs/DIV AN86 F05.tif

5µV/DIV

500ms/DIV AN86 F06.tif

Figure 5. DAC Output Full-Scale Slew Characteristics Figure 6. High Resolution Settling Detail After a Full-Scale Step.

Settling Time Is 1400 Milliseconds to Within 1ppm (±5µV)

PARAMETER SPECIFICATION

Resolution 1ppm

5µV/DIV

50ms/DIV AN86 F07.tif

Figure 7. Small Step Settling Time Measures 100
Milliseconds to Within 1ppm (±5µV) for a 500µV
Transition

Full-Scale Error 4ppm of V

(Trimmable to 1ppm by V

Full-Scale Error Drift 0.04ppm/°C Exclusive of Reference

(0.1ppm/°C with LTZ1000A Reference

Offset Error 0.5ppm
Offset Error Drift 0.01ppm/°C
Nonlinearity ±2ppm, Trimmable to Less Than 1ppm
Output Noise 0.2ppm

(≈0.9µV, 0.1Hz to 10Hz BW)

Slew Rate 0.033V/µs
Settling Time—Full-Scale Step 1400 Milliseconds
Settling Time—500µV Step 100 Milliseconds
Output Voltage Range 0V to 5V. For Other Ranges See Note 3

Note 1: See Appendix I
Note 2: See Appendix E
Note 3: See Appendices E and F

REF

Adjustment)

REF

1

)

2

AN86-4

Figure 8. Summarized Specifications for the 20-Bit DAC

Note: This Application Note was derived from a manuscript originally
prepared for publication in EDN magazine.

Application Note 86

REFERENCES

1. Linear Technology Corporation, “LTC2400 Data Sheet,”
Linear Technology Corporation, January 1999.

2. Linear Technology Corporation, “LTC2410 Data Sheet,”
Linear Technology Corporation, April 2000.

3. Keithley Instruments, “Low Level Measurements,”
Keithley Instruments, 1984.

4. Williams, J., “Testing Linearity of the LTC2400 24-Bit
A/D Converter,” Linear Technology Corporation, De­sign Solution 11, November 1999.

5. Seebeck, T. Dr., “Magnetische Polarisation der Metalle
und Erze durch Temperatur-Differenz,” Abhaandlungen
der Preussischen Akademic der Wissenschaften
(1822–1823), pp. 265–373.

6. Williams, J., “Component and Measurement Advances
Ensure 16-Bit DAC Settling Time,” Linear Technology
Corporation, Application Note 74, July 1998.

7. Lee, M., “Understanding and Applying Voltage Refer­ences,” Linear Technology Corporation, Application
Note 82, November 1999.

8. Williams, J., “Applications Considerations and Cir­cuits for a New Chopper-Stabilized Op Amp,” Linear
Technology Corporation, Application Note 9, August

1987.

9. Huffman, B., “Voltage Reference Circuit Collection,”
Linear Technology Corporation, Application Note 42,
June 1991.

10. Spreadbury, P. J., “The Ultra-Zener—A Portable Re­placement for the Weston Cell?” IEEE Transactions on
Instrumentation and Measurement, Vol. 40, No. 2,
April 1991, pp. 343–346.

11. Williams, J., “Thermocouple Measurement,” Linear
Technology Corporation, Application Note 28, Febru­ary 1988.

12. Hueckel, J. H., “Input Connection Practices for Differ­ential Amplifiers,” Neff Inst. Corporation, Duarte, Cali­fornia.

13. Gould Inc., “Elimination of Noise in Low Level Cir­cuits,” Gould Inc., Instrument Systems Division, Cleve­land, Ohio.

14. Williams, J., “Prevent Low Level Amplifier Problems,”
Electronic Design, February 15, 1975, p. 62.

15. Pascoe, G., “The Choice of Solders for High Gain
Devices,” New Electronics (Great Britain), February 6,

1977.

16. Pascoe, G., “The Thermo-E.M.F. of Tin-Lead Alloys,”
Journal Phys. E, December 1976.

17. Brokaw, A. P., “Designing Sensitive Circuits? Don’t
Take Grounds for Granted,” EDN, October 5, 1975,
p.␣ 44.

18. Morrison, R., “Noise and Other Interfering Signals,”
John Wiley and Sons, 1992.

19. Morrison, R., “Grounding and Shielding Techniques
in Instrumentation,” Wiley-Interscience, 1986.

20. Vishay Inc., “Vishay Foil Resistors,” Vishay Inc., 1999.

AN86-5

Application Note 86

APPENDIX A

A HISTORY OF HIGH ACCURACY
DIGITAL-TO-ANALOG CONVERSION

People have been converting digital-to-analog quantities
for a long time. Probably among the earliest uses was the
summing of calibrated weights (Figure A1, left center) in
weighing applications. Early electrical digital-to-analog
conversion inevitably involved switches and resistors of
different values, usually arranged in decades. The applica­tion was often the calibrated balancing of a bridge or
reading, via null detection, some unknown voltage. The
most accurate resistor-based DAC of this type is Lord
Kelvin’s Kelvin-Varley divider (Figure, large box). Based
on switched resistor ratios, it can achieve ratio accuracies
of 0.1ppm (23+ bits) and is still widely employed in
standards laboratories.1 High speed digital-to-analog con­version resorts to electronically switching the resistor
network. Early electronic DACs were built at the board level
using discrete precision resistors and germanium transis­tors (Figure, center foreground, is a 12-bit DAC from a

Minuteman missile D-17B inertial navigation system, circa

1962). The first electronically switched DACs available as

standard product were probably those produced by
Pastoriza Electronics in the mid 1960s. Other manufactur­ers followed and discrete- and monolithically-based modu­lar DACs (Figure, right and left) became popular by the
1970s. The units were often potted (Figure, left) for
ruggedness, performance or to (hopefully) preserve pro­prietary knowledge. Hybrid technology produced smaller
package size (Figure, left foreground). The development of
Si-Chrome resistors permitted precision monolithic DACs
such as the LTC1595 (Figure, immediate foreground). In
keeping with all things monolithic, the cost-performance
trade off of modern high resolution IC DACs is a bargain.
Think of it! A 16-bit DAC in an 8-pin IC package. What Lord
Kelvin would have given for a credit card and LTC’s phone
number.

Note 1: See Appendix C, “Verifying Data Converter Linearity to 1ppm,”
for details on Kelvin-Varley Dividers.

Figure A1. Historically Significant Digital-to-Analog Converters Include: Weight Set (Center Left), 23+ Bit Kelvin-Varley Divider
(Large Box), Hybrid, Board and Modular Types, and the LTC1595 IC (Foreground). Where Will It All End?

AN86-6

AN86 FA01.tif

APPENDIX B

THE LTC2400—A MONOLITHIC 24-BIT
ANALOG-TO-DIGITAL CONVERTER

Application Note 86

The LTC2400 is a micropower 24-bit A-to-D converter
with an integrated oscillator, 4ppm nonlinearity and 0.3ppm
RMS noise. It uses delta-sigma technology to provide
extremely high stability. The device can be configured for
better than 110dB rejection at 50Hz or 60Hz ±2%, or it can
be driven by an external oscillator for a user defined
rejection frequency in the range 1Hz to 120Hz.

PARAMETER CONDITIONS

Resolution (No Missing Codes) 0.1V ≤ V
Integral Nonlinearity V

Offset Error 2.5V ≤ V
Offset Error Drift 2.5V ≤ V
Full-Scale Error 2.5V ≤ V
Full-Scale Error Drift 2.5V ≤ V
Total Unadjusted Error V

Output Noise 1.5µV
Normal Mode Rejection 110dB (Min)

60Hz ±2%
Normal Mode Rejection 110dB (Min)

50Hz ±2
Input Voltage Range 0.125V • V
Reference Voltage Range 0.1V ≤ V
Supply Voltage 2.7V ≤ VCC ≤ 5.5V
Supply Current

Conversion Mode CS = 0V 200µA
Sleep Mode CS = V

Figure B1. Key Specifications for LTC2400 A-to-D Converter.
High Linearity and Extreme Stability Allow Realization of 1ppm DAC

REF

V

REF

REF

V

REF

This ultraprecision A-to-D converter in an SO-8 pin pack­age forms the heart of the 20-bit DAC described in the text.
It is significant that the device is used here as a circuit

component

rather than in the traditional standalone role
accorded precision A-to-D converters. This freedom, in
keeping with the IC’s economy and ease of use, is a
noteworthy opportunity. Alert designers will recognize
this development and capitalize on it. Key specifications
for the A-to-D are given in Figure B1.

≤ V

REF

CC

= 2.5V 2ppm of V
= 5V 4ppm of V

≤ V

REF

CC

≤ V

REF

≤ V

REF

≤ V

REF

= 2.5V 5ppm of V
= 5V 1ppm of V

CC

CC

CC

CC

0.01ppm of V

0.02ppm of V

to 1.125V • V

REF

24 Bits

0.5ppm of V

REF

4ppm of V

REF

≤ V

REF

20µA

REF
REF

REF

/°C

REF

/°C

REF
REF

RMS

REF

CC

AN86-7

Application Note 86

APPENDIX C

VERIFYING DATA CONVERTER LINEARITY TO 1PPM

Help from the Nineteenth Century

INTRODUCTION

Verifying 1ppm linearity of the DAC and the analog-to­digital converter used to construct it requires special
considerations. Testing necessitates some form of volt­age source that produces equal amplitude output steps for
incremental digital inputs. Additionally, for measurement
confidence, it is desirable that the source be substantially
more linear than the 1ppm requirement. This is, of course,
a stringent demand and painfully close to the state of the
art.

The most linear “D to A” converter is also one of the oldest.
Lord Kelvin’s Kelvin-Varley divider (KVD), in its most
developed form, is linear to 0.1ppm. This manually switched
device features ten million individual dial settings ar­ranged in seven decades. It may be thought of as a
3-terminal potentiometer with fixed “end-to-end” resis­tance and a 7-decade switched wiper position (Figure C1).

SEVEN-DECADE SWITCHED

R = 100k

WIPER POSITION PERMITS
SETTING TO 0.1ppm LINEARITY

AN86 FC01

10k 2k 400Ω 80Ω

INPUT

80Ω

OUT

80Ω

COMMON

Figure C2. A 4-Decade Kelvin-Varley Divider. Additional
Decades Are Implemented By Opening Last Switch, Deleting
Two Associated 80Ω Values and Continuing ÷ 5 Resistor Chains

AN86 FC02

Figure C1. Conceptual Kelvin-Varley Divider

The actual construction of a 0.1ppm KVD is more artistry
and witchcraft than science. The market is relatively small,
the number of vendors few and resultant price high. If
$13,000 for a bunch of switches and resistors seems
offensive, try building and certifying your own KVD. Figure
C2 shows a detailed schematic.

The KVD shown has a 100kΩ input impedance. A conse­quence of this is that wiper output resistance is high and
varies with setting. As such, a very low bias current
follower is required to unload the KVD without introducing
significant error. Now, our KVD looks like Figure␣ C3. The
LT1010 output buffer allows driving cables and loads and,
more subtly, maintains the amplifier’s high open-loop
gain.

AN86-8

10k

0.1µF

E

INPUT

KVD

Figure C3. KVD with Buffer Gives Output Drive Capability

–

LT1010LTC1152

+

KVD = ELECTRO SCIENTIFIC INDUSTRIES RV-722,
FLUKE 720A OR JULIE RESEARCH LABS VDR-307

OUTPUT

AN86 FC03

Application Note 86

Approach and Error Considerations

This schematic is deceptively simple. In practice, con­struction details are crucial. Parasitic thermocouples
(Seebeck effect), layout, grounding, shielding, guarding,
cable choice and other issues affect achievable perfor­mance.1 In fact, as good as the chopper-stabilized LTC1152
is with respect to drift, offset, bias current and CMRR,
selection is required if we seek sub-ppm nonlinearity
performance. Figure C4, an error budget analysis, details
some of the selection criteria.

10k

0.1µF

–

LTC1152

+

WORST-CASE

SPEC

5µV

0.05µV/°C

50pA
110dB
140dB

–

LTC1152

+

0.1µF

LT1010

REALISTIC SELECTION

TARGET

0.5µV

0.05µV/°C

10pA
140dB
140dB

10k

LT1010

FLOATING, BATTERY-POWERED
µV NULL DETECTOR
HP-419A

OUTPUT

ERROR IN

PPM

0.1

0.01/°C

0.1

0.1

0.1

AN86 FC04

OUTPUT

AN86 FC05

≈ 30k

OUTPUT

ERROR

SOURCE

E

OS

E

OS∆T

I

B

CMRR

5V

KVD RIN = 100k

WORST-CASE

RESISTANCE

FINITE GAIN

Figure C4. Error Budget Analysis for the KVD Buffer.
Selection Permits ≈0.4ppm Predicted Linearity Error

5V

KVD

The buffer is tested with Figure C5’s circuit. As the KVD is
run through its entire range, the floating null detector must
remain well within 1ppm (5µV), preferably below 0.5ppm.
This test ensures that all error sources, particularly IB and
CMRR, whose effects vary with operating point, are ac­counted for. Measured performance indicates the sum of
all errors called out in Figure C4 is well within desired
limits.

In Figure C6, we add offset trim, a stable voltage source
and a second KVD to drive the main KVD. Additionally, an
ensemble of three HP3458A voltmeters monitor the out­put.

The offset trim bleeds a small current into the main KVD
ground return, producing a few microvolts of offset-trim
range. This functionally trims out all sources of zero error
(amplifier offsets, parasitic thermocouple mismatches
and the like), permitting a true zero volt output when the
main KVD is set to all zeros.

The voltmeters, specified for < 0.1ppm nonlinearity on the
10V range, “vote” on the source’s output.

Circuitry Details

Figure C7 is a more detailed schematic. It is similar to
Figure C6 but highlights issues and concerns. The ground­ing scheme is single point, preventing mixing of return
currents and the attendant errors. The shielded cables
used for interconnections between the KVDs and voltme­ters should be specified for low thermal activity. Keithley
type SC-93 and Guildline #SCW are suitable. Crush type
copper lugs (as opposed to soldered types) provide lower
parasitic thermocouple activity at KVD and DVM connec­tion points. However, they must be kept clean to prevent
oxidation, thus avoiding excessive thermal voltages.2 A
copper deoxidant (Caig Labs “Deoxit” D100L) is quite
effective for maintaining such cleanliness. Low thermal
lugs and jacks, preterminated to cables, are also available
(Hewlett-Packard 11053, 11174A) and convenient.

Figure C5. Determining Buffer Error By Measuring Input-Output
Deviation with Floating Microvolt Null Detector. Technique
Permits Evaluation of Fixed and Operating Point Induced Errors

Thermal baffles enclosing KVD and DVM connections tend

Note 1: See Appendix J, “Cables, Connections, Solder, Layout,
Component Choice, Terror and Arcana,” for relevant tutorial.

Note 2: See above Footnote.

AN86-9

Application Note 86

to thermally equilibrate their associated banana jack ter­minals, minimizing residual parasitic thermocouple activ­ity. Additionally, restrict the number of connections in the
signal path. Necessary connections should be matched in
number and material so that differential cancellation oc­curs. Complying with this guideline may necessitate delib­erate introduction of solder-copper junctions (marked “X”
on Figure␣ C7) to obtain optimum differential cancellation.

3

This is normally facilitated by simply breaking the appro­priate wire or PC trace and soldering it. Ensure that the
introduced thermocouples temperature track the junc­tions they are supposed to cancel. This is usually accom­plished by locating all junctions within close physical
proximity.

The noise filtering capacitor at the main KVD is a low
leakage type, with its metal case driven by the output
buffer to guard out surface leakage.

When studying the approach used, it is essential to differ­entiate between linearity and absolute accuracy. This
eliminates concerns with absolute standards, permitting
certain freedoms in the measurement scheme. In particu­lar, although single-point grounding was used, remote
sensing was not. This is a deliberate choice, made to
minimize the number of potential error-causing parasitic
thermocouples in the signal path. Similarly, a ratiometric
reference connection between the KVD LTZ1000A voltage
source and the voltmeters was not utilized for the same
reason. In theory, a ratiometric connection affords lower
drift. In practice, the resultant introduced parasitic ther­mocouples obviate the desired advantage. Additionally,
the aggregate stability of the LTZ1000A reference and the
voltmeter references (also, incidentally, LTZ1000A based)
is comfortably inside 0.1ppm for periods of 10 minutes.

4

This is more than enough time for a 10-point linearity
measurement.

STABLE

VOLTAGE

SOURCE

(LTZ1000A

BASED)

KVD

ADJUST FOR

5.000000V AT A

–

LTC1150

+

Figure C6. Simplified Sub-ppm Linearity Voltage Source

0.1µF

OFFSET

TRIM

+V

–V

10k

LT1010

20k

MAIN

KVD

A

R

WIRE

10k

0.1µF

–

LT1010LTC1152

+

HP3458A

HP3458A

HP3458A

OUTPUT

0.000000V
TO

5.000000V

AN86 FC06

AN86-10

Note 3: See Appendix J, “Cables, Connections, Solder, Layout,
Component Choice, Terror and Arcana,” for further discussion.

Note 4: The LTZ1000A reference is detailed in Appendix I, “ Voltage
References.”

Application Note 86

Construction

Figures C8 and C9 are photographs of the voltage source
and the reference-buffer box internal construction. The
figure captions annotate some significant features.

Results

This KVD-based, high linearity voltage source has been in
use in our lab for nearly two years. During this period, the
total linearity uncertainty defined by the source and its
monitoring voltmeters has been just 0.3ppm (see Figure

SEE APPENDIX F
FOR CIRCUIT DETAILS
OF LTZ1000A

ADJUST FOR

STABLE

VOLTAGE

SOURCE

(LTZ1000A

BASED)

KVD

5.000000V AT A

10k

0.1µF

–

LTC1150

+

OFFSET

TRIM

2k

+V

–V

10k

LT1010

20k

R

MAIN

KVD

WIRE

C10’s measurement regime). This is more than 3 times
better than the desired 1ppm performance, promoting
confidence in our measurements.

5

Acknowledgments

The author is indebted to Lord Kelvin and to Warren Little
of the C. S. Draper Laboratory (née M. I. T. Instrumentation
Laboratory) standards lab. Warren taught me, with great
patience, the wonders of KVDs some thirty years ago and
I am still trading on his efforts.

10k

A

–

10k

+

2µF

CASE

0.1µF

LT1010LTC1152

HP3458A

OUTPUT

0.000000V
TO

5.000000V

= SOLDER-COPPER JUNCTION.

PLACEMENT AND NUMBER AS REQUIRED

2µF = POLYSTYRENE. COMPONENT RSCH. CORP.

USE LOW THERMAL, LOW TRIBOELECTRIC
SHIELDED CABLE FOR KVD AND DVM CONNECTIONS.
SEE TEXT

Figure C7. Complete Sub-ppm Linearity Voltage Source

HP3458A

HP3458A

AN86 FC07

HIGH QUALITY

GROUND

Note 5: The author, wholly unenthralled by web surfing, has spent
many delightful hours “surfing the Kelvin.” This activity consists of
dialing various Kelvin-Varley divider settings and noting monitoring
A-to-D agreement within 1ppm. This is astonishingly nerdy behavior,
but thrills certain types.

AN86-11

Application Note 86

AN86 FC08.tif

Figure C8. The Sub-ppm Linearity Voltage Source. Box Upper Right Is LTZ1000A Based Reference and Buffers. Upper Left Is Offset
Trim. Reference and Main Kelvin-Varley Dividers Are Photo Center—Upper and Center-Middle, Respectively. Three HP3458 DVMs
(Photo Lower) Monitor Output. Computer (Left Foreground) Aids Linearity Calculations

AN86-12

Application Note 86

AN86 FC09.tif

Figure C9. Reference-Buffer Box Construction. LTZ1000A Reference Circuitry Is Photo Lower Left, Buffer Amplifiers Photo Center. Note
Capacitor Case Bootstrap Connection (Photo Center—Right). Single Point Ground Mecca Appears Photo Upper Left. Power Supply
(Photo Top) Mounts Outside Box, Minimizing Magnetic Field Disturbance

1. VERIFY KVD LINEARITY BY INTERCOMPARISON AND INDEPENDENT CAL. LAB.

2. TAKE WORST-CASE VOLTMETER ENSEMBLE DEVIATIONS OVER 0V TO 5V, EVERY 0.5V

3. 100 RUNS (10 PER DAY, ONCE PER HOUR)

4. INDICATED RESULT IS 0.3ppm NONLINEARITY

Figure C10. Testing Regime for the High Linearity Voltage Source

AN86 FC10

AN86-13

Application Note 86

10k

10k

MCLR

2
3
4
5
6
7
8
9

11

1

10

D0
D1
D2
D3
D4
D5
D6
D7
CLK
OE
GND

19
18
17
16
15
14
13
12

20

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

V

CC

0.1µF

U2

74HCT574

2
3
4
5
6
7
8
9

11

1

10

D0
D1
D2
D3
D4
D5
D6
D7
CLK
OE
GND

19
18
17
16
15
14
13
12

20

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

V

CC

0.1µF

0.1µF

5V

4MHz
CRYSTAL

U3 74HCT574

2
3
4
5
6
7
8
9

11

1

10

D0
D1
D2
D3
D4
D5
D6
D7
CLK
OE
GND

19
18
17
16
15
14
13
12

20

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

V

CC

0.1µF

AN86 FD01

U4 74HCT574

1
2
3
4
5
6
7
8

9
10
11
12
13
14

USER INPUT
V

DD

NC
V

SS

NC
ADC SCK
ADC SDO
NC
NC
LSB OE
MID OE
MSB OE
LSB WR
MSB WR

28
27
26
25
24
23
22
21
20
19
18
17
16
15

10k
10k
10k
10k
10k
10k
10k
10k

MCLR
CLKIN

CLKIN2

MSB D7

D6
D5
D4
D3
D2
D1

LSB D0

DAC RDY

DAC LD

MLBYTE

D7 MSB
D6
D5
D4
D3
D2
D1
D0

5V

DAC
COMMANDS
TO ANALOG
SECTION

TO LTC2400
IN ANALOG
SECTION

U1 PIC16C5X

10k
10k
10k
10k
10k

10k

DAC LD
MLBYTE

MSB WR
LSB WR
ADC SDO
ADC SCK

20pF

20pF

USER

DATA

INPUT

MSB

DAC RDY

DAC WR

LSB

1ppm

5V

2ppm

5V

4ppm

5V

FILTER

5V

APPENDIX D

A PROCESSOR-BASED CODE COMPARATOR

The code comparator enforces the loop by setting the
slave DAC inputs to the code that equalizes the user input
and the LTC2400 A-to-D output. This action is more fully
described on page one of the text.

Figure D1 is the code comparator’s digital hardware. It is
composed of three input data latches and a PIC-16C5X
processor. Inputs include user data (e.g., DAC inputs),
linearity curvature correction (via DIP switches), convert
command (“DA WR”) and a selectable filter time constant.
An output (“DAC RDY”) indicates when the DAC output is
settled to the user input value. Additional outputs and an

AN86-14

Figure D1. Code Comparator Hardware. User Control Lines Are at Left, Analog Section Connections Appear at Right Side

input control and monitor the analog section (text Fig­ure␣ 2) to effect loop closure. Note that although a total of
32 bits are presented to the two 16-bit slave DACs, there
are 8 bits of overlap, allowing a total dynamic range of 24
bits. This provides 4 bits of indexing range below the 20th
bit, ensuring a stable LSB of 1ppm of scale. The 8-bit
overlap assures the loop will always be able to capture the
correct output value.

The processor is driven by software code, authored by
Florin Oprescu, which is described below.

Application Note 86

;20bit DAC code comparator
;
;***************************************************
; *
; Filename: dac20.asm *
; Date 12/4/2000 *
; File Version: 1.1 *
; *
; Author: Florin Oprescu *
; Company: Linear Technology Corp. *
; *
; *
;***************************************************
;
; Variables
;============
; uses 17 bytes of RAM as follows:
;
; {UB2, UB1, UB0} user input word buffer
;———————————————————————————————————————
; 24 bits unsigned integer (3 bytes):
;
; The information is transferred from the external input register
; into {UB2, UB1, UB0} whenever a “user input update” event
; is detected by testing the timer0 content. Following the data
; transfer, the UIU (“user input update”) flag is set and the DAC
; ready flags RDY and RDY2 are cleared. UB0 uses the same physical
; location as U0. The user input double buffering is necessary
; because the loop error corresponding to the current ADC reading
; must be calculated using the previous user input value.
; The old user input value can be replaced by the new user input
; value only after the loop error calculation.
; The worst case minimum response time to an UIU event must be
; calculated. The user shall not update the external input register
; at intervals shorter than this response time. For the moment the
; program can not block the user access to the external input
; register during a read operation. In such a situation the result
; of the read operation can be very wrong.
;
; UB0 - least significant byte. Same physical location as U0
;
; UB1 - second byte.
;
; UB2 - most significant byte.
;
;
; {U2, U1, U0} user input word
;——————————————————————————————
; 24 bits unsigned integer (3 bytes):
;
; The information is transferred from {UB2, UB1, UB0[7:4], [0000]}
; into {U2, U1, U0} whenever the UIU flag is found set within the
; CComp (“code comparator”) procedure. The UIU flag is reset
; following the data transfer.

AN86-15

Application Note 86

;
; U0 - least significant byte of current DAC input
; The 4 least significant bits U0[3:0] are set
; to zero.
;
; U1 - second byte of current DAC input
;
; U2 - most significant byte of current DAC input
;
;
; {CON} control byte
;————————————————————
; (1 byte):
;
; The 3 least significant bits CON[2:0] represent the ADC linearity
; correction factor transferred from UB[2:0] when the UIU flag
; is found set within the CComp procedure - at the same time as the
; {U2, U1, U0} variable is updated.
;
; The effect of CON[2:0] is additive and its weight is as follows:
;
; CON[0] = 1 linearity correction effect is about 1ppm
; CON[1] = 1 linearity correction effect is about 2ppm
; CON[2] = 1 linearity correction effect is about 4ppm
;
; The LTC2400 has a typical 4ppm INL error therefore the default
; curvature correction value can be set at CON[2:0] = 100
;
; CON[3] is the control loop integration factor transferred from
; UB[3] when the UIU flag is found set within the CComp procedure.
; If CON[3]=0, after the control loop error becomes less than 4ppm
; the error correction gain is reduced from 1 to 1/4
; If CON[3]=1, after the control loop error becomes less than 4ppm
; the error correction gain is reduced from 1 to 1/16
;
; CON[7] is used as the UIU (“user input update”) flag. It is set
; when {UB2, UB1, UB0} is updated and it is reset when {U2, U1, U0}
; and CON[3:0] are updated.
;
; CON[6] is used as the RDY (“DAC ready”) flag. It is set when
; the DAC loop error becomes less than 4ppm and it is reset when
; the UIU flag is set.
;
; CON[5] is used as the RDY2 (“DAC ready twice”) flag. It is set
; whenever the DAC loop error becomes less than 4ppm and the RDY
; flag has been previously set. It is reset when the UIU flag is set.
;
;
; The bit CON[4] is not used and is always set to 0.
;
;

AN86-16