Noty an76 Linear Technology

Application Note 76

May 1999

OPTI-LOOP Architecture Reduces Output Capacitance and
Improves Transient Response

John Seago

INTRODUCTION

Removing output capacitors saves money and board
space. Linear Technology’s OPTI-LOOPTM architecture
allows you to use the output capacitors of your choice and
compensate the control loop for optimum transient
response and loop stability. Figure 1 shows the dramatic
improvement possible with the OPTI-LOOP architecture.
With the improvement shown in Figure 1, less capacitance
is required or less expensive capacitors can be used. Load
dynamics and supply tolerances will predict the minimum
output capacitance required. The quality of loop compen­sation determines how close you can get to this minimum
capacitance requirement in a real world system.

One of the least understood areas of power supply design
is control loop compensation. Because of this, some
manufacturers provide loop compensation inside the regu­lator IC. Internal compensation works best with one set of
operating conditions and is sensitive to output capacitor
characteristics. Consequently, more expensive output
capacitors may be required to stabilize the loop because of
the sensitivities of the internal IC compensation. The
OPTI-LOOP architecture is intended to allow circuit
designers to squeeze the most performance out of the
output capacitors of their choice.

OPTI -LOOP
COMPENSATION

C

OUT

= 1500µF

WHAT IS LOOP COMPENSATION?

Loop compensation is the adjustment of the control loop
frequency response to assure loop stability and optimize
the transient response of the power supply. The frequency
response is determined by the gain and phase of the loop’s
reaction to load current changes at all frequencies. A Bode
plot is used to show the gain and phase of the frequency
response.

LOOP COMPENSATION BASICS

This application note contains a brief refresher course in
control loop basics. Frequency response is characterized
by the effects of poles and zeros. Each pole has a corner
frequency, caused by a resistance and capacitance, that
determines the beginning of a 20dB/decade drop in volt­age gain. The pole also causes the phase to decrease by
90°, starting roughly one decade before the corner fre­quency and ending about one decade after the corner
frequency. A zero has the opposite effect of a pole. It
causes the gain to increase by 20dB/decade starting at its
“RC” corner frequency and it adds 90° of phase shift,
starting one decade before the corner frequency and
ending one
decade after the corner frequency. The effects of poles and
zeros are additive, so that two poles at the same frequency
cause a 40dB/decade roll-off in gain and a 180° phase shift
over two decades. If a pole and zero occur at the same
frequency, their effects cancel.

COMPETITION

OUTPUT VOLTAGE (50mV/DIV)

TIME (10µs/DIV)

Figure 1. Improved Transient Response with
OPTI-LOOP Architecture

VIN = 15V

= 1.6V

V

O

I

= 30mA to 7A

O

= 1500µF

C

OUT

DSOL8 F01

The crossover frequency of the loop determines the band­width and transient response of the power supply. The
crossover frequency is the frequency at which the loop
gain is one (0dB). The higher the crossover frequency, the
faster the power supply can respond to changes in load
current.

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a trademark of Linear Technology Corporation.

AN76-1

Application Note 76

In a voltage mode DC/DC switching regulator system, the
buck inductor and output capacitor form a double pole at
their resonant frequency, causing a 40dB/decade gain
roll-off and 180° phase shift. Since the inductor’s effect on
a current mode control loop is largely cancelled by the
current loop, it is generally easier to compensate a current
mode regulator than a voltage mode regulator.

The first requirement of loop compensation is stability. If
the error amplifier’s feedback becomes positive when the
loop gain equals one, the regulator will oscillate. A loop
oscillation appears as a sine wave riding on the DC output
voltage at the unity-gain frequency of the control loop.
This oscillation will generally occur in the frequency range
of 1kHz to 20kHz. Don’t confuse switching frequency
ripple or higher frequency ringing with a loop instability.

If a network analyzer is available, stability margins can be
determined by measuring the gain and phase of the loop
and observing the resulting Bode plot. The phase margin
is the difference between the signal phase and –360°
when the voltage gain is one (0dB). A 60° phase margin is
preferred, but 45° is usually acceptable. The gain margin
is the amount of negative gain present when the signal
phase is zero (– 360°). A gain margin of – 10dB is normally
considered acceptable. Generous gain and phase margins
are very important because actual component values vary

over temperature and component values differ from unit to
unit in production, causing the loop’s voltage gain and
phase to vary accordingly. If the component values cause
the phase to go to zero when the voltage gain is one, the
regulator will oscillate. The goal is to provide the best gain
and phase margins with the highest crossover frequency
possible. A high crossover frequency results in a quick
response to load current changes whereas high gain at low
frequencies results in fast settling of the output voltage.
Nonideal components and amplifier gain limitations gen­erally force a trade-off between high crossover frequency
and large stability margins.

THE CONTROL LOOP

Figure 2 shows the simplified control loop for the LTC®1628
and LTC1735/LTC1736 current mode, synchronous buck
regulators. The control loop has both DC gain and AC
frequency response characteristics. The DC loop consists
of the feedback resistors, the error amplifier, the DC
resistance of the ITH pin components, the current com­parator, the sense resistor and the load resistor. The AC
loop consists of the DC loop plus the output capacitor,
capacitors C1 and C2 and the AC impedance of the ITH pin
components.

INPUT

C

IN

AN76-2

TOP

MOSFET

BOTTOM

MOSFET

SWITCH

NODE

(LTC1735/LTC1736)

INDUCTOR

TG

BG

LTC1628

MOSFET

CONTROL

LOGIC

+

CURRENT

COMP

–

MODULATOR ERROR AMPLIFIER

30k

30k

R

SENSE

SENSE

(10mV TO 65mV)

0V TO 75mV

(0.3V TO 2.2V)

0.3V TO 2.4V

I

TH

C4

R3

C3

+

ERROR

AMP

gm = 1.4mS

SENSE

+

–

–

V

OSENSE

0.8V

Figure 2. Basic Control Loop of Current Mode, Switching Regulator

OUTPUT

R1

C1

C

R

OUT

LOAD

C2

R2

AN76 F02

Application Note 76

DC GAIN

DC gain is the small-signal loop gain under static test
conditions. Load regulation is determined by DC gain, so
the higher the gain, the lower the change in output voltage
for a given DC load current variation. The DC gain is the
product of the feedback resistor attenuation, the error
amplifier voltage gain and modulator gain. The modulator
consists of the current comparator, the MOSFETs and
their drivers, the inductor, sense resistor, output capacitor
and load resistance: basically the power path.

The feedback divider attenuation is:

A

= V

V(FB)

where: V
V

is the output voltage of the power supply.

OUT

REF/VOUT

is 0.8V for products in the LTC1735 family and

REF

The error amplifier voltage gain is:

A

= g

V(EA)

where: g

m(EA)ZITH

is the transconductance of the error ampli-

m(EA)

fier, 1.4mS for products in the the LTC1735 family and
Z

is the output impedance of the error amplifier in

ITH

parallel with any impedance connected to the ITH pin.

g

m(MOD)

= (V

RSENSE(MAX)/RSENSE

)/∆V

ITH(MAX)

= (0. 075V/0.015Ω)/2.1V = 2.38S
A

V(MOD)

= g

m(MOD)RLOAD

= (2.38S)(3.3V/3A)
= 2.62 = 8.4dB
DC Gain = (A

V(FB)

)( A

V(EA)

)(A

V(MOD)

)

= (0.242)(4592)(2.62) = 2911 = 69.3dB

FREQUENCY RESPONSE

Frequency response is the loop’s reaction to perturbations
at all frequencies and is shown as gain and phase mea­surements on a Bode plot. The output capacitor and load
resistance largely determine where the error amplifier
poles and zeros need to be placed for optimum transient
response and loop stability.

Output Capacitor Pole and Zero

The gain at very low frequencies is equal to the DC gain.
Normally the first departure from that gain is the pole
created by the load resistance and the output capacitance.
The corner frequency of this pole is:

The transconductance of the modulator must be deter­mined before calculating the modulator gain. The modu­lator transconductance is:

g

m(MOD)

where: V
R

SENSE

∆V

ITH(MAX)

= (V

RSENSE(MAX)/RSENSE

RSENSE(MAX)

is listed in the data sheet as 75mV,

)/∆V

ITH(MAX)

is the value of the current sense resistor and

is 2.1V for the no-load to full-load output

voltage swing of the error amplifier.
The DC voltage gain of the modulator is:

A

where: g
and R

V(MOD)

m(MOD)

LOAD

= g

m(MOD)RLOAD

is the transconductance of the modulator

= V

OUT/IOUT

.

As an example, the DC gain for the LTC1735/LTC1736 or
the LTC1628 providing 3A at 3.3V is:

A

V(FB)

A

V(EA)

= V
= g

/V

REF

OUT

m(EA)ZITH

= 0.8V/3.3V = 0.242 = –12.3 dB

= (1.4mS)(3.28M) = 4592 = 73.2 dB

where: 3.28M is the typical output impedance of the error
amplifier without any external DC loading on the ITH pin.

fP = 1/(2πRLC

where: RL is the load resistance and C

OUT

)

is the output

OUT

capacitance.
Notice that as the output current goes down, the equiva-

lent load resistance goes up, causing the pole frequency to
decrease. The same is true when the output capacitance
increases, that is, the pole frequency moves lower.

The amount of phase margin is largely determined by the
zero formed by the output capacitance and capacitor ESR.
The corner frequency of this zero is:

fZ = 1/(2πESR • C

OUT

)

It is interesting to note that doubling the number of like
output capacitors will lower the pole frequency by half but
will not change the zero frequency of the output capacitor.
This is true because, as the capacitance doubles, the ESR
is halved, yet the load resistance remains the same.
Consequently, the product of RL and C
product of ESR and C

remains the same. It is desirable

OUT

goes up, but the

OUT

that the crossover frequency be higher than the ESR zero

AN76-3

Application Note 76

frequency because the phase shift of the ESR zero is very
helpful in achieving adequate phase margin.

Different types of capacitors have different amounts of
ESR per µF of capacitance. The ESR of the output capacitor
determines the output ripple voltage under static load
conditions and greatly affects the output response to
transient loads. For a 3A output, the inductor ripple current
should be about 1A
ESR should be about 0.05Ω for a 50mV

. Therefore, the output capacitor

P-P

output voltage

P-P

ripple. The difference in frequency response between
Panasonic’s Specialty Polymer output capacitors and alu­minum electrolytic output capacitors, with 0.05Ω of ESR,
is shown in Figures 3 and 4.

40

47µF

6.3V

30

0.05Ω

20

= 1.1Ω

R

L

10

0

GAIN (dB)

–10

–20

–30

–40

GAIN
PHASE

110

Figure 3. Frequency Response of Specialty Polymer
Capacitor Used in 3.3V, 3A Power Supply Output

40

1200µF

6.3V

30

0.048Ω

20

RL = 1.1Ω

10

GAIN (dB)

–10

–20

–30

–40

12Hz

0

GAIN
PHASE

110

1

fZ =

2πESR(C

308Hz

100 10k1k

FREQUENCY (Hz)

1

fZ =

2πESR(C

fP =

120Hz

276Hz

100 10k1k

FREQUENCY (Hz)

fP =

)

OUT

fP =

3.08kHz

6.77kHz

fP =

)

OUT

27.6kHz

1.2kHz

fZ = 2.76kHz

1

2πR

LCOUT

677.6kHz

30.8kHz

fZ = 67.76kHz

100k

1

2πR

LCOUT

100k

1M

AN76 F03

1M

AN76 F04

PHASE (DEG)

45

0

–45

–90

–135

PHASE (DEG)

45

0

–45

–90

–135

Aluminum electrolytic capacitors are often selected for
both the input and output of very low cost power supplies.
Figure 3 shows a 3kHz pole for a 47µF, 6.3V, 0.05Ω
Specialty Polymer capacitor. Figure 4 shows a 120Hz pole
for a 1200µF, 6.3V, 0.05Ω aluminum electrolytic capaci-
tor. In order to maintain the 0.05Ω ESR required to meet
the output ripple requirement, the aluminum electrolytic
capacitor requires 25 times the capacitance of the Spe­cialty Polymer capacitor, causing the aluminum electro­lytic capacitor to have a pole frequency at 4% of the
specialty polymer capacitor.

The loop compensation must be quite different when
aluminum electrolytic capacitors are used. It is unlikely
that fixed internal compensation will work well with both
types of capacitors. Although bandwidth will suffer when
aluminum electrolytic capacitors are used, using an OPTI­LOOP architecture, the loop can be optimized for their use
and stable operation achieved. The high ESR zero fre­quency of the Specialty Polymer capacitors makes the
loop more difficult to compensate, but the bandwidth will
be significantly higher as a result of the extra effort.

The Modulator

The modulator controls the inductor current as a function
of the amplified error signal from the error amplifier. The
transconductance of the modulator, calculated earlier, is
determined by the maximum current allowed through the
sense resistor divided by the maximum voltage swing of
the error amplifier output at the ITH pin. The product of the
modulator transconductance and the load resistance is
the modulator gain for DC. The frequency response of the
modulator is determined by multiplying the modulator
gain at DC times the frequency response of the output
capacitor and the load resistance. This is the same as
changing the 0dB gain reference on Figures 3 and 4 to the
modulator gain level. Consequently, the frequency
response of the modulator is primarily determined by the
output capacitor and the load resistance.

Figure 4. Frequency Response of Aluminum Electrolytic
Capacitor Used in 3.3V, 3A Power Supply Output

AN76-4

Application Note 76

The Error Amplifier

The error amplifier provides most of the loop gain. After
selecting the output capacitor, the control loop is compen­sated by tailoring the frequency response of the error
amplifier. It has a transconductance of 1.4mS and an
output resistance of 3MΩ, so it provides a low frequency
gain of 4600 or 73dB. The loop gain is the product of the
error amplifier gain and the modulator gain, so the fre­quency response of the error amplifier, the output capaci­tor and load resistor determine the frequency
response of the loop.

The AC behavior of the error amplifier is determined by C1,
C2, C3, C4, R1, R2 and R3 as shown in Figure 2. The
following relationships are given as a first approximation,
since there is some interaction between the parts. As an
example, the low frequency pole of the error amplifier is
the dominant pole and is determined primarily by C3 and
the output resistance of the error amplifier as shown by:

fP = 1/(2πR

However, R3 and C4 have a small effect on the actual
corner frequency, since the series combination of C3 and
R3 are in parallel with C4, which is in parallel with R
Although all three impedances interact, the resistance of
R3 is small compared to the impedance of C3 at the pole
frequency, so its effect is small. The same is true of C4.
Since the value of C4 is normally small compared to C3,
the primary effect is determined by C3.

Resistor R3 adds a zero to the frequency response to
control gain in the midfrequency range. This zero fre­quency is:

fZ = 1/(2πR3C3)

Capacitor C4 adds a pole to reduce very high frequency
gain. Although frequently unnecessary for loop stability,
C4 helps to filter the effects of PCB noise and output ripple
voltage from the loop. It is desirable to have the error
amplifier gain be less than zero dB at the switching
frequency. The high frequency pole created by C4 is:

fP = 1/(2πR3C4)

The high frequency zero created by C1 and R1 can be very
important for transient load applications. Capacitor C1
provides phase lead and acts like a speed-up capacitor to
output voltage changes, so it tends to “short-out” R1 and

O(EA)

C3)

O(EA)

.

improve the high frequency response. This zero tends to
produce a positive-going bump in the phase plot. Ideally,
the peak of this bump is centered over the loop’s crossover
frequency. The R1, C1 zero is located at:

fZ = 1/(2πR1C1)

The pole created by R2 and C2 is generally not critical for
loop stability. It is frequently set at one half to one third of
the switching frequency and is primarily used for noise
filtering rather than loop compensation. The effect of C2 is
normally countered by the value of R3. The R2, C2 pole
frequency can be calculated by:

fP = 1/(2πR2C2)

ITH PIN COMPONENT VALUES

Selecting the best values for the loop compensation com­ponents is not as simple as selecting pole and zero
frequencies for the ideal crossover frequency. Several
other factors should be taken into account. The slew rate
and amplitude of the load transient largely determine the
ESR requirement of the output capacitor. The amount of
capacitance used at the output is primarily determined by
the type of capacitor used and partially determined by the
load transient characteristics.

PCB-generated noise can have a considerable effect on the
operation of a power supply. Problems caused by PCB
noise should be corrected by layout improvements but
this is not always possible. Proper decoupling and loop
bandwidth limiting can significantly reduce the effects of
PCB noise on regulator operation. However, reducing loop
bandwidth will also reduce dynamic performance.

Good transient response and PCB noise reduction are
opposing requirements when determining the values of
the ITH pin components. The final loop compensation
must have good stability margins. There are no equations
that will yield component values to optimize the loop
transient response, give good PCB noise reduction and
provide the required stability margins. The equations
given for pole and zero frequencies are handy references
for predicting the effect a part change will have on the
frequency response. Although gain can be calculated
reasonably accurately, phase calculations tend to have
large errors because of the many parasitics in the power
path.

AN76-5