Noty an29f Linear Technology

Some Thoughts on DC/DC Converters

Jim Williams and Brian Huffman

INTRODUCTION

Application Note 29

October 1988

Many systems require that the primary source of DC power be converted to other voltages. Battery driven circuitry is an obvious candidate. The 6V or 12V cell in a laptop computer must be converted to different potentials needed for memory, disc drives, display and operating logic. In theory, AC line powered systems should not need DC/DC converters because the implied power transformer can be equipped with multiple secondaries. In practice, economics, noise requirements, supply bus distribution problems and other constraints often make DC/DC conversion preferable. A common example is logic dominated, 5V powered systems utilizing ±15V driven analog components.

The range of applications for DC/DC converters is large, with many variations. Interest in converters is commensurately quite high. Increased use of single supply powered systems, stiffening performance requirements and battery operation have increased converter usage.

Historically, efﬁ ciency and size have received heavy emphasis. In fact, these parameters can be signiﬁ cant, but often are of secondary importance. A possible reason behind the continued and overwhelming attention to size and efﬁ ciency in converters proves surprising. Simply put, these parameters are (within limits) relatively easy to achieve! Size and efﬁ ciency advantages have their place, but other system-oriented problems also need treatment. Low quiescent current, wide ranges of allowable inputs, substantial reductions in wideband output noise and cost effectiveness are important issues. One very important converter class, the 5V to ±15V type, stresses size and efﬁ ciency with little emphasis towards parameters such as output noise. This is particularly signiﬁ cant because wideband output noise is a frequently encountered problem with this type of converter. In the best case, the output noise mandates careful board layout and grounding schemes.

In the worst case, the noise precludes analog circuitry from achieving desired performance levels (for further discussion see Appendix A, “The 5V to ±15V Converter — A Special Case”). The 5V to ±15V DC/DC conversion requirement is ubiquitous, and presents a good starting point for a study of DC/DC converters.

5V TO ±15V CONVERTER CIRCUITS

Low Noise 5V to ±15V Converter

Figure 1’s design supplies a ±15V output from a 5V input. Wideband output noise measures 200 microvolts peakto-peak, a 100× reduction over typical designs. Efﬁ ciency at 250mA output is 60%, about 5% to 10% lower than conventional types. The circuit achieves its low noise performance by minimizing high speed harmonic content in the power switching stage. This forces the efﬁ ciency trade-off noted, but the penalty is small compared to the beneﬁ t.

The 74C14 based 30kHz oscillator is divided into a 15kHz 2-phase clock by the 74C74 ﬂ ip-ﬂ op. The 74C02 gates and 10k-0.001μF delays condition this 2-phase clock into nonoverlapping, 2-phase drive at the emitters of Q1 and Q2 (Figure 2, Traces A and B, respectively). These transistors provide level shifting to drive emitter followers Q3-Q4. The Q3-Q4 emitters see 100Ω-0.003μF ﬁ lters, slowing drive to output MOSFETs Q5-Q6. The ﬁ lter’s effects appear at the gates of Q5 and Q6 (Traces C and D, respectively). Q5 and Q6 are source followers, instead of the conventional common source connection. This limits transformer rise time to the gate terminals ﬁ ltered slew rate, resulting in

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

an32f

AN29-1

Application Note 29

0.001

CLK-NON OVERLAP

GENERATOR

22k

74C14

74C02

74C14

74C02

15kHz, 5μs

NON-OVERLAP

74C74

10k

74C14

LEVEL SHIFTS

0.001

100Ω

150k 1k

10k

100Ω

10k

POINT “A” (SEE TEXT) BOOST OUTPUT ≈17V

DIRVERS-

EDGE

SHAPING

100

1k150k

1N5817

–4V

D1 1N5817

22μF

1N5817

S 1

3 9

OUTPUT

= ±15 COMMON

= +5 GROUND

* = 1% FILM RESISTOR FET = MTP3055E-MOTOROLA PNP = 2N3906 NPN = 2N3904 L1 = PULSE ENGINEERING, INC. #PE-61592 = FERRITE BEAD, FERRONICS #21-110J

1N5817

D2 1N5817

TURBO BURST

470

0.001

100μF

(4.5V TO 5.5V)

MUR 120

(ALL)

10μF

1μF

+15 OUT

OUT COMMON

–15 OUT

LT1086

100μF

10μF

LT337A

10μF

124*

1.37k*

249*

2.74k*

AN29 F01

100

LT1054

BOOST

100

0.003

Figure 1. Low Noise 5V to ±15V Converter

A = 20V/DIV

B = 20V/DIV

C = 20V/DIV

D = 20V/DIV

E = 10V/DIV

F = 10V/DIV

HORIZ = 20μs/DIV

AN29 F02

Figure 2. 5V to ±15V Low Noise Converter Waveforms

well controlled waveforms at the sources of Q5 and Q6 (Traces E and F, respectively). L1 sees complimentary, slew limited drive, eliminating the high speed harmonics normally associated with this type converter. L1’s output is rectiﬁ ed, ﬁ ltered and regulated to obtain the ﬁ nal out-

put. The 470Ω-0.001μF damper in L1’s output maintains loading during switching, aiding low noise performance. The ferrite beads in the gate leads eliminate parasitic RF oscillations associated with follower conﬁ gurations.

The source follower conﬁ guration eases controlling L1’s edge rise times, but complicates gate biasing. Special provisions are required to get the MOSFETs fully turned on and off. Source follower connected Q5 and Q6 require voltage overdrive at the gates to saturate. The 5V primary supply cannot provide the speciﬁ ed 10V gate — channel bias required for saturation. Similarly, the gates must be pulled well below ground to turn the MOSFETs off. This is so because L1’s behavior pulls the sources negative when the devices turn off. Turn-off bias is bootstrapped from the negative side of Q6’s source waveform. D1 and the 22μF capacitor produce a –4V potential for Q3 and Q4 to pull down to. Turn-on bias is generated by a 2-stage

an32f

AN29-2

Application Note 29

boost loop. The 5V supply is fed via D3 to the LT®1054 switched capacitor voltage converter (switched capacitor voltage converters are discussed in Appendix B, “Switched Capacitor Voltage Converters — How They Work”). The LT1054 conﬁ guration, set up as a voltage doubler, initially provides about 9V boost to point “A” at turn-on. When the converter starts running L1 produces output (“Turbo Boost” on schematic) at windings 4-6 which is rectiﬁ ed by D2, raising the LT1054’s input voltage. This further raises point “A” to the 17V potential noted on the schematic.

These internally generated voltages allow Q5 and Q6 to receive proper drive, minimizing losses despite their source follower connection. Figure 3, an AC-coupled trace of the 15V converter output, shows 200μV

noise at full power

P-P

(250mA output). The –15V output shows nearly identical characteristics. Switching artifacts are comparable in amplitude to the linear regulators noise. Further reduction in switching based noise is possible by slowing Q5 and Q6 rise times. This, however, necessitates reducing clock rate and increasing non-overlap time to maintain available output power and efﬁ ciency. The arrangement shown represents a favorable compromise between output noise, available output power, and efﬁ ciency.

A = 100μV/DIV

(AC-COUPLED)

less than 30μV of output noise. This is almost 7× lower than the previous circuit and approaches a 1000× improvement over conventional designs. The trade off is efﬁ ciency and complexity.

A1 is set up as a 16kHz Wein bridge oscillator. The single power supply requires biasing to prevent A1’s output from saturating at the ground rail. This bias is established by returning the undriven end of the Wein network to a DC potential derived from the LT1009 reference. A1’s output is a pure sine wave (Figure 5, Trace A) biased off ground. A1’s gain must be controlled to maintain sine wave output. A2 does this by comparing A1’s rectiﬁ ed and ﬁ ltered positive output peaks with an LT1009 derived DC reference. A2’s output, biasing Q1, servo controls A1’s gain. The

0.22μF capacitor frequency compensates the loop, and the thermally mated diodes minimize errors due to rectiﬁ er temperature drift. These provisions ﬁ x A1’s AC and DC output terms against supply and temperature changes.

A1’s output is AC coupled to A3. The 2k –820Ω divider re-biases the sine wave, centering it inside A3’s input common mode range even with supply shifts. A3 drives a power stage, Q2-Q5. The stages common emitter outputs and biasing permit 1V at V

= 4.5V. At full converter output loading the

SUPPLY

RMS

(3V

) transformer drive, even

P-P

stage delivers 3 ampere peaks but the waveform is clean (Trace B), with low distortion (Trace C). The 330μF coupling capacitor strips DC and L3 sees pure AC. Feedback to A3 is taken at the Q4-Q5 collectors. The 0.1μF unit at this point suppresses local oscillations. L3’s secondary RC network adds additional high frequency damping.

HORIZ = 5μs/DIV

Figure 3. Output Noise of the Low Noise 5V to ±15V Converter. Appendix H Shows a Modern IC Low Noise Regulator

AN29 F03

Ultralow Noise 5V to ±15V Converter

Residual switching components and regulator noise set Figure 1’s performance limits. Analog circuitry operating at the very highest levels of resolution and sensitivity may require the lowest possible converter noise. Figure 4’s converter uses sine wave transformer drive to reduce harmonics to negligible levels. The sine wave transformer drive combines with special output regulators to produce

Without control of quiescent current the power stage will encounter thermal runaway and destroy itself. A4 measures DC output current across Q5’s emitter resistor and servo controls Q6 to ﬁ x quiescent current. A divided portion of the LT1009 reference sets the servo point at A4’s negative input and the 0.33μF feedback capacitor stabilizes the loop.

L3’s rectiﬁ ed and ﬁ ltered outputs are applied to regulators designed for low noise. A5 and A7 amplify the LT1021’s ﬁ ltered 10V output up to 15V. A6 and A8 provide the –15V output. The LT1021 and ampliﬁ ers give better noise performance than three terminal regulators. The Zener-resistor network clips overvoltages due to start-up transients.

an32f

AN29-3

Application Note 29

OUT

15V

25μH

47μF

LT1010

(4.5V TO 5.5V)

4.99k*

–

1/2 LT1013

10k*

22μF

100μH

22μF

1N4001

68Ω

AMP

POWER

430Ω

1μF

MJE2955

50Ω

OUT

†

330μF

0.1

2N2219

0.1

LT1021

OUT

10V

330Ω

534

0.1

50Ω

COMMON

19V

UNREG

0.005

MJE3055

2N2905

220μF

100Ω

330Ω 10k*

1N4001

0.1Ω

220μF

10k

1k750Ω*

10k*

1N5260B

–19V

UNREG

0.22

47μF

OUT

–15V

25μH

LT1010

–

1/2 LT1013

620Ω

LOOP

CONTROL

10k

–

1/2 LT1013

0.33

AN29 F04

0.1

20k

0.01

LT1006

270Ω

–

1k*

(SELECTED

VALUE—

SEE TEXT)

430Ω

LT1009

2.5

MATED

THERMALLY

200k

–

0.22

1/2 LT1013

OSCILLATOR

10k

STAB. LOOP

3.1k

= 1N4148

= 1N4934

L1, L2 = PULSE ENGINEERING, INC. #PE-92100

L3 = PULSE ENGINEERING, INC. #PE-65064

L4 = PULSE ENGINEERING, INC. #PE-92108

= THF337K006P1G

UNMARKED NPN = 2N3904

* = 1% METAL FILM RESISTOR

†

= +5 GROUND

= ±15 COMMON

Figure 4. Ultralow Noise Sine Wave Drive 5V to ±15V Converter

an32f

220Ω

820Ω

1μF

10k

LT1006

47μF

0.22

680Ω

–

220Ω

0.01

16kHz

OSCILLATOR

AN29-4

A = 2V/DIV

B = 2V/DIV

C = 1% DISTORTION

D = 20μV/DIV

HORIZ = 50μs/DIV

Figure 5. Waveforms for the Sine Wave Driven Converter. Note that Output Noise (Trace D) is Only 30μV

AN29 F05

P-P

L1 and L2 combine with their respective output capacitors to aid low noise characteristics. These inductors are outside the feedback loop, but their low copper resistance does not signiﬁ cantly degrade regulation. Trace D, the 15V output at full load, shows less than 30μV (2ppm) of noise. The most signiﬁ cant trade-off in this design is efﬁ ciency. The sine wave transformer drive forces substantial power loss. At full output (75mA), efﬁ ciency is only 30%.

Before use, the circuit should be trimmed for lowest distortion (typically 1%) in the sine wave delivered to L3. This trim is made by selecting the indicated value at A1’s negative input. The 270Ω value shown is nominal, with a typical variance of ±25%. The sine wave’s 16kHz frequency is a compromise between the op amps available gain bandwidth, magnetics size, audible noise, and minimization of wideband harmonics.

Single Inductor 5V to ±15V Converter

Simplicity and economy are another dimension in 5V to ±15V conversion. The transformer in these converters is usually the most expensive component. Figure 6’s unusual drive scheme allows a single, 2-terminal inductor to replace the usual transformer at signiﬁ cant cost savings. Tradeoffs include loss of galvanic isolation between input and output and lower power output. Additionally, the regulation technique employed causes about 50mV of clock related output ripple.

The circuit functions by periodically and alternately allowing each end of the inductor to ﬂ yback. The resultant positive and negative peaks are rectiﬁ ed and ﬁ ltered. Regulation is obtained by controlling the number of ﬂ yback events during the respective output’s ﬂ yback interval.

Application Note 29

The leftmost logic inverter produces a 20kHz clock (Trace A, Figure 7) which feeds a logic network composed of additional inverters, diodes and the 74C90 decade counter. The counter output (Trace B) combines with the logic network to present alternately phased clock bursts (Traces C andD) to the base resistors of Q1 and Q2. When φ1 (Trace B) is unclocked it resides in its high state, biasing Q2 and Q4 on. Q4’s collector effectively grounds the “bottom” of L1 (TraceH). During this interval φ2 (Trace A) puts clock bursts into Q1’s base resistor. If the –15V output is too low servo comparator C1A’s output (Trace E) is high, and Q1’s base can receive pulsed bias. If the converse is true the comparator will be low, and the bias gated away via Q1’s base diode. When Q1 is able to bias, Q3 switches, resulting in negative going ﬂ yback events at the “top” of L1 (Trace G). These events are rectiﬁ ed and ﬁ ltered to produce the –15V output. C1A regulates by controlling the number of clock pulses that switch the Q1-Q3 pair. The LT1004 serves as a reference. Trace J, the AC-coupled –15V output, shows the effect of C1A’s regulating action. The output stays within a small error window set by C1A’s switched control loop. As input voltage and loading conditions change C1A adjusts the number of clock pulses allowed to bias Q1-Q3, maintaining loop control.

When the φ1 and φ2 signals reverse state the operating sequence reverses. Q3’s collector (Trace G) is pulled high with Q2-Q4 switching controlled by C1B’s servo action. Operating waveforms are similar to the previous case. Trace F is C1B’s output, Trace H is Q4’s collector (L1’s “bottom”) and Trace I is the AC-coupled 15V output. Although the two regulating loops share the same inductor they operate independently, and asymmetrical output loading is not deleterious. The inductor sees irregularly spaced shots of current (Trace K), but is unaffected by its multiplexed operation. Clamp diodes prevent reverse biasing of Q3 and Q4 during transient conditions. The circuit provides ±25mA of regulated power at 60% efﬁ ciency.

Low Quiescent Current 5V to ±15V Converter

A ﬁ nal area in 5V to ±15V converter design is reduction of quiescent current. Typical units pull 100mA to 150mA of quiescent current, unacceptable in many low power systems.

an32f

AN29-5

Application Note 29

150k*

12.4k*

HP5082-2810

32k

1000pF

74C90

÷10

= 1N4148

* = 1% METAL FILM RESISTOR

= 74C14

1/2 LT1018

–

10k

C1A

10k

300Ω

10k

100Ω

4.7k

300Ω

C1B

1/2 LT1018

Q1 2N3906

Q2 2N3904

100Ω

–

LT1004

1.2V

Q3 2N5023

–15V

15V

137k*

12.4k*

AN29 F06

OUT

100

L1 145μH

Q4 2N3507

100

L1 = PULSE ENGINEERING, INC. # PE-92105

Figure 6. Single Inductor 5V to ±15V Regulated Converter

A = 5V/DIV

B = 5V/DIV

C = 10V/DIV

D = 10V/DIV

E = 10V/DIV

F = 10V/DIV

G = 20V/DIV

H = 20V/DIV

I = 0.05V/DIV (AC-COUPLED)

J = 0.05V/DIV (AC-COUPLED)

K = 1A/DIV

HORIZ = 100μs/DIV

Figure 7. Waveforms for the Single Inductor, Dual-Output, Regulated Converter

AN29 F07

Figure 8’s design supplies ±15V outputs at 100mA while consuming only 10mA quiescent current. The LT1070 switching regulator (for a complete description of this device, see Appendix C, “Physiology of the LT1070”) drives L1 in ﬂ yback mode. A damper network clamps excessive ﬂ yback voltages. Flyback events at L1’s secondary are half-wave rectiﬁ ed and ﬁ ltered, producing positive and negative outputs across the 47μF capacitors. The positive 16V output is regulated by a simple loop. Comparator C1A balances a sample of the positive output with a 2.5V reference obtained from the LT1020. When the 16V output (Trace A, Figure 9) is too low, C1A switches (TraceB) high, turning off the 4N46 opto-isolator. Q1 goes off, and the LT1070’s control pin (V causes full duty cycle 40kHz switching at the V

) pulls high (Trace C). This

(Trace D). The resultant energy into L1 forces the 16V output to ramp quickly positive, turning off C1A’s output.

an32f

AN29-6

(4.5V TO 5.5V)

Application Note 29

16V PRE-REG

0.47

GND

10k

1 9

3 7

1.2k 2W

MUR120

2N3906

LT1070FB

L1 = PULSE ENGINEERING, INC. # PE-61592 * = 1% FILM RESISTOR

= +5 GROUND

= ±15 COMMON

1N4148

4N46

390k

47μF

1.2M*

82k

216k*

–

C1A

1/2 LT1017

20M

10k

–16V UNREG

10k

0.002

UPDATE

Burst Mode regulators can achieve lower I

Figure 8. Low I

, Isolated 5V to ±15V Converter

GND

–1N

COMP PNP

0.001μF 3M* 500k* 100k

470k

LT1070

2.5V

+IN

REF OUT

74 6

Q2 VN2222

OPTIONAL

(SEE TEXT)

OUT

COMP

NPN

–16V UNREG

–15V

15V

OUT

2.5M*

0.001μF

100mA

500k*

10μF

–15V

OUT

100mA

REF OUT

470k

3.2M

1.5M

–

1/2 LT1017

47k

C1B

TO 16V

PRE-REG

1.5k

5.6M

AN29 F08

A = 100mV/DIV

(AC-COUPLED ON

LEVEL)

16V

B = 20V/DIV

C = 2V/DIV

D = 20V/DIV

HORIZ = 5ms/DIV

AN29 F09

Figure 9. Waveforms for the Low IQ 5V to ±15V Converter

The 20M value combined with the 4N46’s slow response (note the delay between C1A going high and the V

rise) gives about 40mV of hysteresis. The LT1070’s onoff duty cycle is load dependent, saving signiﬁ cant power when the converter is lightly loaded. This characteristic is largely responsible for the 10mA quiescent current. The opto-isolator preserves the converters input-output isolation. The LT1020, a low quiescent current regulator with low dropout, further regulates the 16V line, giving the 15V output. The linear regulation eliminates the 40mV ripple and improves transient response. The –16V output

tends to follow the regulated –16V line, but regulation is poor. The LT1020’s auxiliary onboard comparator is compensated to function as an op amp by the RC damper at Pin 5. This ampliﬁ er linearly regulates the –16V line. MOSFET Q2 provides low dropout current boost, sourcing the –15V output. The –15V output is stabilized with the op amp by comparing it with the 2.5V reference via the 500k-3M current summing resistors. 1000pF capacitors frequency compensate each regulating loop. This converter functions well, providing ±15V outputs at 100mA with only 10mA quiescent current. Figure 10 plots efﬁ ciency versus a conventional design over a range of loads. For high loads results are comparable, but the low quiescent circuit is superior at lower current.

A possible problem with this circuit is related to the poor regulation of the –16V line. If the positive output is lightly loaded L1’s magnetic ﬂ ux is low. Heavy negative output loading under this condition results in the –16V line falling below its output regulators dropout value. Speciﬁ cally, with no load on the 15V output only 20mA is available from the –15V output. The full 100mA is only available from

an32f

AN29-7

Application Note 29

100

EFFICIENCY (%)

LOW QUIESCENT

CURRENT DESIGN

CONVENTIONAL

DESIGN

2010

4030

OUTPUT CURRENT (mA)

60 70 90

100

AN29 F10

Figure 10. Efﬁ ciency vs Load for the Low IQ Converter

the –15V output when the 15V output is supplying more than 8mA. This restriction is often acceptable, but some situations may not tolerate it. The optional connection in Figure 8 (shown in dashed lines) corrects the difﬁ culty. C1B detects the onset of –16V line decay. When this occurs its output pulls low, loading the 16V line to correct the problem. The biasing values given permit correction before the negative linear regulator drops out.

MICROPOWER QUIESCENT CURRENT CONVERTERS

Many battery-powered applications require very wide ranges of power supply output current. Normal conditions require currents in the ampere range, while standby or “sleep” modes draw only microamperes. A typical laptop computer may draw 1 to 2 amperes running while needing only a few hundred microamps for memory when turned off. In theory, any DC/DC converter designed for loop stability under no-load conditions will work. In practice, a converter’s relatively large quiescent current may cause unacceptable battery drain during low output current intervals.

Figure 11 shows a typical ﬂ yback based converter. In this case the 6V battery is converted to a 12V output by the inductive ﬂ yback voltage produced each time the LT1070’s

pin is internally switched to ground (for commentary

on inductor selection in ﬂ yback converters see Appendix D, “Inductor Selection for Flyback Converters”). An internal 40kHz clock produces a ﬂ yback event every 25μs. The energy in this event is controlled by the IC’s internal error ampliﬁ er, which acts to force the feedback (FB) pin to a 1.23V reference. The error ampliﬁ ers high impedance

output (the VC pin) uses an RC damper for stable loop compensation.

This circuit works well but pulls 9mA of quiescent current. If battery capacity is limited by size or weight this may be too high. How can this ﬁ gure be reduced while retaining high current performance?

L1*

50μH

LT1070

GND V

MUR8100

1μF

470μF

*PULSE ENGINEERING, INC #PE-51515

10.7k

1.24k

AN29 F11

V 12V

OUT

Figure 11. 6V to 12V, 2 Amp Converter with 9mA Quiescent Current

A solution is suggested by considering an auxiliary V function. If the V

pin is pulled within 150mV of ground the

IC shuts down, pulling only 50 microamperes. Figure 12’s special loop exploits this feature, reducing quiescent current to only 150 microamperes. The technique shown is particularly signiﬁ cant, with broad implication in battery powered systems. It is easily applied to a wide variety of DC/DC converters, meeting an acknowledged need across a wide spectrum of applications.

Figure 12’s signal ﬂ ow is similar to Figure 11, but additional circuitry appears between the feedback divider and the V

pin. The LT1070’s internal feedback ampliﬁ er and reference are not used. Figure 13 shows operating waveforms under no-load conditions. The 12V output (Trace A) ramps down over a period of seconds. During this time comparator A1’s output (Trace B) is low, as are the 74C04 paralleled inverters. This pulls the V IC in its 50μA shutdown mode. The V

pin (Trace C) low, putting the

pin (Trace D) is

high, and no inductor current ﬂ ows. When the 12V output drops about 20mV, A1 triggers and the inverters go high, pulling the V

pin pulses the inductor at the 40kHz clock rate, caus-

pin up and turning on the regulator. The

ing the output to abruptly rise. This action trips A1 low, forcing the V

pin back into shutdown. This “bang-bang”

control loop keeps the 12V output within the 20mV ramp

an32f

AN29-8

(4.5V TO 8V)

47μF

L1 50μH

LT1070

GND

200Ω

C2 47μF

MUR405

FB NC

3.6M*

Application Note 29

–

1/2 LT1017

1.2M*

C1 2700μF

1/2 LT1017

–

“LOW BATT”

12V

R1 1M*R7100k

R2 120k*

OUT

C3 1500pF

UPDATE

Micropower regulators using Burst Mode operation are available

10pF**

** = OPTIONAL. SEE TEXT

= 1N4148

* = 1% METAL FILM RESISTOR

= 74C04

L1 = PULSE ENGINEERING, INC. # PE-51515

Figure 12. 6V to 12V, 2 Amp Converter with 150μA Quiescent Current

hysteresis window set by R3-R4. Diode clamps prevent

pin overdrive. Note that the loop oscillation period of

4 to 5 seconds means the R6-C2 time constant at V

is not a signiﬁ cant term. Because the LT1070 spends almost all of the time in shutdown, very little quiescent current (150μA) is drawn.

Figure 14 shows the same waveforms with the load increased to 3mA. Loop oscillation frequency increases to keep up with the loads sink current demand. Now, the V

pin waveform (Trace C) begins to take on a ﬁ ltered appearance. This is due to R6-C2’s 10ms time constant. If

R4 10k

AN29 F12

A = 0.02V/DIV

(AC-COUPLED)

B = 5V/DIV

C = 2V/DIV

D = 10V/DIV

180k

LT1004

1.2V

Figure 13. Low I

HORIZ = 1s/DIV

Converter Waveforms with No Load

(Traces B and D Retouched for Clarity)

AN29 F13

an32f

AN29-9

Application Note 29

the load continues to increase, loop oscillation frequency will also increase. The R6-C2 time constant, however, is ﬁ xed. Beyond some frequency, R6-C2 must average loop oscillations to DC. Figure 15 shows the same circuit points at 1 ampere loading. Note that the VC pin is at DC, and repetition rate has increased to the LT1070’s 40kHz clock frequency. Figure 16 plots what is occurring, with a pleasant surprise. As output current rises, loop oscillation frequency also rises until about 500Hz. At this point the R6-C2 time constant ﬁ lters the V LT1070 transitions into “normal” operation. With the V

pin to DC and the

pin at DC it is convenient to think of A1 and the inverters as a linear error ampliﬁ er with a closed-loop gain set by the R1-R2 feedback divider. In fact, A1 is still duty cycle modulating, but at a rate far above R6-C2’s break frequency. The phase error contributed by C1 (which was selected for low loop frequency at low output currents) is dominated by the R6-C2 roll off and the R7-C3 lead into A1. The loop is stable and responds linearly for all loads beyond 80mA. In this high current region the LT1070 is desirably “fooled” into behaving like Figure 11’s circuit.

A formal stability analysis for this circuit is quite complex, but some simpliﬁ cations lend insight into loop operation. At 100μA loading (120kΩ) C1 and the load form a decay time constant exceeding 300 seconds. This is orders of magnitude larger than R7-C3, R6-C2, or the LT1070’s 40kHz commutation rate. As a result, C1 dominates the loop. Wideband A1 sees phase shifted feedback, and very

low frequency oscillations similar to Figure 13’s occur

. Although C1’s decay time constant is long, its charge time constant is short because the circuit has low sourcing impedance. This accounts for the ramp nature of the oscillations.

Increased loading reduces the C1 load decay time constant. Figure 16’s plot reﬂ ects this. As loading increases, the loop oscillates at a higher frequency due to C1’s decreased decay time. When the load impedance becomes low enough C1’s decay time constant ceases to dominate the loop. This point is almost entirely determined by R6 and C2. Once R6 and C2 “take over” as the dominant time constant the loop begins to behave like a linear system. In this region (e.g. above about 75mA, per Figure 16) the LT1070 runs continuously at its 40kHz rate. Now, the R7C3 time constant becomes signiﬁ cant, performing as a

simple feedback lead

to smooth output response. There is

A = 0.02V/DIV

(AC-COUPLED)

B = 5V/DIV

C = 2V/DIV

D = 10V/DIV

HORIZ = 20ms/DIV

AN29 F14

Figure 14. Low IQ Converter Waveforms at Light Loading

A = 0.02V/DIV

B = 5V/DIV

C = 2V/DIV

D = 10V/DIV

AN29 F15

2.5A

100

AN29 F16

Figure 15. Low I

550

500

450

400

350

300

250

IQ = 150μA

200

150

LOOP FREQUENCY (Hz)

100

HORIZ = 20μs/DIV

Converter Waveforms at 1 Amp Loading

LINEAR REGION

EXTENDS TO

0.2Hz

OUTPUT (mA)

Figure 16. Figure 12’s Loop Frequency vs Output Current. Note Linear Loop Operation Above 80mA

Some layouts may require substantial trace area to A1’s inputs. In such cases the optional 10pF capacitor shown ensures clean transitions at A1’s output.

“Zero Compensation” for all you technosnobs out there.

AN29-10

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A = 10V/DIV

B = 0.1V/DIV

(AC-COUPLED)

HORIZ = 5ms/DIV

Figure 17. Load Transient Response for Figure 12’s Low IQ Regulator

AN29 F17

Application Note 29

constant decay is visible as Trace B approaches steady state between the 4th and 5th vertical divisions.

A2 functions as a simple low-battery detector, pulling low when V

drops below 4.8V.

Figure 18 plots efﬁ ciency versus output current. High power efﬁ ciency is similar to standard converters. Low power efﬁ ciency is somewhat better, although poor in the lowest ranges. This is not particularly bothersome, as power loss is very small.

(“rattling” is perhaps more appropriate)

100

EFFICIENCY (%)

Figure 18. Efﬁ ciency vs Output Current for Figure 12. Standby Efﬁ ciency is Poor, But Power Loss Approaches Battery Self Discharge

TYPICAL OPERATING

15mA

3mA

650μA

IQ = 150μA

0.5

OUTPUT CURRENT (A)

REGION

TYPICAL STANDBY REGION

1.5

2.5

AN29 F18

a fundamental trade-off in the selection of the R7-C3 lead network values. When the converter is running in its linear region they must dominate the DC hysteresis deliberately generated by R3-R4. As such, they have been chosen for the best compromise between output ripple at high load and loop transient response.

This loop provides a controlled, conditional instability instead of the more usually desirable (and often elusive) unconditional stability. This deliberately introduced characteristic lowers converter quiescent current by a factor of 60 without sacriﬁ cing high power performance. Although demonstrated in a boost converter, it is readily exportable to other conﬁ gurations. Figure 19a’s step-down (buck mode) conﬁ guration uses the same basic loop with almost no component changes. P-channel MOSFET Q1 is driven from the LT1072 (a low power version of the LT1070) to convert 12V to a 5V output. Q2 and Q3 provide current limiting, while Q4 supplies turn off drive to Q1. the lower output voltage mandates slightly different hysteresis biasing than Figure 12, accounting for the 1MΩ value at the comparators positive input. In other respects the loop and its performance are identical. Figure 19b uses the loop in a transformer based multi-output converter. Note that the ﬂ oating secondaries allow a –12V output to be obtained with a positive voltage regulator.

Low Quiescent Current Micropower 1.5V to 5V Converter

Despite the complex dynamics transient response is quite good. Figure 17 shows performance for a step from no load to 1 ampere. When Trace A goes high a 1 ampere load appears across the output (Trace B). Initially, the output sags almost 150mV due to slow loop response time (the R6-C2 pair delay V

pin response). When the LT1070 comes

on (signaled by the 40kHz “fuzz” at the bottom extreme of Trace B) response is reasonably quick and surprisingly well behaved considering circuit dynamics. The multi-time

Figure 20 extends our study of low quiescent current converters into the low voltage, micropower domain. In some circumstances, due to space or reliability considerations, it is preferable to operate circuitry from a single 1.5V cell. This eliminates almost all ICs as design candidates. Although it is possible to design circuitry which runs directly from

a single cell (see LTC

Application Note 15, “Circuitry For Single Cell Operation”) a DC/DC converter permits using higher voltage ICs. Figure 20’s design converts a single

Once again, “multi-pole settling” for those who adore jargon.

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AN29-11

Application Note 29

12V

(8V TO 16V)

0.4Ω

1k100Ω

2N3906

IRF-9531

Q4 2N3904

100μH

MUR405

2700μF

1M*

OUT

1500pF

100k

10μF

1N4148

L1 = PULSE ENGINEERING, INC. # PE-92108 ** = OPTIONAL. SEE TEXT * = 1% FILM RESISTOR

Q3 2N3904

= 74C04

LT1072

200Ω

47μF

GND

FB NC

10k

12V

–

1/2 LT1017

10pF**

UPDATE

Burst Mode regulators can achieve lower I

340k*

10k 470k

LT1004

1.2V

AN29 F19a

12V

Figure 19a. The Low Quiescent Current Loop Applied to a Buck Converter

1.5V cell to a 5V output with only 125μA quiescent current. Oscillator C1A’s output is a 2kHz square wave (Trace D, Figure 21). The conﬁ guration is conventional, except that the biasing accommodates the narrow common mode range dictated by the 1.5V supply. To maintain low power, C1A’s integrating capacitor is small, with only 50mV of swing. The parallel connected sides of C2 drive L1. When the 5V output (Trace A) coasts down far enough C1B goes low (Trace B), pulling both C2 positive inputs close to ground. C1A’s clock now appears at the paralleled C2

outputs (Trace C), forcing energy into L1. The paralleled outputs minimize saturation losses. L1’s ﬂ yback pulses, rectiﬁ ed and stored in the 47μF capacitor, form the circuits DC output. C1B on-off modulates C2 at whatever duty cycle is required to maintain the circuits 5V output. The LT1004 is the reference, with the resistor divider at C1B’s positive input setting the output voltage. Schottky clamping of C2’s outputs prevents negative going overdrives due to parasitic L1 behavior.

AN29-12

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Application Note 29

12V

MUR120

22μF

2k 2W

0.2μF

MUR120

MBR360

MUR120

GND

LT1071

FB NC

200Ω

C2 47μF

74C04 (5)

470μF

C1 2700μF

LT1086

1.2k

11k

12V

1/2 LT1017

11k

–

10μF

12V

10μF

–12V V

OUT

5V 1A

1M*R710k

0.005

R2 453k*

1N4148

L1 = PULSE ENGINEERING, INC. # PE-65108 * = 1% FILM RESISTOR ** = OPTIONAL. SEE TEXT

Figure 19b. Multi-Output, Transformer Coupled Low Quiescent Current Converter

The 1.2V LT1004 reference biasing is bootstrapped to the 5V output, permitting circuit operation down to 1.1V. A 10M bleed to supply ensures start-up. The 1M resistors divide down the 1.2V reference, keeping C1B inside common mode limits. C1B’s positive feedback RC pair sets about 100mV hysteresis and the 22pF unit suppresses high frequency oscillation.

The micropower comparators and very low duty cycles at light load minimize quiescent current. The 125μA ﬁ gure noted is quite close to the LT1017’s steady-state currents. As load increases the duty cycle rises to meet the demand,

10pF**

1N4148

10k

LT1004

1.2

AN29 F19b

180k

12V

requiring more battery power. Decrease in battery voltage produces similar behavior. Figure 22 plots available output current versus battery voltage. Predictably, the highest power is available with a fresh cell (e.g., 1.5V to 1.6V), although regulation is maintained down to 1.15V for 250μA loading. The plot shows that the test circuit continued to regulate below this point, but this cannot be relied on in practice (LT1017 V

= 1.15V). The low supply voltage

MIN

makes saturation and other losses in this circuit difﬁ cult to control. As such, efﬁ ciency is about 50%.

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AN29-13

Application Note 29

3.9M

–

1.5M

150pF

3.9M

1.5V

470k

* = 1% METAL FILM RESISTOR PNP = 2N3906 NPN = 2N3904 L1 = TRIAD # SP-29

C1A

1/2 LT1017

240k

1.5V

150k

10M

–

C2B

1/2 LT1017

–

C2A

1/2 LT1017

(1.1V TO 2V)

1N4148

HP5082-2810

HP-5082-2810

2.2μF

OUT

22pF

1M*

0.001

C1B

1/2 LT1017

–

1M*

10M

360k

10M

LT1004

1.2V

4.3M*

47μF

619k*

390k

0.001

OPTIONAL FOR

NEGATIVE

OUTPUT

(SEE TEXT)

1.5V

C2B

C2A

Figure 20. 800μA Output 1.5V to 5V Converter

A = 100mV/DIV

(AC-COUPLED ON

LEVEL)

B = 2V/DIV

C = 2V/DIV

D = 2V/DIV

HORIZ = 5ms/DIV

AN29 F21

Figure 21. Waveforms for Low Power 1.5V to 5V Converter

TO 390kΩ

OF C2B

47μF

620k

850 800 750

= 5V

700 650

OUT

600 550 500 450 400 350 300 250 200 150 100

OUTPUT (μA) AVAILABLE AT V

22pF

1.2M* 10k5.1M

–

IQ = 125μA

1.05 1.15

C1B

OUT

EFFICIENCY ≈ 50%

GUARANTEED MINIMUM

OPERATING VOLTAGE

1.25

INPUT VOLTAGE (V)

10M 47k

= 5V

LT1017

1.35

LT1004

1.2V

1.45

1.55

AN29 F22

Figure 22. Output Current Capability vs Input Voltage for Figure 20

AN29 F20

AN29-14

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+ 32 hidden pages

Noty an29f Linear Technology

Specifications and Main Features

Frequently Asked Questions

User Manual