Noty an17f Linear Technology
Application Note 17
December 1985
Considerations for Successive Approximation
A→D Converters
Jim Williams
The most popular A→D method employed today is the
successive approximation register (SAR) converter (see
Box, “The Successive Approximation Technique”). Numerous monolithic, hybrid and modular devices embodying
the successive approximation technique are available, and
monolithic devices are slowly gaining in performance.
Nevertheless, hybrid and modular SAR types feature
the best performance. In particular, at the 12-bit level,
the fastest monolithic devices currently available require
about 10µs to convert. Modular and hybrid units achieve
LT1021
7V
R3
6.98k
0.001µF
6012 12-BIT
D/A CONVERTER
AM2504
SAR REGISTER
SE
START
15V
16151420
17
1
D
CC
S
CP
CLOCK f = 1.4MHz
15V
PARALLEL
OUTPUTS
R1
1k
FULL-SCALE
TRIM
R2*
6.49k
13
12 11 10 9 876 5 432
4 5 6 7 8 9 161718192021
24
5V
12
conversion speeds below 2µs, although they are quite
expensive. Because of these factors, it is often desirable to
build, rather than buy, a high speed 12-bit SAR converter.
Even in cases where high speed is not required, lower cost
may still mandate building the circuit instead of using a
monolithic device.
Figure 1 shows a simple 12-bit, 12µs SAR converter. Understanding this circuit’s performance limitations is useful
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–15V
19
DAC I
18
PARALLEL
OUTPUTS
SERIAL OUTPUT
*R2 AND R4 SHOULD TC TRACK
INPUT
0V TO 10V
R4*
2.49k
R6
820
7475
LATCH
I
2
+
LT1011A
3
–
5V
R5
1k
7
AN17 F01
Figure 1. Basic 12-Bit, 12μs Successive Approximation A→D Converter
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Application Note 17
in designing faster converters. Figure 2 shows waveforms
of operation. Trace A is the clock, which is applied to the
2504 IC successive approximation register (SAR), while
Trace B is the start pulse. On the rising edge of the start
pulse, the SAR-DAC combination begins to test each
bit, beginning with the MSB. This action is reflected in
conditions at the LT1011’s positive input (Trace C). This
waveform is seen to sequentially converge towards zero
as the SAR, DAC and comparator servo the node. After
the LSB has been converted the “conversion complete”
(CC) line (Trace D) goes high, signaling the end of the
sequence. The 7475 latch prevents the comparator from
responding to input noise or shifts after the conversion is
complete. It is reset at the next “conversion command”.
The major limitations on speed in this circuit are the DAC
and the comparator. Most bipolar DACs require 150ns to
200ns to settle for a worst-case (full-scale) step and the
comparator’s delay time must also be accounted for. The
clamp diodes limit overdrive, aiding comparator response.
Additionally, the 820 resistor to ground shunts the DACs
output capacitance, helping the comparator-DAC node
settle more quickly. The shunt degrades the voltage perLSB available to the comparator, but the LT1011’s high
gain makes up for this.
In general, this is a fairly typical 12-bit SAR converter with
good speed and low cost. To get higher conversion speed
requires more sophisticated circuitry.
Figure 3 shows a circuit, which uses a clock modulation
scheme to decrease conversion time. The A→D is identical
to Figure 1’s circuit, but the clock terminal (CP) is driven
by a 2-speed oscillator. Figure 4 shows operating details.
A convert command pulse (Trace A) initiates the SAR routine. Simultaneously, the 7474 flip-flop’s Q output is set
high (Trace C), biasing Q1. This causes the 47pF capacitor
to be paralleled with the 33pF unit. These capacitors are
part of the timing network of C1, which is configured as
an oscillator. C1’s output pulses (Trace B) drive the SAR’s
clock terminal (CP in the schematic). After the third MSB
has been converted, the flip-flop is reset (Trace C). Q1
goes off and the clock oscillator (Trace B) speeds up. The
increase in clock speed results in less dwell time per bit
at the DAC-comparator junction (Trace D), allowing faster
total conversion time. Trace E, the conversion complete
pulse (CC), drops low 7.5µs after the conversion started.
This clock modulation approach buys significantly improved speed, but does nothing to get around the comparator’s contribution to delay. Minimizing comparator delay
would seem to be as simple as using a faster device. At
the 8-bit or even 10-bit level this usually works, but 12-bit
performance raises problems. Replacing the LT1011, a
150ns device, with a 10ns LT1016 increases speed, but
decreases available gain. The LT1011 has a minimum
gain of 200,000. The LT1016’s high speed sacrifices gain.
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A = 5V/DIV
B = 5V/DIV
C = 200mV/DIV
D = 5V/DIV
HORIZ = 2µs/DIV
Figure 2. 12μs A→D Waveforms
AN17 F02
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Application Note 17
Minimum gain for this device is 1400. For a 10V full-scale
A→D, the LSB size is given by:
4096 steps
10V
= 2.44mV/LSB
PARALLEL
OUTPUTS
15V
5V
R1
1k
FULL-SCALE
TRIM
R2*
6.49k
13
12 11 10 9 876 5 432
4 5 6 7 8 9 161718192021
24
12
LT1021
7V
R3
6.98k
0.001µF
6012 12-BIT
D/A CONVERTER
AM2504
SAR REGISTER
SE
15V
To switch a full TTL output level with one-half LSB overdrive
(1.22mV), the comparator must have a minimum gain of:
5V
= 4,098
DAC I
PARALLEL
OUTPUTS
SERIAL OUTPUT
INPUT
0V TO 10V
R4*
2.49k
R6
820
7475
LATCH
I
2
3
+
C2
LT1011A
–
5V
R5
1k
7
AN17 F03
16151420
CP
1.22mV
17
1
D
CC
S
–15V
19
18
7474
CONVERT
COMMAND
1k
1k
5V
47pF
4.7k
QQ
PRESETCLR
15k
–5V
Q1
2N2369
33pF
+
LT1016
–
1k
C1
NC
6.8k
Figure 3. 7.5μs A→D Using a 2-Speed Clock
A = 5V/DIV
B = 10V/DIV
C = 10V/DIV
D = 200mV/DIV
E = 5V/DIV
HORIZ = 1µs/DIV
AN17 F04
Figure 4. Figure 3’s Waveforms
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AN17-3
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