Noty an16f Linear Technology

Application Note 16

Unique IC Buffer Enhances Op Amp Designs,
Tames Fast Amplifiers

Robert J. Widlar

August 1985

Abstract: A unity gain IC power buffer that uses NPN
output transistors while avoiding the usual problems of
quasi-complementary designs is described. Free of para­sitic oscillations and stable with large capacitive loads, the
buffer has a 20MHz bandwidth, a 100V/μs slew and can
drive ±10V into a 75Ω load. Standby current is 5mA. A
number of applications using the buffer are detailed, and
it is shown that a buffer has many uses beyond driving
a heavy load.

Introduction

An output buffer can do much more than increase the
output swing of an op amp. It can also eliminate ringing
with large capacitive loads. Fast buffers can improve the
performance of high speed followers, integrators and
sample/hold circuits, while at the same time making them
much easier to work with.

Interest in buffers has been low because a reasonably
priced, high performance, general purpose part has not
been available. Ideally, a buffer should be fast, have no
crossover distortion and drive a lot of current with large
output swing. At the same time, the buffer should not eat
much power, drive all capacitive loads without stability
problems and cost about the same as the op amps it is
used with. Naturally, current limiting and thermal overload
protection would be nice.

These goals have been a dream for twenty years; but thanks
to some new IC design techniques, they have finally been
reached. A truly general purpose buffer has been made that
is faster than most op amps but not hard to use in slow
applications. It is manufactured using standard bipolar
processing, and die size is 50 × 82 mils.

The electrical characteristics of the buffer are summarized
in Table 1. Offset voltage and bias current win no medals;
but the buffer will usually be driven from an op amp output
and put within the feedback loop, virtually eliminating these
terms as errors. Loaded voltage gain is mostly determined
by the output resistance. Again, any error is much reduced
with the buffer inside a feedback loop.

Unloaded, the output swings within a volt of the positive
supply and almost to the negative rail. With ±150mA load­ing, this saturation voltage increases by 2.2V. Except for
output voltage swing, performance is little affected for a
total supply voltage between 4V and 40V. This means that
it can be powered by a single 5V logic supply or ±20V op
amp supplies.

Bandwidth and slew rate decrease somewhat with reduced
load resistance. The values given in Table 1 are for a 100Ω
in parallel with 100pF. The speed is quite impressive con­sidering that quiescent current is but 5mA.

Table 1. Typical Performance of the Buffer at 25°C. Supply
Voltage Range is 4V to 40V

PARAMETER VALUE

Output Offset Voltage 70mV
Input Bias Current 75μA
Voltage Gain 0.999
Output Resistance 7Ω
Positive Saturation Voltage 0.9V
Negative Saturation Voltage 0.1V
Output Saturation Resistance 15Ω
Peak Output Current ±300mA
Bandwidth 22MHz
Slew Rate 100V/μs
Supply Current 5mA

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.

an16f

AN16-1

Application Note 16

Design Concept

The functional schematic in Figure 1 describes the basic
elements of the buffer design. The op amp drives the
output sink transistor, Q30, such that the collector cur­rent of the output follower, Q29, never drops below the
quiescent value (determined by I

and the area ratio of

1

Q12 and Q28). As a result, the high frequency response
is essentially that of a simple follower even when Q30 is
supplying the load current. The internal feedback loop is
isolated from the effects of capacitive loading by a small
resistor in the output lead.

The scheme is not perfect in that the rate of rise of sink
current is noticeably less than for source current. This
can be mitigated by connecting a resistor between the

+

bias terminal and V

, raising quiescent current. A feature
of the final design is that the output resistance is largely
independent of the follower current, giving low output
resistance at low quiescent current. The output will swing
to the negative rail, which is particularly useful with single­supply operation.

+

V

Q28Q12

BIAS

+

–

A1

I

C23

Basic Design

Figure 2 shows the essential details of the buffer design
using the concept in Figure 1 (for clarity, parts common
to simplified and developed schematics use the same
number). The op amp uses a common base PNP pair, Q10
and Q11, degenerated with R6 and R7 for an input stage.
The differential output is converted to single-ended by a
current mirror, Q13 and Q14; and this drives the output
sink transistor, Q30, through a follower, Q19.

A clamp, Q15, is included to insure that the output sink
transistor does not turn off completely. Its biasing circuitry
Q6 through Q9, is arranged such that the emitter current
of Q15 is about equal to the base current of Q19 with no
output load.

The control loop is stabilized with a feedforward capacitor,
C1. Above 2MHz, feedback is predominantly through the
capacitor. The break frequency is determined by C1 and R7
plus the emitter resistance of Q11. The loop is made stable
for capacitive and resonant loading by R23, which limits
the phase lag that can be induced at the emitter of Q29.

A resistor, R10, has been added to improve the negative
slew response. With a large negative transient, Q29 will
cut off. When this happens, R10 pulls stored charge from
Q28 and provides enough voltage swing to get Q30 from
its clamp level into conduction.

Q29

I

1

Figure 1. In the Buffer, Main Signal Path Is Through Followers
Q21 and Q29. Op Amp Keeps Q29 Turned on Even When Q30 Is
Supplying Load Current, So Response Is That of Followers

Q21

Q30

R23

AN16 F01

INPUT

OUTPUT

–

V

Start-up biasing is done with a collector FET, Q4. Once in
operation, the collector current of Q6 is added to the drain
current of Q4 to bias Q5. These currents plus the current
through Q9 and Q10 flow through Q12 to set the output
quiescent current (along with R10).

Follower Boost

The boost circuit in Figure 3 reduces the buffer standby
current by at least a factor of three while improving per­formance. It does this by increasing the effective current
gain of Q29 so that the current source current I

, can be

C23

drastically cut. Secondly, it can give under 0.5Ω follower
output resistance at less than 3mA bias, something that
normally takes over 40mA. Hard as it may be to believe,
the boost does not degrade the high frequency response
of the final design.

an16f

AN16-2

Application Note 16

+

R23

7

AN16 F02

V

BIAS

OUTPUT

INPUT

–

V

R10
300

R7

R6

Q5

Q6

Q4

R4
4k

R5
1k

Q10

Q9

100μ

Q8

100μ

1k

100μ

1k

Q11

Q15

Q14Q7 Q13

R20

200

700μ
C1
60

Q19

R14
4k

Q28Q12

Q23

Q29

Q30

Q21

Figure 2. Implementation of the Buffer in Figure 1. Simple Op Amp Uses Common Base PNP Input Transistors (Q10 and Q11).
Control Loop Is Stabilized with Feedforward Capacitor (C1); and Clamp (Q15) Keeps Q30 from Turning Off Entirely

+

V

0.7mA

INPUT

I

C23

Q24

Q21

–

V

R19
200

Q25

R21
3k

Q29

I

Q

OUTPUT

AN16 F03

Figure 3. This Boost Circuit Raises Effective Current Gain and
Transconductance of the Output Transistor, Giving Low Standby
Current Along with Low Output Resistance

If R19 is removed (opened), circuit operation becomes
clearer. Output resistance is determined by Q24, with Q25
and Q29 providing current gain. If the current through R21
is larger than the base current of Q29, output resistance is
proportionately reduced. Without R21, output resistance
depends on Q29 bias, like a simple follower.

The purpose of R19 is to provide a direct AC path at high
frequencies and kill unneeded gain in the boost feedback

loop. If R21 is properly selected, voltage change across R19
with loading is less than 40mV, so a small value causes no
problems (increasing load does cause Q21 bias current to
increase). The quiescent drop across R19 is set by sizing
Q24, Q25 and Q29 geometries.

Charge Storage PNP

At high frequencies, a lateral PNP looks like a low imped­ance between the base and emitter because charge stored
between the emitter and subcollector (the PNP base) has a
capacitive effect. The input PNP, Q21, has been designed to
have more than 30 times the stored charge of a standard
lateral for a given emitter current. This stored charge
couples in the input to slew internal stray capacitances
and drive the output follower while the boost circuitry is
coming into action.

Stored charge can be maximized in a lateral PNP by using
large emitter area and wide base spacing. Dimensions of
several mils are practical; diffusion lengths are in the order
of 6 mils with good processing.

an16f

AN16-3

Application Note 16

A sketch of a charge storage PNP is shown in Figure 4.
With the dimensions shown, current gains of 10 can be
obtained regularly. A sinker base contact is shown here
because a low resistance from the base terminal to the
area under the emitter is important.

The charge stored under the emitter is most effective in
obtaining a fast charge transfer from base to emitter with
minimum change of emitter base voltage. Using the nota­tion in Figure 4, this charge varies as:

W

BAE

S

E

∝ XC–X

()

X

E

E

QE∝

where SE is the emitter periphery. With XC fixed, it can be
shown that Q

is maximized for XE = 0.5XC.

E

P+ COLLECTOR

W

B

2 MILS

X

E

4 MILS

X

C

W

B

2 MILS

As will be seen on the complete schematic, the isolation­base transistor is used as a bias diode for current sources
because of its high V

. One (Q28) is also used in the

BE

collector of the output follower because the behavior at
very high current densities is much better than a standard
transistor.

20

10

N+ EMITTER

)

–3

19

10

18

10

NET CONCENTRATION (cm

17

10

0

4 8 12 16

JUNCTION DEPTH (μm)

Figure 5. Impurity Profile of Isolation-Base Transistor. In
Contrast, Typical Standard NPN Has Peak Base Concentration
of 5 × 1016cm–3 and Base Width of 1μm

P+ ISOLATION

SUBCOLLECTOR

+

N

AN16 F05

+

N

AN16 F04

SINKER

BASE

CONTACT

N

–

BASE

0.4 MILS

+

SUBCOLLECTOR

N

Figure 4. Charge Storage PNP is Lateral Structure with Base and
Emitter Dimensions of Several Mils. As Above, Current Gains of
10 are Practical

Isolation-Base Transistor

Transistors can be made by substituting an isolation dif­fusion for the normal base diffusion. Figure 5 shows the
impurity profile of such a transistor. Base doping under
the emitter is three orders of magnitude higher than stan­dard transistors, and the base extends all the way to the
subcollector. The measured current gains of 0.1 are not
lower than might be expected.

The emitter-base voltage of an isolation-base transistor is
about 120mV greater than a standard IC transistor when
operating at the same emitter current. Production varia­tions in V

are much less than standard NPNs, probably

BE

because net base doping is little affected by anything but
the isolation doping.

Complete Circuit

A complete schematic of the LT1010 buffer is given in
Figure 6. Component identification corresponds to the
simplified schematics. All details discussed thus far have
been integrated into the diagram.

Current limiting for the output follower is provided by
Q22 and Q31, which serve to clamp the voltage into the
follower boost circuitry when the voltage across R22
equals a diode drop.

Negative current limit is less conventional because putting
a sense resistor in the emitter of Q30 will seriously degrade
negative slew under load. Instead, the sense resistor, R17,
is in the collector. When the drop across it turns on Q27,
this transistor supplies current directly to the sink current
control amplifier, limiting sink current.

+

Should the output terminal rise above V

because of some
fault condition, Q27 can saturate, breaking the current limit
loop. Should this happen, Q26 (a lateral collector near Q27
base) takes over to control current by removing sink drive
through Q16. This reserve current limit oscillates, but in
a controlled fashion.

AN16-4

an16f

Application Note 16

Clamp diodes, from the output to each supply, should
be used if the output can be driven beyond the supplies
by a high-current source. Unlike most ICs, the LT1010 is
designed so that ordinary junction diodes are effective
even when the IC is much hotter than the external diodes.

Current limit is backed up by thermal overload protec­tion. The thermal sensor is Q1, with its base biased near
400mV. When Q1 gets hot enough to pull base drive off
Q2 (about 160°C), the collector of Q2 will rise, turning on
Q16 and Q20. These two transistors then shut down the
buffer. Including R2 generates hysteresis to control the
frequency of thermal limit oscillation.

Base drive to Q20 is limited by R15, a pinched base re­sistor. The value of this resistor varies as transistor h

fe

over temperature and in production, controlling the turn
off current near 2mA. An emitter into the isolation wall
capacitor, C2, keeps Q20 from turning on with fast signals
on its collector.

In current limit or thermal limit, excessive input-output
voltage might damage internal circuitry. To avoid this,
back-to-back isolation Zeners, Q32 and Q33, clamp the
input to the output. They are effective as long as the input
current is limited to about 40mA.

Other details include the negative saturation clamp, Q17
and Q18. This clamp allows the output to saturate within
100mV of the negative supply rail without increasing supply
current while recovering cleanly from saturation. The base
of Q17 is connected internally into Q30 to sense voltage
on the internal collector side of the saturation resistance
to insure optimum operation at high currents.

When sinking large currents, the base of Q19 loads the
control amplifier. This unbalances the control loop and
reduces the output follower bias current. To compensate
for this, the base current of Q30 is routed to the bias diode,
Q12, through Q19. A small resistor, R19, aids compensa­tion. This action raises the bias to Q23 and is responsible
for increasing the input PNP bias current with sink current.

R9
15

Q18

R15
24k

R14

4k

R20
200

Q23

Q19

Q20

R19
200

R18

2k

R16
200

R17

C2

100

2

Q21

Q22

Q24

Q26

Q25

R21
3k

Q27

Q31

Q30

R10

Q11

Q14

300

R7
1k

C1
30

Q15

R12

1k

Q17

Q16

R13
4k

Q12

R8

15k

R6

R3
440

Q2

Q1

R2

R1

450

4k

Q5

Q6

Q4

R4
4k

R5

1k

1k

Q10Q9

Q8

Q7

Q13

Q28

Q29

R22
2

AN16 F06

+

V

BIAS

Q32

Q33

–

V

R23

5

OUTPUT

INPUT

Figure 6. Complete Schematic of the LT1010 Buffer. Component Identification Corresponds to Simplified Schematics.
The Isolation-Base Transistors Are Drawn with Heavy Base, as Is the Charge Storage PNP. Follower Drive Boost Has
Been Included Along with Negative Saturation Clamp (Q17 and Q18) and Protection Circuitry

an16f

AN16-5

Application Note 16

Final details of the design are that the collectors of Q10
and Q11 are segmented so that only a fraction of the
emitter current is sent to the current mirror, with the rest
dumped to V-. This allows the transistors to be operated

A AC

D EB

at their f

peak without requiring large C1. Lastly, R8 has

T

been included to shape the temperature characteristics of
output stage quiescent current.

F

Figure 7. Plot of the LT1010. Die Size Is 50 × 82 Mils

A photomicrograph of the LT1010 die is shown in Figure7.
The features pointed out are identified below.

A) Output transistors were designed to maximize high
frequency performance, while obtaining some ballasting.

B) Clamp PNP base (Q17) is connected by subcollector
stripe to region furthest from Q30 collector contact to
isolate saturation resistance.

C) Output resistors are in floating tub so that IC tubs are
not forward biased when junction diodes clamp output

–

below V

.

AN16-6

G H

D) A high fT, 0.3 mil stripe, cross geometry is used for
the sink transistor driver (Q19).

E) Isolation-base transistor (Q28) carries the same 500mA
peak current as the output transistor but is much smaller.

F) MOS capacitor (C1) takes up considerable area.
G) Capacitance formed by diffusing emitter into isolation

wall takes advantage of unused area.
H) Charge storage PNP.

an16f

Application Note 16

Buffer Performance

Table 1 in the Introduction summarizes the typical speci­fications of the LT1010 buffer. The IC is supplied in three
standard power packages: the solid kovar base TO-5
(TO-39), the steel TO-3, and the plastic TO-220. The bias
terminal is not available in the TO-39 package because it has
only four leads, compared to five for the other packages.

The thermal resistance for one output transistor, excluding
the package, is 20°C/W because it was kept as small as pos­sible to enhance speed. This explains the junction-to-case
thermal resistance of 40°C/W for the TO-39 package and
25°C/W for the TO-3 and TO-220, again for one transistor.
With AC loads, both transistors will be conducting; if the
frequency is high enough, thermal resistance is reduced
by 10°C/W.

The operating case temperature range for the LT1010 is
–55°C to 125°C. The maximum junction temperature for
the internal power transistors is 150°C. A commercial
version, the LT1010C, is also available. It rated for 0°C
to 100°C case temperature with a maximum junction
temperature of 125°C.

Phase Delay

50

20

RL = 50Ω 200Ω

10

PHASE LAG (DEGREES)

5

2

51020

FREQUENCY (MHz)

Figure 9. The Phase Delay Gives More Useful Information
About High Frequency Performance Than Bandwidth. This Is
a Plot of Phase Delay as a Function of Frequency with 50Ω
and 100Ω Loads. Capacitive Loading Is 100pF, and Quiescent
Current Is Not Boosted

50

CL = 100pF

= 50Ω

R

S

= 0

I

BIAS

= 25°C

T

J

AN16 F09

The following curves describe the buffer performance in
some detail. The fact that quiescent current boost (5mA
– 40mA) is not available on the TO-39 package should
be noted.

Bandwidth

50

40

30

20

FREQUENCY (MHz)

10

0

0

QUIESCENT CURRENT (mA)

Figure 8. The Dependence of Small Signal Bandwidth on Load
Resistance and Quiescent Current Boost Is Shown Here. The
100pF Capacitive Load That Is Specified Limits the Bandwidth
That Can Be Obtained with Boost and Light Loads

RL = 200Ω

50Ω

VIN = 100mV
CL = 100pF
A

V

= 25°C

T

J

10

20

= –3dB

30

PP

40

AN16 F08

20

RL = 50Ω

10

PHASE LAG (DEGREES)

5

2

FREQUENCY (MHz)

51020

200Ω

CL = 100pF

= 50Ω

R

S

= 20Ω

R

BIAS

= 25°C

T

J

AN16 F09

Figure 10. This Shows Reduction in Phase Lag with
Quiescent Current Boosted to 40mA (R

BIAS

= 20Ω)

an16f

AN16-7

Application Note 16

Step Response Capacitive Loading

150

RL = 100Ω

= 25°C

T

J

100

50

INPUT OUTPUT

0

–50

VOLTAGE CHANGE (mV)
–100

–150

0

10 20

TIME (ns)

30

AN16 F11

Figure 11. The Small Signal Step Response with 100Ω Load
Shows a 2ns Output Delay. This Gives an Excess Phase Delay
of 15° at 20MHz, Explaining Why the –3dB Bandwidth Is
Greater Than the Frequency for 45° Phase Delay.

Output Impedance

100

I

= 0

BIAS

= 25°C

T

J

10

OUTPUT IMPEDANCE (Ω)

1.0

0.1

1 10 100

FREQUENCY (MHz)

AN16 F12

10

RS = 50Ω

= 0

I

BIAS

= 25°C

T

J

0

100pF

3nF

–10

VOLTAGE GAIN (dB)

–20

0.1

0.1μF

1 10 100

FREQUENCY (MHz)

AN16 F13

Figure 13. These Frequency Response Plots, with Capacitive
Load Only, Show That Nothing Unusual Happens as Load
Capacitance Is Varied Over a Wide Range. Minor Peaking Is
Reduced with Quiescent Current Boost

Slew Response

20

VS = ±15V

= 100Ω

R

L

15

= 25°C

T

J

f ≤ 1MHz

10

5

0

–5

OUTPUT VOLTAGE (V)

–10

–15

–20

–80

0

I

= 0

BIAS

R

= 20Ω

BIAS

50 150

100 200

TIME (ns)

POSITIVE

NEGATIVE

250

AN16 F14

Figure 12. The Unloaded Small Signal Output Impedance Stays
Down to 1MHz, Indicating the Frequency Limit of the Follower
Boost Circuitry

AN16-8

Figure 14. The Negative Slew Delay Is Reduced by Using
Quiescent Current Boost (40mA). Positive Slew Is Not
Affected by Boost.

an16f