Noty AN143f Linear Technology
Application Note 143
N
R
December 2013
A Simple Method to Accurately Predict PLL Reference
Spur Levels Due to Leakage Current
Michel Azarian and Will Ezell
Presented is a simple model that can be used to accurately
predict the level of reference spurs due to charge pump
and/or op amp leakage current in a PLL system. Knowing
how to predict these levels helps pick loop parameters
wisely during the early stages of a PLL system design.
Quick Review of PLLs
The phase locked loop (PLL) is a negative feedback system
that locks the phase and frequency of a higher frequency
device (usually a voltage controlled oscillator, VCO) whose
phase and frequency are not very stable over temperature
and time to a more stable and lower frequency device
(usually a temperature compensated or oven controlled
crystal oscillator, TCXO or OCXO). As a black box, the PLL
can be viewed as a frequency multiplier.
A PLL is employed when there is the need for a high
frequency local oscillator (LO) source. Example applica
tions are numerous and include wireless communications,
medical devices and instrumentation.
Figure 1 shows the building blocks of a PLL system used
for generating an LO signal. The PLL integrated cir
(IC)
usually contains all clock dividers (R and N), phase/
cuit
frequency detector (PFD) and the charge pump, represented
by the two current sources, ICP_UP and ICP_DN.
The VCO output is compared to the reference clock (the
OCXO output here) after both signals are divided down in
frequency by their respective integer dividers (N and R,
respectively). The PFD block controls the charge pump to
sink or source current pulses at the f
rate into the loop
PFD
filter to adjust the voltage on the tuning port of the VCO
(V_TUNE) until the outputs of the clock dividers are equal
in frequency and are in phase. When these are equal, it is
said that the PLL is locked. The LO frequency is related to
the reference frequency, f
fLO=
• f
REF
, by the following equation:
REF
The PLL shown in Figure 1 is called an integer-N PLL because the feedback divider (the N-divider) can only assume
integer values. When this divider can assume both integer
and noninteger values, the loop is called a fractional-N
PLL. The focus here will be only on integer-N PLLs, as
different mechanisms are at work in fractional-N PLLs.
Integer
-N PLL Nonidealities
The PLL IC contributes its own nonidealities to the system,
principally phase noise and spurious.
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property of their respective owners.
V_CP
= f
OCXO
PLL IC
÷R
f
PFD
PFD
÷N
Figure 1. Basic Building Blocks of a PLL
ICP_UP
ICP_DN
LOOP FILTER
CPR
V_VCO
VCO
V_TUNE
Z
C
I
f
LO
FEEDBACK
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LO
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V_OCXO
OCXO
f
REF
Application Note 143
Phase Noise
The PLL system of Figure 1 acts as a low pass filter on the
reference clock phase noise and as a high pass filter on
that of the VCO. The low pass and high pass filter cutoff
frequency is defined by the loop bandwidth (LBW) of the
PLL. Ideally, the LO phase noise follows that of the reference
clock converted to the LO frequency (that is, multiplied by
N/R) up to the LBW and subsequently follows the phase
noise of the VCO. The PLL IC’s noise contribution elevates
the phase noise in the transition area.
Figure 2 is a phase noise plot generated by PLLWiz
ard™, a free PLL design and simulation tool from Linear
Technology. The figure shows both the total output phase
(TOTAL), and the individual noises at the output
noise
due to the reference (REF at RF) and the VCO (VCO at
RF). The IC’s noise contribution can easily be seen in the
highlighted area.
–40
–50
–60
–70
–80
–90
–100
–110
–120
PHASE NOISE (dBc/Hz)
–130
–140
–150
–160
100
Figure 2. PLL IC Phase Noise Contribution Region as Highlighted
by the Drawn Ellipse
1k
OFFSET FREQUENCY (Hz)
10k
VCO AT RF
REF AT RF
TOTAL
100k 1M
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Spurious
Any unwanted signals on the power supplies shown in
Figure 1 (V_OCXO, V_CP and V_VCO) can translate into
spurious (spurs) on the LO signal. Careful design of these
supplies greatly reduces or even eliminates these spurs.
Charge pump related spurs, however, are inevitable. But,
they can be reduced with careful PLL system design.
These spurs are commonly referred to as reference spurs,
though reference here does not mean the reference clock
frequency. Rather, it refers to f
by an integer-N PLL has dual sideband spurs at f
. An LO signal produced
PFD
PFD
and
its harmonics.
For example, Figure 3 shows the spectrum of a 2.1GHz LO
signal. f
is 1MHz (N = 2100) and the reference clock
PFD
is 10MHz (R = 10). The loop bandwidth is 40kHz. As a
side note, it is worth mentioning that the spurious level
achieved in this measurement is world class due to the
high performance of the LTC6945, an ultralow noise and
spurious PLL IC from Linear Technology.
0
–20
–40
–60
–80
AMPLITUDE (dBc)
–100
–120
–140
2096
Figure 3. Reference Spurs of a 2100 MHz LO Signal with an
f
of 1MHz Generated Using the LTC6945 PLL IC from Linear
PFD
Technology Along with the UMX-586-D16-G VCO from RFMD
2100
2098
FREQUENCY (MHz)
2102 2104
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Causes of Reference Spurs
In steady-state operation, the PLL is locked, and, theoretically, there is no more need to engage the ICP_UP and
ICP_DN current sour
ces of Figure 1 during ever
y PFD
cycle. However, doing so would create a dead zone in the
loop response as there is a significant drop in the smallsignal loop gain (practically, an open loop). This dead zone
is eliminated by forcing ICP_UP and ICP_DN to produce
extremely narrow pulses during every PFD cycle. These
are commonly referred to as anti-backlash pulses. This
produces energy content on the VCO tune line at f
PFD
and
its harmonics. The negative feedback cannot counteract
these pulses since these frequencies are outside the loop
bandwidth of a properly designed PLL. The VCO, then, is
frequency modulated (FM) by this energy content, and
related spurs appear at f
and its harmonics, all centered
PFD
around LO.
Between anti-backlash pulses, the charge pump current
sources are off (tri-stated). Inherently, the charge pump
has some leakage current when tri-stated. Using an op amp
in an active loop filter (such as in Figure 7) introduces yet
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Application Note 143
another leakage current source due to the op amp’s input
bias and offset currents. The aggregate of these unwanted
currents, whether sourcing or sinking, causes a drift in
the voltage across the loop filter and, consequently, in
the tune voltage of the VCO. The negative feedback of the
loop will correct for this anomaly by introducing a unipolar
current pulse from the charge pump once every PFD cycle
so that the average tune line voltage produces the correct
frequency out of the VCO. The pulses produce energy at
, which also causes spurs to appear centered around LO
f
PFD
and offset by f
In integer-N PLLs, f
and its harmonics as previously noted.
PFD
is often chosen to be relatively small
PFD
because of the system’s frequency step size requirements.
This means that the anti-backlash pulse width, especially
with the present high speed IC technologies, is extremely
small compared to the PFD period. As such, a large leak
age current causes the total charge pump pulses to be
unipolar and tends to be the dominant cause of reference
spurs.
This phenomenon will
be examined in more depth.
Reference Spurs’ Effect on System Performance
In a particular communications frequency band there are
multiple channels that occupy equal bandwidths. The
center-to-center frequency distance between two adjacent
channels is equal among all channels and is denoted by
channel spacing. Due to several factors, it is common to
find large variations in signal strength between any two
adjacent channels.
DESIRED
f
IF
CHANNEL AT IF
ADJACENT
CHANNEL AT IF
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ADJACENT
CHANNEL
DESIRED
CHANNEL
CHANNEL
SPACING
f
RF
Figure 4. Illustration of Adjacent Channel Interference Due to
Reference Spurs
MIXER
RF IF
LO
CHANNEL
SPACING
f
LO
REFERENCE
SPUR
Relationship Between Leakage Current and Reference
Spur Levels
The mathematical prediction of a PLL IC’s phase noise
contribution is relatively straightforward and can be ac
curately determined by calculations. However, the prediction of reference spur levels is traditionally believed to
be complex. This section derives a method to accurately
predict reference spur levels due to leakage current using
simple calculations. T
wo examples using different loop
filters will be examined.
Passive Loop Filter Example
A typical scenario in a multi-channel wireless communi
cations system where a stronger channel exists adjacent
to the desired but weaker channel is shown in Figure 4.
Only one of the LO reference spurs of concern is shown.
In an integer-N PLL, f
is usually chosen to be equal
PFD
to the channel spacing, which means that the reference
spurs are positioned at the channel spacing from the LO.
These spurs translate all adjacent and nearby channels to
the center of the intermediate frequency (f
) along with
IF
the LO mixing the desired channel to the same frequency.
These undesired channels, being uncorrelated to the signal
in the desired channel, appear as an elevated noise floor
to the desired signal and limit the signal-to-noise ratio.
A PLL system with a typical passive loop filter is shown in
Figure 5 along with a current sour
to represent the leakage current of the charge pump. As
ce denoted I_LEAKAGE
suming the PLL is locked, I_LEAKAGE reduces the charge
held by C
during the time when the charge pump is off.
P
When the charge pump turns on once every PFD cycle,
ICP_UP replenishes the charge lost from C
by applying
P
a short pulse of current. Feedback forces the average
voltage seen at V_TUNE (V_TUNE_AVG) to be constant,
maintaining the correct LO frequency. Figure 6 depicts
this visually.
The derivation of the resultant spurs involves some knowl
edge of loop stability requirements, the first being LBW
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