Noty an136f Linear Technology
Application Note 136
June 2012
PCB Layout Considerations for Non-Isolated Switching
Power Supplies
Henry J. Zhang
Introduction
The best news when you power up a prototype supply board
for the very first time is when it not only works, but also
runs quiet and cool. Unfortunately, this does not always
happen. A common problem of switching power supplies
is “unstable” switching waveforms. Sometimes, waveform
jittering is so pronounced that audible noise can be heard
from the magnetic components. If the problem is related
to the printed circuit board (PCB) layout, identifying the
cause can be difficult. This is why proper PCB layout at
the early stage of a switching supply design is very critical.
Its importance cannot be overstated.
The power supply designer is the person who best understands the technical details and functional requirements of
the supply within the final product. He or she should work
closely with the PCB layout designer on the critical supply
layout from the beginning. A good layout design optimizes
supply efficiency, alleviates thermal stress, and most importantly, minimizes the noise and interactions among traces
and components. To achieve these, it is important for the
designer to understand the current conduction paths and
signal flows in the switching power supply. The following
discussion presents design considerations for a proper
layout design for non-isolated switching power supplies.
PLAN OF THE LAYOUT
Location of the Power Supply in System Board
For the embedded DC/DC supply on a large system board,
the supply output should be located close to the load devices in order to minimize the interconnection impedance
and the conduction voltage drop across the PCB traces to
achieve best voltage regulation, load transient response
and system efficiency. If forced-air cooling is available,
the supply should also be located close to the cooling
fan or have good air flow to limit the thermal stress. In
addition, the large passive components such as inductors
and electrolytic capacitors should not block the air flow
to the low profile, surface mount semiconductor components such as power MOSFETs, PWM controller, etc. To
prevent the switching noise from upsetting other analog
signals in the system, avoid routing sensitive signal traces
underneath the supply if possible. Otherwise, an internal
ground plane between the power supply layer and small
signal layer is needed for shielding.
It is necessary to point out that this power supply location and board real estate planning should be done at the
early design/planning stage of the system. Unfortunately,
sometimes people focus on other more “important” or
“exciting” circuits on the big system board first. If power
management/supply is the last thought and is relegated
to whatever space is left on the board, this certainly does
not help ensure efficient and reliable power supply design.
Placement of Layers
On a multilayer PCB board, it is highly desirable to place
the DC ground or DC input or output voltage layers between the high current power component layer and the
sensitive small signal trace layer. The ground and/or DC
voltage layers provide AC grounds to shield the small signal
traces from noisy power traces and power components.
As a general rule, the ground or DC voltage planes of a
multilayer PCB should not be segmented. If the segmentation is unavoidable, the number and length of traces in
these planes must be minimized. The traces should also
be routed in the same direction as the high current flow
direction to minimize the impact.
Figures 1a and 1c provide examples of the undesired layer
arrangement of the 6-layer and 4-layer PCB boards for
switching power supply. In these examples, the small signal
layer is sandwiched between the high current power layer
and the ground layer. These configurations increase the
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owners.
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Application Note 136
Undesired
Layer 1 - Power Component
Layer 2 - Small Signal
Layer 3 - GND Plane
Layer 4 - DC Voltage or GND Plane
Layer 5 - Small Signal
Layer 6 - Power Component/Controller
(a)
Undesired
Layer 1 - Power Component
Layer 2 - Small Signal
Layer 3 - GND Plane
Layer 4 - Small Signal/Controller
(c)
Figure 1. Desired and Undesired Layer Arrangement of 6-Layer and 4-Layer PCBs
capacitive noise coupling between the high current/voltage
power layer and small analog signal layer. To minimize
the noise coupling, Figures 1b and 1d show examples
of desired layer arrangement for 4-layer and 6-layer PCB
designs. In these two examples, the small signal layer is
shielded by the ground layer(s). It is important to always
have a ground layer next to the outside power stage layer.
Finally, it is also desirable to have thick copper for the
external high current power layers to minimize the PCB
conduction loss and thermal impedance.
POWER STAGE COMPONENT LAYOUT
A switching power supply circuit can be divided into the
power stage circuit and the small signal control circuit.
The power stage circuit includes the components that
conduct high current. In general, these components
should be placed first. The small signal control circuitry
is subsequently placed in specific spot in the layout. In
this section, we will discuss the layout of power stage
components.
Continuous and Pulsating Current Paths – Minimize
Inductance in High di/dt Loop (Hot Loop)
The large current traces should be short and wide to minimize PCB inductance, resistance and voltage drop. This is
especially critical for the traces with high di/dt pulsating
current flow. Figure 2 identifies the continuous current and
pulsating current paths in a synchronous buck converter.
Desired
Layer 1 - Power Component
Layer 2 - GND Plane
Layer 3 - Small Signal
Layer 4 - Small Signal
Layer 5 - DC Voltage or GND Plane
Layer 6 - Power Component/Controller
(b)
Desired
Layer 1 - Power Component
Layer 2 - GND Plane
Layer 3 - Small Signal
Layer 4 - Small Signal/Controller
(d)
AN136 F01
The solid line represents the continuous current paths,
and the dashed line represents the pulsating (switching)
current paths. The pulsating current paths include the
traces connected to the input decoupling ceramic capacitor,
, the top control FET, QT, the bottom synchronous FET,
C
HF
, and its optional paralleled Schottky diode. Figure 3a
Q
B
shows the parasitic PCB inductors in these high di/dt current paths. Due to the parasitic inductance, the pulsating
current paths not only radiate magnetic fields, but also
generate high voltage ringing and spikes across the PCB
traces and MOSFETs. To minimize the PCB inductance,
this pulsating current loop (hot loop) should be laid out
so that it has a minimum circumference and is composed
of traces that are short and wide. The high frequency decoupling capacitor, C
, should be a 0.1F to 10F, X5R
HF
or X7R dielectric ceramic capacitor with very low ESL and
ESR. Higher-capacitance dielectrics (such as Y5V) can
allow a large reduction in capacitance over voltage and
temperature. Therefore, these kinds of capacitors are not
preferred for C
HF
.
Figure 3b provides a layout example of the critical pulsating
current loop (hot loop) in the buck converter. To limited
resistive voltage drops and the number of vias, power
components should be placed on the same side of board,
with power traces routed on the same layer. When it becomes necessary to route a power trace to another layer,
choose a trace in the continuous current paths. When vias
are used to connect PCB layers in the high current loop,
multiple vias should be used to minimize via impedance.
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Application Note 136
VIN+
HIGH dV/dt NODE
Q
T
ESR
IN
+
V
IN
–
C
IN
C
HF
SW
PGND
Q
B
L
F
ESR
OUT
C
D
OUT
RV
OUT
+
–
CONTINUE CURRENT
PULSATING CURRENT
AN136 F02
Figure 2. Continuous and Pulsating Current Paths of a Synchronous Buck Converter
+
V
IN
Q
T
Q
T
C
HF
PGND
SW
VIN+
C
D
Q
B
0.1µF TO 10µF
CERAMIC CAPACITOR
HF
Q
MINIMIZE THIS
LOOP AREA
SW
B
PGND
(a) (b)
+
D
AN136 F03
L
F
Figure 3. Minimize the High di/dt Loop Area in the Synchronous Buck Converter.
(a) High di/dt loop (Hot Loop) and its Parasitic PCB Inductors, (b) Layout Example
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Application Note 136
+
V
IN
–
C
IN
HIGH dV/dt NODE
L
F
SW
D
Q
B
V
+
OUT
C
HF
C
OUT
V
OUT
LOAD
PGND
CONTINUE CURRENT
PULSATING CURRENT
Figure 4. Continuous and Pulsating Current Paths of a Boost Converter
L
F
SW
PGND
D
C
Q
B
HF
(a) (b)
Figure 5. Minimize the High di/dt Loop Area in the Boost Converter.
(a) High di/dt Loop (Hot Loop) and its Parasitic PCB Inductors, (b) Layout Example
Similarly, Figure 4 shows the continuous and pulsating
current loops (hot loop) in the boost converter. In this
case, the high frequency ceramic capacitor, C
be placed on the output side close to the MOSFET, Q
boost diode, D. The loop formed by switch, Q
diode, D, and high frequency output capacitor, C
, should
HF
, and
B
, rectifier
B
, must
HF
be minimized. Figure 5 shows the layout example of the
pulsating current loop in the boost converter.
To emphasize the importance of the decoupling capacitor C
, Figures 6 and 7 provide an actual example of a
HF
synchronous buck circuit. Figure 6a shows the layout of
a dual phase, 12V
to 2.5V
IN
buck supply using the LTC3729 2-phase, single V
/30A max, synchronous
OUT
OUT
controller IC. As shown in Figure 6a, the switching nodes
SW1 and SW2 and output inductor current i
waveforms
LF1
are stable at no load. But if the load current increases
to above 13A, the SW1 node waveform starts missing
cycles. The problem becomes even worse with higher load
AN136 F04
L
F
Q
SW
B
+
D
PGND
MINIMIZE THIS
LOOP AREA
C
HF
0.1µF TO 10µF
CERAMIC CAPACITOR
AN136 F05
current. Figure 7 shows that adding one 1F high frequency
ceramic capacitors on each channel’s input side solves
the problem. It separates and minimzes the hot loop area
of each channel. The switching waveform is stable even
with maximum load current up to 30A.
Isolate and Minimize High dv/dt Switching Area
In Figures 2 and 4, the SW node voltage swings between
(or V
V
IN
) and ground with a high dv/dt rate. This
OUT
node is rich in high frequency noise components and is
a strong source of EMI noise. To minimize the coupling
capacitance between SW node and other noise-sensitive
traces, the SW copper area should be minimized. However,
on the other hand, to conduct high inductor current and
provide a heat sink to the power MOSFET, the SW node
PCB area cannot be too small. It is usually preferred to
have a ground copper area placed underneath this SW
node to provide additional shielding.
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Application Note 136
+
(12V)
V
IN
L
Q
C
IN
T
F1
SW1
V
OUT
+
(2.5V)
I
V
LF1
SW1
LTC3729
C
OUT
Q
B
GND
GND
C
OUT
SW2
+
V
IN
+
V
(2.5V)
OUT
(a)
V
SW1
I
LF1
I
OUT
= 0A
V
SW2
AN136 F06b
I
OUT
V
= 13.3A
SW2
(b) (c)
Figure 6. An Example of a 2-Phase, 2.5V/30A Output Buck Converter with Noise Problem.
(a) Layout, (b) Switching Waveform at I
= 0A, (c) Switching Waveform at I
OUT
OUT
AN136 F06c
= 13.3A
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