Noty an128f Linear Technology

Application Note 128

2 Nanosecond, 0.1% Resolution Settling Time
Measurement for Wideband Amplifiers

Quantifying Quick Quiescence

Jim Williams

June 2010

INTRODUCTION

Instrumentation, waveform synthesis, data acquisition,
feedback control systems and other application areas uti­lize wideband amplifiers. Current generation components
(see box section, page 2, “A Precision Wideband Amplifier
with 9ns Settling Time”) feature good DC precision while
maintaining high speed operation. Verifying precision
operation at high speed is essential, and presents a high
order measurement challenge.

SETTLING TIME DEFINED

Amplifier DC specifications are relatively easy to verify.
Measurement techniques are well understood, albeit
often tedious. AC specifications require more sophis­ticated approaches to produce reliable information. In
particular, amplifier settling time is extraordinarily difficult
to determine. Settling time is the elapsed time from input
application until the output arrives at and remains within
a specified error band around the final value. It is usually
specified for a full-scale transition. Figure 1 shows that
settling time has three distinct components. The delay time
is small and almost entirely due to amplifier propagation
delay. During this interval there is no output movement.

SETTLING TIME

INPUT

RING TIME

During slew time the amplifier moves at its highest pos-
sible speed towards the final value. Ring time defines the
region where the amplifier recovers from slewing and
ceases movement within some defined error band. There
is normally a trade-off between slew and ring time. Fast
slewing amplifiers generally have extended ring times,
complicating amplifier choice and frequency compensation.
Additionally, the architecture of very fast amplifiers usually

1

dictates trade-offs which degrade DC error terms

.

Measuring anything at any speed requires care. Dynamic
measurement is particularly challenging. Reliable nano­second region settling time measurement constitutes a
high order difficulty problem requiring exceptional care

2

in approach and experimental technique

.

CONSIDERATIONS FOR MEASURING NANOSECOND
REGION SETTLING TIME

Historically, settling time has been measured with circuits
similar to that in Figure 2. The circuit uses the “false sum
node” technique. The resistors and amplifier form a bridge
type network. Assuming ideal resistors, the amplifier output
will step to –V

when the input is driven. During slew,

IN

the settle node is bounded by the diodes, limiting voltage
excursion. When settling occurs, the oscilloscope probe
voltage should be zero. Note that the resistor divider’s
attenuation means the probe’s output will be one-half of
the actual settled voltage.

ALLOWABLE

OUTPUT

ERROR

OUTPUT

Figure 1. Settling Time Components Include Delay, Slew and
Ring Times. Fast Amplifiers Reduce Slew Time, Although
Longer Ring Time Usually Results. Delay Time Is Normally a
Small Term

SLEW

TIME

DELAY TIME

BAND

AN128 F01

In theory, this circuit allows settling to be observed to
small amplitudes. In practice, it cannot be relied upon to
produce useful measurements. Several flaws exist. The

Note 1. This issue is treated in detail in latter portions of the text. Also see
Appendix B, “Practical Considerations for Amplifier Compensation”.
Note 2. The approach used for settling time measurement and its
description, while new, borrows from previous publications. See
References 1-5, and Reference 9.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.

an128f

AN128-1

Application Note 128

INPUT STEP TO
OSCILLOSCOPE

POSITIVE INPUT

FROM PULSE

GENERATOR

Figure 2. Popular Summing Scheme for Settling Time
Measurement Provides Misleading Results. Pulse Generator
Post-Transition Aberrations Appear at Output. Large Oscilloscope
Overdrive Occurs. Displayed Information Is Meaningless

–

AMPLIFIER

+

R

R

+V

REF

OUTPUT TO
OSCILLOSCOPE

AN128 F02

circuit requires the input pulse to have a flat top within the
required measurement limits. Typically, settling within 5mV
or less for a 5V step is of interest. No general purpose pulse
generator is meant to hold output amplitude and noise within
these limits. Generator output-caused aberrations appear­ing at the oscilloscope probe will be indistinguishable from

A PRECISION WIDEBAND AMPLIFIER WITH 9ns
SETTLING TIME

Historically, wideband amplifiers provided speed, but
sacrificed precision and, often, settling time. The LT1818
op amp does not require this compromise. It features
low offset voltage and bias current with adequate gain
for 0.1% accuracy. Settling time is 9ns to 0.1% for a
5V step. The output will drive a 100 load to ±3.75V
with ±5V supplies, and up to 20pF capacitive loading
is permissible at unity gain. The table below provides
short form specifications.

LT1818 Short Form Specifications

CHARACTERISTIC SPECIFICATION

Offset Voltage 0.2mV
Offset Voltage vs Temperature 10µV/°C
Bias Current 2µA
DC Gain 2500
Noise Voltage 6nV/√Hz
Output Current 70mA
Slew Rate 2500V/µs
Gain-Bandwidth 400MHz
Delay 1ns
Settling Time 9ns/0.1%
Supply Current 9mA

amplifier output movement, producing unreliable results.
The oscilloscope connection also presents problems. As
probe capacitance rises, AC loading of the resistor junction
influences observed settling waveforms. 1x probes are not
suitable because of their excessive input capacitance. A 10x
probe’s attenuation sacrifices oscilloscope gain and its 10pF
capacitance still introduces significant lag at nanosecond
speeds. An active 1x, 1pF FET probe largely alleviates the
problem but a more serious issue remains.

The clamp diodes at the settle node are intended to reduce
swing during amplifier slewing, preventing excessive oscil­loscope overdrive. Unfortunately, oscilloscope overdrive
recovery characteristics vary widely among different types
and are not usually specified. The Schottky diodes’ 400mV
drop means the oscilloscope will undergo an unacceptable

3

overload, bringing displayed results into question

.

At 0.1% resolution (5mV at the amplifier output –2.5mV at
the oscilloscope), the oscilloscope typically undergoes a
10x overdrive at 10mV/DIV, and the desired 2.5mV baseline
is unattainable. At nanosecond speeds, the measurement
becomes hopeless with this arrangement. There is clearly
no chance of measurement integrity.

The preceding discussion indicates that measuring ampli­fier settling time requires an oscilloscope that is somehow
immune to overdrive and a “flat top” pulse generator. These
become the central issues in wideband amplifier settling
time measurement.

The only oscilloscope technology that offers inherent

4

overdrive immunity is the classical sampling ‘scope

.
Unfortunately, these instruments are no longer manufac­tured (although still available on the secondary market).
It is possible, however, to construct a circuit that borrows
the overload advantages of classical sampling ‘scope
technology. Additionally, the circuit can be endowed with
features particularly suited for measuring nanosecond
range settling time.

Note 3. For a discussion of oscilloscope overdrive considerations, see
Appendix C, “Evaluating Oscilloscope Overdrive Performance”.
Note 4. Classical sampling oscilloscopes should not be confused with
modern era digital sampling ‘scopes that have overdrive restrictions.
See Appendix C, “Evaluating Oscilloscope Overload Performance” for
comparisons of various type ‘scopes with respect to overdrive. For
detailed discussion of classical sampling ‘scope operation, see References
23-26 and 29-31. Reference 24 is noteworthy; it is the most clearly
written, concise explanation of classical sampling instruments the author
is aware of—a 12-page jewel.

an128f

AN128-2

Application Note 128

The flat-top pulse generator requirement can be avoided by
switching current, rather than voltage. It is much easier to
gate a quickly settling current into the amplifier’s summing
node than to control a voltage. This makes the input pulse
generator’s job easier, although it still must have a rise time
of about 1 nanosecond to avoid measurement errors.

PRACTICAL NANOSECOND SETTLING TIME
MEASUREMENT

Figure 3 is a conceptual diagram of a settling time measure­ment circuit. This figure shares attributes with Figure 2,
although some new features appear. In this case, the
oscilloscope is connected to the settle point by a switch.
The switch state is determined by a delayed pulse genera­tor, which is triggered from the input pulse. The delayed
pulse generator’s timing is arranged so that the switch
does not close until settling is very nearly complete. In
this way, the incoming waveform is sampled in time, as
well as amplitude. The oscilloscope is never subjected to
overdrive—no off-screen activity ever occurs.

A switch at the amplifier’s summing junction is controlled
by the input pulse. This switch gates current to the amplifier
via a voltage-driven resistor. This eliminates the “flat-top”
pulse generator requirement, although the switch must
be fast and devoid of drive artifacts.

Figure 4 is a more complete representation of the settling
time scheme. Figure 3’s blocks appear in greater detail and
some new refinements show up. The amplifier summing
area is unchanged. Figure 3’s delayed pulse generator has

+V

CURRENT

SWITCH

INPUT FROM

PULSE

GENERATOR

Figure 3. Conceptual Arrangement Is Insensitive to Pulse
Generator Aberrations and Eliminates Oscilloscope Overdrive.
Input Switch Gates Current Step to Amplifier. Second Switch,
Controlled by Delayed Pulse Generator, Prevents Oscilloscope
from Monitoring Settle Node Until Settling Is Nearly Complete

–

AMPLIFIER

+

SETTLE
NODE

+V

REF

DELAYED

PULSE

GENERATOR

SWITCH

AN128 F03

OUTPUT TO
OSCILLOSCOPE

been split into two blocks; a delay and a pulse generator,
both independently variable. The input step to the oscil­loscope runs through a section that compensates for the
propagation delay of the settling time measurement path.
Similarly, another delay compensates sample gate pulse
generator propagation delay. This delay causes the sample
gate pulse generator to be driven with a phase-advanced
version of the pulse which triggers the amplifier under test.
This considerably improves minimum measurable settling
time by making sample gate pulse generator propagation
delay irrelevant.

The most striking new aspects of the diagram are the diode
bridge switch and the multiplier. The diode bridge’s bal­ance, combined with matched, low capacitance Schottky
diodes and high speed drive, yields clean switching. The
bridge switches current into the amplifier’s summing point
very quickly, with settling inside a nanosecond . The diode
clamp to ground prevents excessive bridge drive swings
and ensures that non-ideal input pulse characteristics are
nearly irrelevant.

Requirements for Figure 4’s sample gate are stringent.
It must faithfully pass wideband signal path information
without introducing alien components, particularly those
deriving from the switch command channel (“sample

5

gate pulse”)

.

The sample gate multiplier functions as a wideband, high
resolution, extremely low feedthrough switch. The great
advantage of this approach is that the switch control
channel can be maintained in-band; that is, its transition
rate is held within the multipliers 250MHz bandpass. The
multipliers wide bandwidth means the switch command
transition is under control at all times. There are no out­of-band responses, greatly reducing feedthrough and
parasitic artifacts.

Note 5. Conventional choices for the sample gate switch include FET’s
and the sampling diode bridge. FET parasitic gate to channel capacitances
result in large gate drive originated feedthrough into the signal path. For
almost all FETs, this feedthrough is many times larger than the signal to
be observed, inducing overload and obviating the switches’ purpose. The
diode bridge is better; its small parasitic capacitances tend to cancel and
the symmetrical, differential structure results in very low feedthrough.
Practically, the bridge requires DC and AC trims and complex drive and
support circuitry. LTC Application Note 74, “Component and Measurement
Advances Ensure 16-bit DAC Settling Time” utilized such a sampling
bridge and it is detailed in that text. See Reference 3. References 2, 9 and
11 describe a similar sampling bridge based approach.

an128f

AN128-3

Application Note 128

TIME-CORRECTED
INPUT STEP TO
OSCILLOSCOPE

SAMPLE

GATE

Y

X

X

SAMPLE
GATE
PULSE

OUTPUT TO
OSCILLOSCOPE

W

SETTLE NODE



2

X • Y = W

PULSE

GENERATOR

INPUT

SAMPLE GATE

PULSE GENERATOR

DELAY COMPENSATION

CURRENT

SWITCH

+V

–

+

–V

SAMPLE GATE PULSE GENERATOR

VARIABLE

DELAY

AMPLIFIER

UNDER TEST

VARIABLE WIDTH

PULSE GENERATOR

SIGNAL PATH

DELAY COMPENSATION

SETTLE

NODE

R

R

+V

REF

SAMPLE GATE

DRIVER

s1

AN128 F04

Figure 4. Block Diagram of Settling Time Measurement Scheme. Diode Bridge Cleanly Switches Input Current to Amplifier. Multiplier
Based Sampling “Switch” Eliminates Signal Paths Pre-Settling Excursion, Preventing Oscilloscope Overdrive. Input Step Time
Reference and Sample Gate Pulse Generator Are Compensated for Test Circuit Delays

DETAILED SETTLING TIME CIRCUITRY

Figure 5 is a detailed schematic of the settling time mea­surement circuitry. The input pulse switches the input
bridge via a delay network (“A” inverters) and a driver
stage (“C” inverters). The delay compensates the sample
gate pulse generator’s delayed response, ensuring that
the sample gate pulse can occur immediately after the
amplifier-under-tests’ slew time ends. The delay range is
chosen so that the sample gate pulse can be adjusted to
occur before the amplifier slews. This capability is obvi­ously unused in operation although it guarantees that the
settling interval will always be capturable.

The “C” inverters form a non-inverting driver stage to
switch the diode bridge. Various trims optimize driver
output pulse shape, providing a clean, fast impulse to the

6

diode bridge

. The high fidelity pulse, devoid of undamped
components, prevents radiation and disruptive ground
currents from degrading the measurement noise floor.
The driver also activates the “B” inverters, which supply
a time corrected input step to the oscilloscope.

The driver output pulse transitions through the 1N5712
diode clamp potential in under a nanosecond, causing
essentially instantaneous diode bridge switching. The
resultant cleanly settling current into the amplifier under
tests’ summing point causes proportionate amplifier output

movement. The negative bias current at the amplifiers
summing point combined with the current step produces a
+2.5V to –2.5V amplifier output transition. The amplifier’s
output is compared against a 5V supply derived reference
via the summing resistors. The clamped “settle node” is
unloaded by A1, which feeds the sample gate signal path
information.

The comparator based sample gate pulse generator pro­duces a delayed (controllable by the 20k potentiometer)
pulse whose width (controllable by the 2k potentiometer)
sets sample gate on-time. The Q1 stage forms the sample
gate pulse into a fast rise, exceptionally clean event, furnish­ing high purity, calibrated amplitude, “on-off” switching
instruction to the sample gate multiplier. If the sample gate
pulse delay is set appropriately, the oscilloscope will not
see any input until settling is nearly complete, eliminating
overdrive. The sample window width is adjusted so that
all remaining settling activity is observable. In this way,
the oscilloscope’s output is reliable and meaningful data
may be taken.

Figure 6 shows circuit waveforms. Trace A is the time-cor­rected input pulse, Trace B the amplifier output, Trace C the

Note 6. To maintain text flow and focus, trimming procedures are not
presented here. Detailed trimming information appears in Appendix
A, “Measuring and Compensating Settling Circuit Delay and Trimming
Procedures.”

an128f

AN128-4

+5

SETTLE

NODE

PULSE

INPUT

AN128 F05

1k*

2k*

200

453*

130

43

200

82

2pF

499*

C

F

, SELECT 1pF TO 8pF

(SEE APPENDIX B)

453*

TIME-CORRECTED

INPUT STEP TO

OSCILLOSCOPE

ALL TRIMMING PROCEDURES DETAILED IN APPENDIX A.

* = 1% METAL FILM RESISTOR

** = HSMS-2860, MATCHED 1 MILLIVOLT AT 10mA

= 1/6 74AHC04. LETTER; e.g. “A”, “B”, “C” DENOTES

SEPARATE PACKAGE. GROUND ALL UNUSED INPUTS.

= FERRITE BEAD, FERRONICS #21-11OJ.

INPUT 50 TERMINATION MUST BE IN-LINE COAXIAL TYPE—DO NOT USE BOARD MOUNTED RESISTOR.

+5V AND –5V SUPPLIES DERIVED FROM BOARD MOUNTED REGULATORS. LT1175 = –5V, LT1761 = 5V.

TRIM BOTH SUPPLIES—0.1%.

BYPASSING NOT SHOWN EXCEPT FOR AD835. BYPASS EACH IC AND INDICATED SUPPLY POINTS WITH

10µF SANYO OSCON PARALLELED WITH 0.1µF FILM CAPACITOR.

SAMPLE GATE

DRIVER

CURRENT

SWITCH

+5V

CURRENT

SWITCH

DRIVER

SCALE

FACTOR

–5V

–

+

SAMPLE GATE PULSE GENERATOR

SAMPLE GATE

SIGNAL PATH DELAY COMPENSATION (8.6ns)

SAMPLE GATE

PULSE GENERATOR PATH

DELAY COMPENSATION (15ns)

Z

W

X

+V

–V

–5

+5

–5

+5

AD835

Y1X1Y2

X2

LT1818

+

–

1/2

LT1720

C2

–

+

LT1818

A1

AMPLIFIER

UNDER TEST

HSMS-2860

2s

HSMS-2860**

4s

OUTPUT TO

OSCILLOSCOPE

SETTLE NODE

1.5



47

1k

PULSE

TOP SMOOTHING

1pF

SAMPLE

GATE

PULSE

SETTLE

NODE

ZERO

1k

1.5k*

50

SEE NOTES

150

500

TOP

FRONT

CORNER

+5

+5

+5

1k*

–5

0.1µF 4.7µF

1pF

0.1µF 4.7µF
2pF TO 10pF

EDGE TIME

10pF

1pF

+5 –5

10k

Y OFFSET

1k

X OFFSET

1k

12pF

10k

1k

DELAY

B

B

+5

CX5

+5

C

AA

1k

DELAY

1k

5pF

20pF

20pF

100

BOTTOM

FRONT

CORNER

TOP

FRONT

CORNER

TOP

REAR

CORNER

24pF

15pF

82

100

BOTTOM REAR

CORNER-TRAILING

ABBERATIONS

IN5711

Q1

2N4260

IN5712

20

1.6k*

3.4k* 261*

2k*

100

SAMPLE GATE

PULSE AMPLITUDE

100

FRONT

CORNER

PURITY

IN5711

0.1µF

82pF

+5

0.1µF

47µF

20

2k*

1k

+

–

1/2

LT1720

C1

+

–

1/2

LT1720

C3

IN5711

1k

2k

SAMPLE

WINDOW WIDTH

50ns TO 110ns

20k

SAMPLE

WINDOW DELAY

9ns TO 150ns

2.5k

FEEDTHROUGH

COMPENSATION

TIME PHASE

100

FEEDTHROUGH

COMPENSATION

AMPLITUDE

+

+

+

–5 +5

OUTPUT

OFFSET

1k

X • Y = W

16k

392

Application Note 128

Figure 5. Detailed Schematic of Settling Time Measurement Circuitry Follows Block Diagram. Trimmed, Paralleled Logic Inverters Provide High Speed Drive to

Current Switch Bridge. Additional Inverters Form Delay Compensation Networks for Signal Path and Sample Gate Pulse Generator. Transistor Stage Shapes Edges and

Amplitude of Sample Gate Pulse Supplied to Multiplier. Multiplier, Functioning as Sample Gate, Passes Settling Time Signal when Sample Gate Pulse Is High

an128f

AN128-5

Application Note 128

7

sample gate pulse and Trace D the settling time output
When the sample gate pulse goes high, the sample gate
switches cleanly, and the last 20mV of slew are easily ob­served. Ring time is also clearly visible, and the amplifier
settles nicely to final value. When the sample gate pulse
goes low, the sample gate switches off with only 2mV of
feedthrough. Note that there is no off-screen activity at any
time—the oscilloscope is never subjected to overdrive.

Figure 7 expands vertical and horizontal scales so that

8

settling detail is more visible

. Trace A is the time-cor­rected input pulse and Trace B the settling output. The
last 50mV of slew are easily observed, and the amplifier
settles inside 5mV (0.1%) in 9 nanoseconds when CF (see

9

Figure 5) is optimized

A = 5V/DIV

B = 5V/DIV

C = 5V/DIV

D = 10mV/DIV

Figure 6. Settling Time Circuit Waveforms Include Time­Corrected Input Pulse (Trace A), Amplifier-Under-Test Output
(Trace B), Sample Gate (Trace C) and Settling Time Output
(Trace D). Sample Gate Window’s Delay and Width Are
Variable. Trace B Appears Time Skewed Relative to Time
Corrected Trace A.

.

HORIZ = 20ns/DIV

AN128 F06

.

USING THE SAMPLING-BASED SETTLING TIME CIRCUIT

In general, it is good practice to walk the sampling window
“backwards” in time up to the last 50mV or so of ampli­fier slewing so that the onset of ring time is observable
without encountering oscilloscope overdrive. The sam­pling based approach provides this capability and it is a
very powerful measurement tool. Slower amplifiers may
require extended delay and/or sampling window times,
necessitating larger capacitor values in the delayed pulse
generator timing networks.

VERIFYING RESULTS–ALTERNATE METHOD

The sampling-based settling time circuit appears to be
a useful measurement solution. How can its results be
tested to ensure confidence? A good way is to make the
same measurement with an alternate method and see if
results agree. It was stated earlier that classical sampling

10

oscilloscopes were inherently immune to overdrive

. If
this is so, why not utilize this feature and attempt settling
time measurement directly at the clamped settle node?
Figure 8 does this. Under these conditions, the sampling

11

scope

is heavily overdriven, but is ostensibly immune to
the insult. Figure 9 puts the sampling oscilloscope to the
test. Trace A is the time corrected input pulse and Trace B
the settle signal. Despite a brutal overdrive, the ‘scope
appears to respond cleanly, giving a very plausible settle
signal presentation.

SUMMARY OF RESULTS AND MEASUREMENT LIMITS

A = 2V/DIV

B = 10mV/DIV

HORIZ = 5ns/DIV

Figure 7. Expanded Vertical and Horizontal Scales Show
9ns Amplifier Settling within 5mV (Trace B). Trace A Is
Time Corrected Input Step

Note 7. When interpreting waveform placement note that trace B appears

time skewed relative to time corrected trace A. This accounts for trace B’s
falsely apparent movement before trace A’s ascent.

AN128 F07

AN128-6

The simplest way to summarize the different method’s
results is by visual comparison. Ideally, if both approaches
represent good measurement technique and are properly
constructed, results should be identical. If this is the case,
the data produced by the two methods has a high probability
of being valid. Examination of Figures 9 and 10 shows

Note 8. In this and all following photos, settling time is measured from
the onset of the time-corrected input pulse. Additionally, settling signal
amplitude is calibrated with respect to the amplifier, not the settle node.
This eliminates ambiguity due to the settle node’s resistance ratio.
Note 9. This section mentions amplifier frequency compensation within
the context of sampling-based settling time measurement. As such, it
is necessarily brief. Considerably more detail is available in Appendix B,
“Practical Considerations for Amplifier Compensation.”
Note 10. See Appendix C, “Evaluating Oscilloscope Overdrive
Performance” for in-depth discussion.
Note 11. Tektronix type 661 with 4S1 vertical and 5T3 timing plug-ins.

an128f

Application Note 128

nearly identical settling times and highly similar settling
waveform signatures. This kind of agreement provides a
high degree of credibility to the measured results.

Close observation of settling time circuit operation
indicates a noise floor/feedthrough imposed amplitude

FROM CURRENT
SWITCH DRIVER

FROM DIODE

BRIDGE CURRENT

SWITCH

ADJUST FOR 6.65ns DELAY COMPENSATION

1k

–5

SEE APPENDIX A

B

499

–

LT1818

+

1k

5pF

1k

1.5k

SETTLE

NODE

ZERO

B

1k

HSMS-2860

2s

+5

resolution limit of 2mV. The time resolution limit is about
2 nanoseconds to 5mV settling. For details, see the section
“Measurement Limits and Uncertainties”, in Appendix A,
“Measuring and Compensating Settling Circuit Delay and
Trimming Procedures.”

Y OFFSET

1k

+5 –5

–

LT1818

+

A1

50

10k

47

TO TEKTRONIX 661/4S1/5T3
SAMPLING SCOPE CHANNEL A

100X PROBE (TEKTRONIX P-6057)

VIA Z

0

TO CHANNEL B VIA 50 CABLE
DELAY MATCHED TO CHANNEL A

PROBE

Z

0

TO SAMPLE GATE

AN128 F08

Figure 8. Settling Time Test Circuit Modifications Using Classical Tektronix 661/4S1/5T3 1GHz Sampling Oscilloscope. Sampling
‘Scope’s Inherent Overload Immunity Permits Large Off-Screen Excursions without Degrading Measurement Fidelity

A = 2V/DIV

B = 10mV/DIV

HORIZ = 5ns/DIV

AN128 F09

Figure 9. Settling Time Measurement with Classical Sampling
‘Scope. Oscilloscope’s Overload Immunity Allows Accurate
Measurement Despite Extreme Overdrive. 9ns Settling Time and
Waveform Profile Are Consistent with Figure 7

REFERENCES

1. Williams, Jim, “1ppm Settling Time Measurement for
a Monolithic 18-Bit DAC,” Linear Technology Corpora­tion, Application Note 120, February 2010.

2. Williams, Jim, “30 Nanosecond Settling Time
Measurement for a Precision Wideband Amplifier,”
Linear Technology Corporation, Application Note 79,
September 1999.

A = 2V/DIV

B = 10mV/DIV

HORIZ = 5ns/DIV

AN128 F10

Figure 10. Settling Time Measurement Using Figure 5’s Circuit.
T

= 9ns. Results Correlate with Figure 9

SETTLE

3. Williams, Jim, “Component and Measurement Ad­vances Ensure 16-Bit DAC Settling Time,” Linear
Technology Corporation, Application Note 74, July

1998.

4. Williams, Jim, “Measuring 16-Bit Settling Times: The
Art of Timely Accuracy,” EDN, November 19, 1998.

5. Williams, Jim, “Methods for Measuring Op Amp Set­tling Time,” Linear Technology Corporation, Application
Note 10, July 1985.

an128f

AN128-7

Application Note 128

6. LT1818 Data Sheet, Linear Technology Corporation.

7. AD835 Data Sheet, Analog Devices, Inc.

8. Elbert, Mark, and Gilbert, Barrie, “Using the AD834 in
DC to 500MHz Applications: RMS-to-DC Conversion,
Voltage-Controlled Amplifiers, and Video Switches”,
p. 6-47. “The AD834 as a Video Switch”, “Applications
Reference Manual”, Analog Devices, Inc., 1993.

9. Kayabasi, Cezmi, “Settling Time Measurement Tech­niques Achieving High Precision at High Speeds,” MS
Thesis, Worcester Polytechnic Institute, 2005.

10. Demerow, R., “Settling Time of Operational Amplifiers,”
Analog Dialogue, Volume 4-1, Analog Devices, Inc.,

1970.

11. Pease, R.A., “The Subtleties of Settling Time,” The
New Lightning Empiricist, Teledyne Philbrick, June

1971.

12. Harvey, Barry, “Take the Guesswork Out of Settling
Time Measurements,” EDN, September 19, 1985.

13. Williams, Jim, “Settling Time Measurement Demands
Precise Test Circuitry,” EDN, November 15, 1984.

Technology Corporation, Application Note 122, January
2009, p.14-19.

22. Korn, G.A. and Korn, T.M., “Electronic Analog and
Hybrid Computers,” “Diode Switches,” p. 223-226.
McGraw-Hill, 1964.

23. Carlson, R., “A Versatile New DC-500MHz Oscilloscope
with High Sensitivity and Dual Channel Display,”
Hewlett-Packard Journal, Hewlett-Packard Company,
January 1960.

24. Tektronix, Inc. “Sampling Notes,” Tektronix, Inc.,

1964.

25. Tektronix, Inc. “Type 1S1 Sampling Plug-In Operating
and Service Manual,” Tektronix, Inc. 1965.

26. Mulvey, J. “Sampling Oscilloscope Circuits,” Tektronix,
Inc., Concept Series, 1970.

27. Addis, John, “Sampling Oscilloscopes,” Private Com­munication, February 1991.

28. Williams, Jim, “Bridge Circuits–Marrying Gain and
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