Noty an10f Linear Technology

Application Note 10

Methods of Measuring Op Amp Settling Time

Jim Williams

July 1985

Servo, DAC and data acquisition amplifiers all require
good dynamic response. In particular, the time required
for an amplifier to settle to final value after an input step
is especially important. This specification allows setting
a circuit’s timing margins with confidence that the data
produced is accurate. The settling time is the total length
of time from input step application until the amplifier re­mains within a specified error band around the final value.

Figure 1 shows one way to measure amplifier settling
time (see References 1, 2, and 3). The circuit uses the
“false sum node” technique. The resistors and amplifier
form a bridge-type network. Assuming ideal resistors, the
amplifier output will step to –V

when an input pulse is

IN

applied. During slew, the oscilloscope probe is bounded
by the diodes, limiting voltage excursion. When settling
occurs, the oscilloscope probe voltage should be zero. Note
that the resistor divider’s attenuation means the probe’s
output will be one-half of the actual settled voltage.

In theory, this circuit allows settling to be observed to
small amplitudes. In practice, it cannot be relied upon to
produce useful measurements. Several flaws exist. The
circuit requires the input pulse to have a flat top within
the required measurement limits. Typically, settling within

10mV or less for a 10V step is of interest. No general­purpose pulse generator is meant to hold output amplitude
and noise within these limits. Generator output-caused
aberration appearing at the oscilloscope probe will be
indistinguishable from amplifier output movement, pro­ducing unreliable results. The oscilloscope connection
presents additional problems. As probe capacitance rises,
AC loading of the resistor junction will influence observed
settling waveforms. The 20pF probe shown alleviates this
problem but its 10X attenuation sacrifices oscilloscope
gain. 1X probes are not suitable because of their excessive
input capacitance. An active 1X FET probe will work, but
another issue remains.

The clamp diodes at the probe point are intended to reduce
swing during amplifier slewing, preventing excessive oscil­loscope overdrive. Unfortunately, oscilloscope overdrive
recovery characteristics vary widely among different types
and are not usually specified. The diodes’ 600mV drop
means the oscilloscope may see an unacceptable overload,
bringing displayed results into question (for a discussion of
oscilloscope overdrive considerations, see Box SectionA,
“Evaluating Oscilloscope Overload Response”).

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.

SCOPE PROBE 20pF OR LESS

4.99k4.99k

1N4148

V

IN

4.99k

–15V 15V

Figure 1. Typical Settling Time Test Circuit

1N4148

4.99k

–

AUT

+

0.01

V

0.01

SCOPE VERTICAL 1mV/DIV

V

ERROR

OUT

SCOPE VERTICAL
INPUT REFERENCE

AN10 F01

=

VIN – V

OUT

2

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Application Note 10

Figure 2 shows a practical settling time test circuit that ad­dresses the problems discussed. Combined with a careful
evaluation of the test oscilloscope used, it permits reliable
settling time measurements in the 0.1% to 0.01% region.
The input pulse does not drive the amplifier, but switches
a Schottky bridge via a clamp. The bridge is biased from
two low noise LT1021-10V references. Depending on input
pulse polarity, current flows through the appropriate 10k
resistor to bias the amplifier’s summing point. The bridge
switches cleanly and quickly, producing a flat-topped
current pulse into the AUT. The circuit’s input pulse char­acteristics do not influence the measurement. A second
clamp-bridge arrangement supplies an opposite polarity
signal which is nulled against the amplifier’s output at
point B. Schottky clamp diodes limit this point’s voltage
excursion to ±300mV.

TTL

INPUT

PULSE

15V

50Ω

LT1021-10

IN

2k

GND

OUT

10k

1µF

+

C

(SELECT)

f

10k

A

–

The Q1-Q5 configuration forms a low input capacitance,
high speed buffer to drive the oscilloscope. Q1A’s 1pF
to 2pF input capacitance provides very light AC loading,
eliminating probe-caused problems. Q1B, running as a
current sink, compensates Q1A’s V

drop. Q2-Q5 form

GS

a complementary emitter-follower, which can drive sub­stantial cable capacitance without distortion.

The circuit should be built on a ground planed board with
particular care taken to ensure low stray capacitance at
points A and B. The AUT socket should be selected for short
pin lengths. Very high speed amplifiers (t

SETTLE

< 200ns)

should be directly soldered into the circuit.

USE GROUND PLANE
BYPASS SUPPLIES AT
AMPLIFIER UNDER TEST
AND OUTPUT STAGE.
MINIMIMZE STRAY
CAPACITANCE AT POINTS
A AND B

ALL HP5082-2810

NC

2k

LT1021-10

OUT

GND

10k

10k

10k

2k1µF

–15V

AUT

+

B

1k
NULL TRIM

9.76k

Figure 2. Improved Settling Time Test Circuit

Q1A

Q1B

–15V

1/2 U440

50Ω

1/2 U440

100Ω
ZERO

15V15V

–15V

15V

–15V –15V

15V

4.7k

Q2
2N5160

Q3
2N3866

4.7k

Q4
2N3866

3Ω

SETTLE
OUTPUT
(TO OSCILLOSCOPE)

3Ω

Q5
2N5160

AN10 F02

AN10-2

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Application Note 10

This circuit, combined with a judiciously chosen oscillo­scope, allows observation of amplifier settling to a millivolt
(0.01%) for a 10V step. A good way to gain confidence
in the circuit is to test a very fast UHF amplifier. Figure 3
shows response for an amplifier (Teledyne Philbrick 1435)
specified to settle in 70ns within a millivolt for a 10V step.
Trace A is the input pulse, Trace B is the amplifier output
and Trace C is the settle signal. Settling occurs inside
70ns, indicating good agreement between the circuit and
the AUT specification. Since most amplifiers are not nearly
this fast, it is reasonable to assume that the circuit will
always provide reliable results.

A = 5V/DIV

B = 5V/DIV

C = 5mV/DIV

Because this circuit works by nulling opposite polarity
sources, it seems unable to test followers—but it can.
The AUT is battery-powered and completely floated from
the circuit’s power supply (Figure 4). The AUT output is
connected to circuit ground and the battery center tap
becomes the output. The positive input is driven from
the Schottky bridge. The floating power supply lets the
follower fool the circuit into thinking it is testing an in­verter. The AUT’s output appears inverted, but this is not
a significant penalty.

20ns/DIV

Figure 3. Settling Detail for a Fast Amplifier

+V

–

AUT

+

15V

–

+

A = –1

NULL POINT

AN10 F04

TO OUTPUT
BUFFER

+

15V

–

–V

+V

–V

Figure 4. Circuit for Testing Followers

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