After Sales Technical Documentation
NHN–3N Series Transceivers
Chapter 1
Baseband Block
Original 42/96
NHN–3N
After Sales
Baseband Block
Technical Documentation
CONTENTS
Introduction 3 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Sub–modules 3 – 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation 3 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ratings ? where ?? 3 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics 3 – 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connections 3 – 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery/Service Connector 3 – 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charger Connector 3 – 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Audio Specifications ?? 3 – 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Description 3 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRLU 3 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRLU Internal Signals, Inputs 3 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRLU Internal Signals, Outputs 3 – 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block description 3 – 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RFTEMP, RF temperature measurement 3 – 13. . . . . . . . . . . . . . . . . . . . . .
Main components 3 – 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWRU 3 – 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block description 3 – 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MUUMI Block diagram 3 – 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUDIO 3 – 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction 3 – 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Main features 3 – 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical specifications 3 – 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NIPA Block Diagram 3 – 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit (TX) audio signal path 3 – 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UIF 3 – 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Original 42/96
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Technical Documentation
Introduction
The baseband submodule controls the internal operation of the phone. It
controls the user interface, i.e. LCD driver, keyboard, and audio interface
functions. The module performs all signalling towards the system, and
carries out audio–frequency signal processing. In addition, it controls the
operation of the transceiver and stores tuning data for the phone.
All functional blocks of the baseband are mounted on a single multi layer
printed circuit board. This board also contains RF–parts. The chassis of
the radio unit contains separating walls for baseband and RF. All components of the baseband are surface mountable. They are reflow soldered .
The connections to the Display–module are fed through a flex to the
board connector.
The Baseband Module includes power supply, modem, audio filters, micro–controller, nonvolatile memory, SIS–processor, and keyboard. The
display is a separate module. Power supply circuits like regulators, voltage detection and charging control, are integrated to the custom MUUMI
circuit . The modem and audio operations are integrated into NIPA ASIC.
The micro–controller is a Hitachi H8 series controller with 64 kbytes ROM
and 2 kbytes RAM. The 2 kbytes EEPROM memory is of serial I
type. The SIS–processor is a Motorola MC68HC11A8 connected to the
controller over serial bus I2C.
Baseband Block
2
C–bus
List of Sub–modules
Name of submodule Notes
CTRLU
PWRU
AUDIO
UIF
RECEIVER
TRANSMITTER
SYNTHESIZER
These blocks are only functional blocks and therefore have no type nor
material codes.
Control Unit for the phone
Power supply
Audio
User interface
Receiver
Transmitter
Synthesizer
Original 42/96
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NHN–3N
After Sales
Baseband Block
Modes of Operation
The module has three operating modes: stand–by, listening, and conversation mode.
Standby mode:
CPU‘s clock is switched off, only NIPA timer is running to take care of battery save timings.
If charger is connected CPU doesn‘t go to standby mode.
Listening mode:
In the listening mode, some blocks of the audio IC (NIPA) are in standby
state.
Conversation mode:
Technical Documentation
In the conversation mode all ICs are active.
DC Characteristics
Line Symbol Minimum Typical /
Nominal
VCS
VCS
VBA T 4.5V 4.8V 6.8V
VRF 4.5V 4.8V 6.8V VBAT for RF module
VA 3.1V 3.3V 3.5V Imax = 20mA
VL 3.1V 3.3V 3.5V Imax = 0.5mA
VL2 3.1V 3.3V 3.5V Imax = 40mA
VL3 3.6V 3.9V 4.3V Imax = 20mA
VREF 3.2V 3.3V 3.42V Imax = 5mA
9.5V 10.5V 10.5V LCH–6; ACH–6
740mA
10.5V 12.0V 16.5V ACH–8
265mA
Maximum Unit / Notes
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Technical Documentation
Connections
Battery/Service Connector
Baseband Block
Pin Line
Symbol
1 VBAT 4.2V 4.8V 6.8V Battery voltage for transceiver.
2 MBUS Mbus line
3 XEAR External earphone
4 XMIC External microphone
5 GND Power supply ground.
Minimum
Typical
/ Nomi-
nal
Maxi-
mum
Minimum Typical /
Nominal
Maximum
Original 42/96
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After Sales
Baseband Block
Charger Connector
Technical Documentation
Pin Line
Symbol
2 VCS
3 GND Power Supply Ground
4 TERMI-
NAL
Minimum
9.5V 10.5V 10.5V LCH–6 and ACH–6
10.5V 12.0V 16.5V ACH–8
Typical
/ Nomi-
nal
740mA
265mA
Maxi-
mum
Unit / Notes
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Technical Documentation
Audio Specifications
Minimum Typical /
Nominal
Minimum Typical /
Nominal
MIC (NIPA’s input pin) 2,5 mV
EARP, EARM 35 mV
XEAR 170mV
XMIC 260mV
rms
rms
rms
rms
Baseband Block
Maximum Unit / Notes
Maximum Unit / Notes
30 mV
rms
3.0 V
rms
2600mV
rms
Mic amplifier input
(NIPA’s input pin)
Earphone amplifier
output
Via Battery / Service
Connector
Via Battery / Service
Connector
Original 42/96
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After Sales
Baseband Block
Technical Documentation
Circuit Description
CTRLU
The Control block controls all phone functions, and SIS–processor too.
CTRLU Internal Signals, Inputs
Signal Name Notes From
VL2 Logic supply voltage Max 40 mA PWRU
VL3 SIS processor supply voltage PWRU
VREF Reference voltage 3.3V 2%. Max. 5mA. PWRU
PWRON Signal from power button. PWRU
XRES Reset line from MUUMI PWRU
VCHARG Charger voltage to A/D converter PWRU
VBATSW Battery voltage to A/D converter. PWRU
BTEMP Battery temperature CTRLU
RFTEMP RF temperature SYNTHESIZER
RSSI Received signal strength indication RECEIVER
TXI Transmitter output power level indication TRANSMITTER
RXD Serial interface (M2BUS) PWRU
XINT Interrupt request from NIPA AUDIO
NMI No maskable Interrupt request from NIPA AUDIO
CLKMCU Clock for controller AUDIO
CTRLU Internal Signals, Outputs
Signal Name Notes To
TXD Serial interface (M2BUS) PWRU
CSW Charger control PWRU
AGC Gain control RECEIVER
RXE RX Circuit power on/off RECEIVER
SCLK Synchronous data clock for synthesizers SYNTHESIZER
SDAT Synchronous data for synthesizers SYNTHESIZER
SLE Synthesizer data latch enable SYNTHESIZER
TXE Transmitter control (on/off) TRANSMITTER
TXC Transmitter Power Control TRANSMITTER
TXS TX synthesizer enable SYNTHESIZER
EAREN Earphone enable AUDIO
XNCS NIPA chip select signal AUDIO
XNWR NIPA write control signal AUDIO
XNRD NIPA read control signal AUDIO
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Technical Documentation
NA(3:0) NIPA address bus AUDIO
ND(7:0) NIPA data bus AUDIO
LIGHTS Backlights on/off UIF
COL0/
XPWROFF
COL1–4 Lines for keyboard read (keypad outputs) UIF
ROW0–2 Lines for keyboard read (keypad inputs). Input pull–up used UIF
LCDD0–3 Lcd driver data UIF
E Lcd driver chip select signal UIF
RW Lcd driver read/write select signal UIF
RS Lcd driver register select signal UIF
LCDRES Lcd driver reset signal UIF
Line for keyboard read/
Power off control
Baseband Block
UIF
ToNotesSignal Name
Block description
CTRLU – PWRU
CTRLU controls the watchdog timer in MUUMI. It sends a positive pulse
at approximately 1 s intervals to the XPWROFF pin of MUUMI to keep the
power on. If CTRLU fails to deliver this pulse, the MUUMI will cut off power from the system. CTRLU also controls the charger on/off switching in
the PWRU block. When power off is requested, CTRLU leaves the
MUUMI watchdog without reset. After the watchdog has elapsed, MUUMI
cuts off the supply voltages from the phone. Battery charging is controlled
by CSW line, which is a PWM–controlled output port (frequency about 11
Hz).
VBATSW, Battery voltage measurement
The battery voltage can be measured up to 9.075 V nominal with 3.3 V
reference voltage. The absolute accuracy is low because of the reference
3 % accuracy, and A/D–converter +/– 8 LSB accuracy . This battery voltage measurement offset error must be calibrated with input voltage 4.8 V.
The A/D conversion result can be calculated from the equation:
A/D readout = 1024 * (VBATSW* ( 4/11)) / VREF VREF=3.3V
Original 42/96
For example:
6.9 V results 778 = 30AH
4.8 V results 542 = 21EH
4.0 V results 451 = 1C3H
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Baseband Block
VCHARG, Charger voltage measurement
The charger voltage can be measured up to 21.6 V nominal. The
A/D–conversion result can be calculated from the equation :
BTEMP , Battery temperature measurement
Battery temperature measurement is implemented with 15 kohm NTC
and 47 kohm pull–up resistor. The A/D conversion readout can be calculated from the equation:
Technical Documentation
A/D readout = 1024 * (VCSW*(18/118)) / VREF VREF=3.3 V
For example:
11 V gives 520 = 208H
10 V gives 473 = 1D9H
4.8 V gives 227 = 0E3H
A/D readout= 1024* ( R
NTC
/( R
NTC
+47k))
For example:
CTRLU – AUDIO
The interface between micro–controller and NIPA circuit is a bi–directional
8–bit data bus with 4 address lines. Address, data, and control lines are
used in micro–controller as I/O–port pins. Data line direction must be controlled with the micro–controller data direction register. The Interface includes address outputs NA0–3, data inputs (read) / outputs (write)
ND0–7, chip select control output XNCS, read control output XNRD, write
control output XNWR, and interrupt inputs XINT and NMI. To minimize
power consumption in battery stand by mode, control signals XRD and
XCS should be in ’0’ state, address output NA0–3 and NWR in ’1’ state,
and data lines ND0–7 should be inputs .
CTRLU – UIF
The keyboard is connected directly to the controller. COL0–4 are output
lines and ROW0–2 are input lines. The watchdog is updated at the same
time as keyboard scanning (XPWROFF). Keyboard scanning is done by
driving one COL to 0 V at time, and ROWs are used to read which key is
pressed.
The keyboard and LCD lights are controlled by the LIGHTS signal.
+25°C gives 247 = 0F7H ( About 0.8 V )
The LCD controller interface to the micro–controller are 4 bi–directional
data lines DD0–3, register select control RS output, read/write control RW
output, and bus enable control E output. The data lines LCDD0–3 and
control signals RS, RW must be set to high state during standby operation because of the pull–up resistors in the LCD controller. LCD controller
resetting requires clock signal during XRES active low which is controlled
by LCDRES line. The MCU disables LCDRES after it has set LCDCLK
frequency to 57.6 kHz.
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CTRLU – RECEIVER
The RECEIVER circuit power is connected on/off by the RXE signal.
Received signal strength is measured over the RSSI line, and the inter-
mediate frequency is measured over the IF line.
CTRLU – SYNT
The frequency is controlled by the AFC signal. The synthesizer is controlled via the synchronous serial bus SDAT/SCLK. The data is latched to
the synthesizer by the positive edge of the SLE line. The TX synthesizer
power on/off (TXS) line is controlled via PLL circuit. Control information is
programmed by using the SDAT line.
RFTEMP, RF temperature measurement
RF temperature measurement is implemented with 15 kohm NTC and
47 kohm pull–up resistor. The A/D conversion readout can be calculated
from the equation:
A/D readout= 1024* ( R
NTC
Baseband Block
/( R
NTC
+47k))
For example:
25 C gives 247 = 0F7H ( about 0.8 V )
CTRLU – TRANSMITTER
The transmitter output power level is measured over the TXI line. The
TXE line activates the power module. The power is controlled via the TXC
line which is a PWM–controlled output port (frequency about 5.1 kHz).
Main components
H8/3032 is a CMOS micro–controller. All memory needed (64kB ROM,
2kB RAM) except the EEPROM, is located in the controller. The MCU operating clock (3.6864 MHz) is generated on NIPA. H8/3032 is operating in
single–chip normal mode (mode 2) 64 kbyte address space, so all input/
output pins are used as I/O–ports.
Pin Number Port Signal Description
1 PB0 SDAT
2 PB1
3 PB2
4 PB3 RXD
Serial data for synthesizer
M2BUS net free timer input
5 PB4 EAREN
6 PB5 LCDRES
7 PB6 PWRON
8 PB7 SLE
Original 42/96
Earphone enable
Reset for Lcd driver
Power button state
RX/TX synthesizer latch
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Baseband Block
9 P90 TXD
10 P92 RXD
11 P94 ECLK
12 VSS GND
13 – 20 P30 – P37 ND0 – ND7
21 VCC VL2
22 P10 NA0
23 P11 NA1
24 P12 NA2
25 P13 NA3
26 P14 XNCS
27 P15 XNWR
Technical Documentation
DescriptionSignalPortPin Number
Serial interface (M2BUS)
Serial interface (M2BUS)
Serial clock for EEPROM
Parallel data bus for NIPA
Address line for NIPA
Address line for NIPA
Address line for NIPA
Address line for NIPA
NIPA chip select
Read/write control to NIPA
28 P16 XNRD
29 P17 LIGHTS
30 VSS GND
31 – 34 P20 – P23 LCDD0 – LCDD3
35 – 37 P24 – P26 ROW0 – ROW2
38 P27 COL4
39 P50 COL0/XPWROFF
40 – 42 P51 – P53 COL1 – COL3
43 P60 TXS
44 – 45 MD0 – MD1
46
47 STBY
48 RES XRES
NC
Read/write control to NIPA
Backlight control
Lcd driver data
Keypad inputs (Input pull–up
used)
Keypad output
Keypad output /
Watchdog control
(XPWROFF)
Keypad outputs
TX synthesizer enable. Ac-
tive high
Mode selection
Reset from MUUMI
49 NMI NMI
50 VSS GND
51 EXTAL CLKMCU
52 XTAL
53 VCC VL2
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Interrupt request from
NIPA
External system clock from
NIPA
Original 42/96
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NHN–3N
Technical Documentation
54 P63 TXE
55 P64 AGC
56 P65 RXE
57 RESO
58 AVSS GND
59 P70 VBATSW
60 P71 VCHARG
61 P72 RSSI
62 P73 TXI
63 P74 BTEMP
64 P75
65 P76 RFTEMP
Baseband Block
DescriptionSignalPortPin Number
Transmitter on/off
Receiver gain control
RX circuit power on/off
Battery voltage
Charger voltage
Received signal strength
Transmitter power monitor
Battery temperature
RF temperature
66 P77 CALLCNT
67 VREF VREF
68 AVCC VREF
69 P80 XINT
70 P81 RS
71 P82 RW
72 P83 E
73 PA0 SISCLK
74 PA1 SISD
75 PA2 EDATA
76 PA3 SCLK
77 PA4 CSW
78 PA5
Call continue during battery change
Interrupt request from
NIPA
Lcd driver register select
Lcd driver read/write
Lcd driver chip select
Serial clock for SIS–pro-
cessor
Serial data for SIS–proces-
sor
Serial data to/from EE-
PROM
Serial clock for synthesizer
Charging control
79 PA6 TXC
80 PA7
Original 42/96
Transmitter power control
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Baseband Block
MC68HC11A8
MC68HC11A8 is a SIS (subscriber identification) circuit connected to the
controller over serial bus I2C.
SIS–processor signals
Pin No Signal From
31 EXTAL Clock input from the NIPA
43 RESET Reset input
47 PD0
50 PD1
EEPROM
I2C bus clock
I2C bus data
There is one 2k EEPROM in the phone. EEPROM is a nonvolatile
memory into which the tuning data for the phone is stored. In addition, it
contains the short code memory locations to retain user selectable phone
numbers.
Technical Documentation
EEPROM signals
Pin No Signal Description
5 SDA
6 SCL
I2C bus data
I2C bus clock
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Technical Documentation
Baseband Block
PWRU
The power block provides the supply voltages for the baseband, and also
includes the charging electronics.
PWRU Internal Signals, Inputs
Signal Name Notes From
VBAT Battery voltage input CONNECTOR
XPWRON Power on control from keyboard UIF
XPWROFF Power off control from controller (watch dog) CTRLU
VCS Charging supply voltage from charger CONNECTOR
CSW Charger control CTRLU
TXD Serial interface (M2BUS) CTRLU
M2BUS Serial interface CONNECTOR
PWRU Internal Signals, Outputs
Signal Name Signal description To
VL Logic supply voltage. Max 0.5 mA. AUDIO
VA Analog supply voltage. Max 20 mA. AUDIO
VL2 MCU supply voltage CTRLU, UIF
VL3 SIS processor supply voltage CTRLU
VREF Reference voltage 3.3V 2%. Max. 5mA. CTRLU,
RECEIVER,
TRANSMITTER
XRES Master reset CTRLU, AUDIO
VBATSW Battery voltage to A/D converter. CTRLU
VCHARG Charger voltage to A/D converter CTRLU
RXD Serial interface (M2BUS) CTRLU
PWRON Power button indicator, PWRON is same as XPWRON but
buffered and inverted.
CTRLU
Block description
The baseband power supplying circuit MUUMI includes:
– the supply voltages:
VL 0.5mA for NIPAs digital circuits
VL2 40mA for digital circuits
VL3 20mA for SIS–processor
VA 20mA for analog circuits
VREF 5mA reference voltage for A/D–converters and
regulators
– switched output of battery (VBATSW) and charger voltage (VCHARG)
measurements to MCU A/D–converter
Original 42/96
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Baseband Block
– battery voltage detection and reset logic
– charger switch control output used to limit battery voltage VBAT < 6.8V
– power on/off switch input (XPWRON), buffered output to MCU
(PWRON)
– watchdog timer using oscillator in COFF pin , cleared by falling edge
input in PWROFFX, elapsing time for watchdog timer is 3 ... 4 seconds
– M2BUS open drain output driver.
The charge switch driving circuit is implemented with discrete compo-
nents. This circuit includes transient voltage protection, soft charge
switching, low voltage battery charging, and battery disconnecting with
charger connected protection. This circuit also limits the battery voltage
when charger is connected to protect MUUMI and TX transistors.
The power circuits have three different operating modes: POWER OFF,
RESET, and POWER ON. In POWER OFF state, MUUMI regulator outputs are disabled, and the reset control output signal (PURX) is active
low. The MUUMI internal oscillator at pin COFF is working in all operating
modes. MUUMI goes through a short RESET state (100ms ) to POWER
ON–state if the PWR–button is pressed, or a charger voltage input is connected to the charging input VCS (charging voltage detection in MUUMI
input VCHAR is level active). In RESET–state, the regulator outputs
VL,VA and VREF are active, and the PURX–signal is active low. If the battery voltage VBAT is lower than 4.1V (3.9V...4.3V), the circuit cannot go to
POWER ON state. MUUMI also goes to RESET state when the battery
voltage falls below 3.9 V (3.7V...4.1V). This situation is possible when the
battery is fully discharged, or disconnected.
Technical Documentation
In POWER ON mode, all regulator outputs are active, and the MUUMI reset signal output PURX is inactive high. The micro–controller XPWROFF–
output signal clears at the falling edge of the watchdog inside MUUMI. If
the watchdog is not cleared, MUUMI goes to POWER OFF state. When
the charger is connected and battery voltage is higher than 4.1V, the
module stays in POWER ON mode.
The micro–controller controls battery charging with CSW output (which is
a PWM–controlled output port), and MUUMI limits the maximum battery
voltage to 6.8 V with CHRGSW–output.
No current flows from charger (VCHARG) to battery if the MCU output
CSW is active low, and the XRES signal is inactive high. The battery is
also charged when a charger is connected and the XRES signal is active
low. The charging circuit charges the battery during RESET to higher
than 4.3 V.
The charging electronics is controlled by CTRLU. When the charging voltage is applied to the phone while the phone is powered up, the CTRLU
detects it and starts tp control the charging.
If the phone is in power–off state, the MUUMI will detect the charging voltage. If the battery voltage is high enough, the reset will be released and
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Technical Documentation
the CTRLU will start controlling the charging. If the battery voltage is too
low, the phone is in reset, and charging control circuitry will pass the
charging current to the battery. When the battery voltage has reached
4.1V (3.9...4.3V), the reset will be removed, and the CTRLU starts controlling the charging. This all is invisible to the user.
V116 is the charging switch. It is governed by the controller (CSW line) via
voltage regulator V114 and V115. In fast charge mode, CSW is ”1” and in
maintain charge mode, there are controller controlled pulses. In charge
off state, CSW is ”0”. In maintain charge mode, the pulse ratio depends
on the charger and temperature.
There are three different ways to switch power on:
– Pressing power–key grounds the XPWRON line. The MUUMI detects
that, and switches the power on.
– Charger detection on MUUMI detects that a charger is connected, and
switches the power on.
– MUUMI will switch power on when the battery is connected. If the bat-
tery is changed during the call, the power is kept on. If not, the power
is switched off.
Baseband Block
Original 42/96
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Baseband Block
MUUMI Block diagram
VBAT1
1
VBAT2
22
VBAT3
5
M2BUSIN
11
760k
PWM
15
760k
CHARGER
CTRL
LOGIC
BANDGAP
REF
Technical Documentation
70k
40k
VBATSW
M2BUSOUT
VREF
17
12
VL
23
VA
2
4
21
13
14
3
VCHAR
PWRONX
PWROFFX
TEST
VBAT
32k
760k
760k
LOW VBAT
& CHARGER
DETECT
PWR ON/OFF
&
RESET LOGIC
Creset
20
16
Coff
VL_ENA
VA_ENA
VREF_ENA
VSW_ENA
VCHAR
GND1
24
GND2
19
GND3
7
CHRGSW
PWRONXBUFF
VCHARSW
Cref
6
PURX
8
10
9
18
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Technical Documentation
AUDIO
Introduction
The block includes NIPA audio/signalling processor in a 64 TQFP package for NMT450 and NMT900 systems.
Main features
– Single chip FFSK modem and audio circuit
– Full duplex 1200 baud signalling
– DMS facility
– Low power consumption modes
– Programmable output clocks with clock stop for MCU and LCD
– 8 bit parallel interface with pull ups
– FSK indicator and level detector
– Speech volume indicator
– Programmable timer
– IF counter
– 8 bit DAC
– FII filter and gain control
– Low noise microphone amplifier
– Input for a handset microphone or an accessory
– Microphone sensitivity compensation +4.8/–4.2 dB range (4 bits)
– Compander
– RX and TX filters
– Tx hard limiter
– Tx AGC
– Internal reference compensation +1.00/–0.75 dB range(3 bits)
– Summing stage for voice/data, signalling and fii
– Transmitter compensation amplifier with +3.75/–3.75 dB range (4 bits)
– Receiver compensation amplifier with +3.75/–3.75 dB range (4 bits)
– Volume control amplifier with –20/+17.5 range (4 bits)
– Earphone amplifier with drive capability for ceramic earpiece
– Buffered output for a handset or an accessory
– Mute switches
– Dual and single tone multi–frequency generator
– Driver for buzzer amplifier
– Hands free functions
Baseband Block
Original 42/96
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NHN–3N
After Sales
Baseband Block
Technical Documentation
Technical specifications
AUDIO Internal Signals, Inputs
Signal Name Notes From
XRES Reset line from MUUMI PWRU
XNCS Chip select signal CTRLU
XNWR W rite control signal CTRLU
XNRD Read control signal CTRLU
NA0...3 4–bit address bus CTRLU
ND0...7 8–bit bi–directional data bus CTRLU
EAREN Earphone enable CTRLU
MBUSINT M2BUS interrupt request PWRU
KBINT Keyboard interrupt request UIF
IF (2nd) Intermediate frequency for AFC function RECEIVER
DAF Detected audio signal from receiver RECEIVER
XMIC External audio input from service accessories CONNECTOR
VBAT Battery voltage CONNECTOR
VL Logic supply voltage Max 0.5 mA. PWRU
VA Analog supply voltage Max 20 mA. PWRU
AUDIO Internal Signals, Outputs
Signal Name Notes To
XINT Interrupt request to MCU CTRLU
NMI No maskable Interrupt request to MCU CTRLU
LCDCLK Clock signal for LCD driver ( 57.6 kHz) UIF
CLKMCU Clock signal for MCU (3.6864 MHz) CTRLU
XEAR External audio output to service accessories CONNECTOR
MOD Audio output to synthesizer SYNTHESIZER
AFC VCTCXO control SYNTHESIZER
NIPA Pin list
Pin no Symbol Pin type Notes
1 VDD1 + 3.3 V Supply voltage, digital
2 XRD DIN/pd Read control signal, active state LOW, pull–down > 50
k
3 XCS DIN/pd Chip select signal, active state LOW, pull–down > 50
k
4 A3 DIN/pu 4–bit address bus, MSB, pull–up > 50 k
5 A2 DIN/pu 4–bit address bus, pull–up > 50 k
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Technical Documentation
NotesPin typeSymbolPin no
6 A1 DIN/pu 4–bit address bus, pull–up > 50 k
7 A0 DIN/pu 4–bit address bus, LSB, pull–up > 50 k
8 D7 DIO 8–bit bi–directional data bus MSB
9 D6 DIO 8–bit bi–directional data bus
10 D5 DIO 8–bit bi–directional data bus
11 D4 DIO 8–bit bi–directional data bus
12 D3 DIO 8–bit bi–directional data bus
13 D2 DIO 8–bit bi–directional data bus
14 D1 DIO 8–bit bi–directional data bus
15 D0 DIO 8–bit bi–directional data bus LSB
16 VDD2 + 3.3 V Supply voltage, digital
17 NMI DOUT Non maskable Interrupt request
18 XCLR DIN HW reset input, active state LOW
Baseband Block
19 TMODE DIN/pd Test mode selection, pull–down > 50 k
20 TSEL DIN/pd Test select, pull–down > 50 k
21 XINT DOUT Interrupt request to MCU, active state LOW
22 MBUSINT DIN MBUS interrupt request, falling edge active
23 KBINT DIN Keyboard interrupt request, falling edge active
24 IF AIN IF input
25 VSS2 0 V Supply voltage, digital ground
26 VSA2 0 V Supply voltage, analog ground
27 DAF AIN Signal input
28 FILO AOUT RX–filter output
29 EXPI AIN Expander input
30 EAMPBO AOUT Expander Amplifier B output
31 EWCI AIN Expander Window Comparator input
32 EXPO AOUT Expander output
33 VDA2 + 3.3 V Supply voltage, analog
34 VOLI AIN Volume control ampl. input (Volume)
35 EXTEAR AOUT Buffered output for handset or an accessory
36 EVGND AIN Earphone driver virtual ground
37 EARM AOUT Earphone driver output
38 EARP AOUT Earphone driver output
39 CWCI AIN Compressor window comparator input
40 DACO AOUT DA converter output
41 SIDEAR AOUT Sidetone output
42 REF AIN Internal analog signal ground 1.65 V
Original 42/96
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NHN–3N
After Sales
Baseband Block
NotesPin typeSymbolPin no
43 MIC AIN Microphone amplifier input
44 BIMIC AOUT Microphone bias current output
45 CMIC AIN Microphone current stabilization capacitor
46 EXTMIC AIN Audio input for a handset or an accessory
47 TXBPO AOUT Transmit bandpass filter output
48 VDA1 + 3.3 V Supply voltage, analog
49 COMI AIN Compressor input
50 COMO AOUT Compressor output
51 EMPI AIN Pre emphasis input
52 FIIOUT AOUT Received FII signal
53 TOUT DOUT Test output, digital
54 ATST AOUT Audio Filter Test output
55 MOD AOUT Transmit path output
Technical Documentation
56 VSA1 0 V Supply voltage, analog ground
57 VSS1 0 V Supply voltage, digital ground
58 BUZZ DOUT Buzzer output
59 ATOUT AOUT Test pin
60 CLKOUT COUT 7.3728 MHz (3.6864 MHz) crystal oscillator output
61 CLKIN CIN 7.3728 MHz (3.6864 MHz) crystal oscillator input or
input for the external clock
62 CLKLCD DOUT Clock signal for LCD, 230.4 kHz or 57.6 kHz
63 CLKMCU DOUT Clock signal for MCU, 3.6864 MHz or 7.3728 MHz
64 XWR DIN/pu Write control signal, active state LOW, pull–up > 50
k
Page 1 – 22
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R
NHN–3N
Technical Documentation
NIPA Block Diagram
ATST
ATOUT
LIM
VOL
AGC
SUM
TXTRI
TXAAF
PREEMP
EMPI
CWCI
COMI COMO
TXBPO
RXAAF
SINGEN
MODTRFIL
MODRXFIL
DATACOMP
TXLP TXTRI+TXPOSTFIL
AGC
PREEM LIM
COMPR
txbpo
aloop (to RXMUX)
(to SIDEAR)
SINGEN MODTRFIL
FSKMOD
TRSTBY
RFLAG
TFLAG
RECCTRL
WTRFIL
TRREG
TR
CTRL
STATUS
RECREG
DPLL
INTERNAL
CLOCKS
WPOSFIL
SUM
BITS
MOD
BUZZ
BUZZ
ddtmf
SMUX
DFLAG
AFC
loop (to MODRXFIL)
MODTRPOST
XBSSBY
XTALKSBY
XBUZZSBY
XIFSBY
XDTMFSBY
DRIV
CONTROL BITS
CREG
TIMER
DETFIL
DETED
DACO
D/A
8 bit
XDACSBY
INTERFACE
FIIBUF
A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7
NMI
XINT
XWR
XRD
XCS
FIIOUT
EAR
FIIPOST
EARP
HF
Baseband Block
SIDEAR
EARM
CONTR
EVGND
RXATT ACC
EXP VOL
DEEMP+RXFIL
EXTEAR
SIDEA
txbpo
(from TXBP)
64 pins
VOLI
EXPO
EWCI
EAMPBO
EXPI
FILO
TXMUX+TXAAF TXATT MICTRI TXBP
MICAM
MIC
BIMIC
Original 42/96
ddtmf (to BUZZDRIV)
DTMFCOMP
DTMF GEN
CMIC
EXTMIC
CLKLCD CLKMCU
XCLR
dtmf
(to RXMUX)
REF GEN
TSEL
TMODE
CLKIN
CLOCKDIV
OSC
CLKOUT
IFAMP
IFCNTR
IF
FSKDIS
FSKIND
GND GEN
REF
DATACOMP
MODRXFIL
KBINT
MBUSINT
FSKLEV
VDD1
FIIFIL(4kHz)+FIITRI
LEVEL
loop (from WPOSFIL)
VSS2
VDA1
VDD2
VSA1
dtmf
VDA2
RXMUX+AAFIL
VSA2
VSS1
aloop (from TXPOSTFIL)
RXTRI RXAAF
DAF
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NHN–3N
After Sales
Baseband Block
Transmit (TX) audio signal path
The TX audio signal is processed in the NIPA circuit and fed via the MOD
line to the TX synthesizer on SYNTHESIZER module.
NIPA ASIC contains the following stages for TX signal processing:
MICAM:
The signal from the microphone is fed to this stage and amplified up to
200 mVrms.
TXMUX + TXAAF:
TX source selection (exmic/mic/dmmf/muted). Txaafil prevents aliasing in
TXBP filter.
TXATT:
TXATT is a hands free attenuator. Maximum attenuation is selectable
from four levels: –30, –27, –24 or –21 dB.
MICTRI:
Technical Documentation
MICTRI is for different microphone (phone microphone, headset and
handset etc.) sensitivity compensation. It is used also for dtmf level setting. Gain 16 levels, step 0.6 dB.
BANDPASS:
Tx bandpass filter takes out high freq noise and low freq hum.
COMPR:
It compresses speech dynamic area to avoid noise at tx and radio path. It
is an amplitude compressor and ratio is 2:1 in dB scale. It can be bypassed for measurement or dtmf purposes.
PREEMP:
Pre–emphasis filter gives +6 dB/oct emphasis.
AGC:
A soft limiter is needed in order to suppress inter–modulation. Signal
measuring circuitry measures peak–to–peak voltage. If the signal on soft
limiter input is not a sine signal (clipped in preceding stages), peak–to–
peak signal level is increased in the post limiter filter.
LIM:
Hard limiter. It cuts the signal transients to 1131 mVpp levels.
TXLP:
The corner frequency of tx lowpass filter is 3400 Hz. Amplitude attenua-
tion is 12 dB/oct after the corner point. Filter includes notch at 4 kHz.
TXTRI:
TXTRI is for nominal deviation tuning. Gain 8 levels, step 0.5 dB.
TXPOSTFIL:
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NHN–3N
Technical Documentation
Postfil eliminates filter clock.
SUM:
Speech, data and FII signals are summed together.
WTRFIL:
This block is a lowpass filter for FII and data. Transmitter Compensation
Amplifier is these too. Gain 16 levels, step 0.5 dB.
WPOSFIL:
WPOSFIL filters out the replicates of the output spectrum around WTRFIL
clock frequency and its harmonics.
RECEIVE (RX) AUDIO SIGNAL PATH
Baseband Block
NIPA contains the following stages for RX signal processing:
RXTRI:
RXTRI is for demodulation sensitivity compensation. Gain 16 levels, step
0.5 dB.
RXAAF:
RX aafilter filters out noise and other high frequency components from
the incoming signal. It prevents aliasing in FIIFIL, RXFIL and MODRXFIL.
RXMUX+AAFIL:
Rxmux selects speech from DAF–pin or DTMF from generator or a loop
from TXTRI or mute. Aafil prevents aliasing in RXFIL.
DEEMP+ RXFIL:
Rx filter filters out high freq noise and low freq hum. It has de–emphasis
–6 dB/oct for the received speech signal. Design should include notch at
4kHz.
EXP:
It expands speech dynamic back to normal. It is an amplitude expander
and ratio is 1:2 in dB scale. It can be by–passed for measurement or dtmf
purposes.
VOL:
VOL is for earphone or accessory speaker/earphone volume control. Vol-
ume Control Amplifier. Gain 16 levels over –20 to +17.5 dB in 2.5 dB
steps.
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NHN–3N
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Baseband Block
RXATT:
RXATT is a hands free attenuator. Maximum attenuation is selectable
from four levels: –30, –27, –24 or –21 dB.
Hands free controller (HF CONTR) measures peak–to–peak level of the
received audio and controls gains of the transmit and receive attenuators
as a function of measured signal level.
EAR:
The Earphone Amplifier is a single input, differential output amplifier for a
ceramic earpiece.
ACC:
Buffer for accessory line is capable of driving high capacitive load. Gain
and response of the buffer are fixed.
Transmitting data path
The data to be transmitted will be loaded into the transmitting register
TRREG. From the TRREG register the 8 bit data is transformed to serial data
which is sent to the FSK modulator (FSKMOD) and sine wave generator
(SINGEN) and then to the summing block (SUM).
Technical Documentation
Receiving data path
The data from anti alias filter is connected through the modems RX filter
(MODRXFIL) to the data comparator (DA TACOMP) and then to FSK discriminator. Further from FSK discriminator data is connected to detecting filter
(DETFIL) and from there to digital phase locked loop (DPLL).
IF
Intermediate frequency counter (IFCTR) is on the modem to measure
the frequency of IF signal.
AFC
AFC provides the synthesizer fine tuning. It can also be used for channel
sidestep.
AFC DA–converter output DC level tunes RF oscillator (VCXO).
FII path
The FII signal is filtered and amplified with a 4 kHz bandpass filter (FIIFIL). FIITRI is for FII sensitivity compensation. The filtered FII is then fed to
the summing block (SUM).
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After Sales
NHN–3N
Technical Documentation
Buzzer driver
The buzzer driver is a ’semi PWM’ signal generator. It detects rising edges
of DTMF signal and generates a pulse on every rising edge. The length of
the pulse can be set by writing a length control word to the register BUZZVOL. The length is N * 2.17 us, where N is a value in BUZZVOL register.
V alue 0x0H in BUZZVOL register disables buzzer driver i.e. BUZZ output is
always low.
The buzzer uses three volume levels, which are controlled by the PWM
signal.
Clock divider
The clock divider generates internal clock frequencies by dividing the
master clock frequency which is created by an internal crystal oscillator
and an external 7.3728 MHz or 3.6864 MHz crystal. An external clock signal can also be used. If the crystal is used, the oscillator output CLKOUT
must not be loaded. A buffered crystal frequency can be obtained at pin
CLKMCU directly or divided by two. A 230.4kHz / 57.6kHz clock can be
obtained at pin CLKLCD. The frequency can be selected with control bit
SELLCDC.
Baseband Block
NHN–3N uses a 3.6864 MHz clock for the MCU (CLKMCU), and a
57.6 kHz clock for the LCD display (CLKLCD).
UIF
The UIF module includes keyboard, keyboard illumination and display.
UIF internal Signals, Inputs
Signal Name Notes From
LIGHTS Backlights on/off CTRLU
COL0–4 Lines for keyboard read (keypad outputs) CTRLU
DD0–3 Lcd driver data CTRLU
E Lcd driver chip select signal CTRLU
RW Lcd driver read/write select signal CTRLU
RS Lcd driver register select signal CTRLU
LCDRES Lcd driver reset signal CTRLU
UIF internal Signals, Outputs
Signal Name Notes To
ROW0–2 Lines for keyboard read (keypad inputs). Internal pull–up of
MCU is used
XPWRON Power on control fro keyboard PWRU
KBINT Keyboard interrupt request, falling edge active AUDIO
Original 42/96
CTRLU
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Technical Documentation
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