The RH-41 is a dual band transceiver unit designed for TDMA800/1900 networks. The
transceiver consists of the engine module (ST6_11) and the various assembly parts.
The transceiver has a full graphic display and the user interface is based on a Jack style
UI with two soft keys. An internal antenna is used in the phone, and there is no connection to an external antenna. The transceiver also has a low leakage tolerant earpiece and
an omnidirectional microphone that provides excellent audio quality.
Both the analog and digital modes have different states controlled by the Cellular SW.
Some examples are Idle State (on ACCH), Camping (on DCCH), Scanning, Conversation,
NSPS (No Service Power Save, previously OOR = Out of Range).
3Local mode (both Cellular SW and UI SW non active)
4Test mode (Cellular SW active but UI SW non active)
All of the EIA/TIA-136-270A requirements are not exactly specified over the temperature
range. For example, the RX sensitivity requirement is 3dB lower over the –30 - +60 °C
range.
Engine Module
Baseband Module
The core part of the transceiver’s baseband (see the figure below) consists of two ASICs
— the UEM and UPP — and flash memory. The following sections illustrate and explain
these parts in detail.
UEM is the Universal Energy Management IC for digital hand portable phones. In addition to energy management, it performs all the baseband’s mixed-signal functions.
Most UEM pins have 2kV ESD protection, and those signals considered to be more easily
exposed to ESD, have 8kV protection within the UEM. These kinds of signals are (1) all
audio signals, (2) headset signals, (3) BSI, (4) Btemp, (5) Fbus, and (6) Mbus signals.
Regulators
The UEM has six regulators for baseband power supplies and seven regulators for RF
power supplies. The VR1 regulator has two outputs: (1) VR1a and (2) VR1b. In addition to
these, there are two current generators — IPA1 and IPA2 — for biasing purposes.
A bypass capacitor (1uF) is required for each regulator output to ensure stability.
Reference voltages for regulators require external 1uF capacitors. Vref25RF is the reference voltage for the VR2 regulator, Vref25BB is the reference voltage for the VANA,
VFLASH1, VFLASH2, VR1 regulators, Vref278 is the reference voltage for the VR3, VR4,
VR5, VR6, VR7 regulators, and VrefRF01 is the reference voltage for the VIO, VCORE regulators and for the radio frequency (RF).
BBRFCurrent
VANA: 2.78Vtyp 80mA maxVR1a:4.75V 10mA max
VR1b:4.75V
Vflash1: 2.78Vtyp 70mA maxIPA2: 0-5mA
Vflash2: 2.78Vtyp
40mA max
VIO: 1.8Vtyp
150mA max
Vcore: 1.0-1.8V
200mA max
VR2:2.78V 100mA max
VR4: 2.78V 50mA max
VR5: 2.78V 50mA max
VR6: 2.78V 50mA max
VR7: 2.78V 45mA max
IPA1: 0-5mA
The VANA regulator supplies the baseband’s (BB) internal and external analog circuitry.
It is disabled in the Sleep mode.
The Vflash1 regulator supplies the LCD, the digital parts of the UEM and Taco ASIC. It is
enabled during startup and goes into the low Iq-mode when in the Sleep mode.
The VIO regulator supplies both the external and internal logic circuitries. It is used by
the LCD, flash and UPP. The regulator goes into the low Iq-mode when in the Sleep mode.
The VCORE regulator supplies the DSP and the core part of the UPP. The voltage is programmable and the startup default is 1.5V. The regulator goes into the low Iq-mode
when in the Sleep mode.
The VR1 regulator uses two LDOs (VR1A and VR1B) and a charge pump. The charge pump
requires one external 1uF capacitor in the Vpump pin and a 220nF flying capacitor
between the CCP and CCN pins. In practice, the 220nF flying capacitor is formed by 2 x
100nF capacitors that are parallel to each other. The VR1A regulator is used by the Taco
RF ASIC.
The VR2 regulator is used to supply the (1) external RF parts, (2) lower band up converter, (3) TX power detector module, and (4) Taco. In light load situations, the VR2 regulator can be set to the low Iq-mode.
The VR3 regulator supplies the VCTCXO and Taco in the RF. It is always enabled when the
UEM is active. When the UEM is in the Sleep mode, the VR3 is disabled.
The VR4 regulator supplies the RX frontends (LNA and RX mixers).
The VR5 regulator supplies the lower band PA. In light load situations, the VR5 regulator
can be set to the low Iq-mode.
The VR6 regulator supplies the higher band PA and TX amplifier. In light load situations,
the VR6 regulator can be set to the low Iq-mode.
The VR7 regulator supplies the VCO and Taco. In light load situations, the VR7 regulator
can be set to the low Iq-mode.
The IPA1 and IPA2 are programmable current generators. A 27Ω/1%/100ppm external
resistor is used to improve the accuracy of the output current. The IPA1 is used by the
lower PA band and IPA2 is used by the higher PA band.
RF Interface
The interface between the baseband and the RF section is also handled by the UEM. It
provides A/D and D/A conversion of the in-phase and quadrature receive and transmit
signal paths. It also provides A/D and D/A conversions of received and transmitted audio
signals to and from the UI section. The UEM supplies the analog AFC signal to the RF section, according to the UPP DSP digital control.
Charging Control
The CHACON block of the UEM asics controls charging. The needed functions for the
charging controls are the (1) pwm-controlled battery charging switch, (2) charger-monitoring circuitry, (3) battery voltage monitoring circuitry, and (4) RTC supply circuitry for
backup battery charging (Not used in RH-41). In addition to these, external components
are needed for EMC protection of the charger input to the baseband module.
Digital Interface
Data transmission between the UEM and the UPP is implemented using two serial con-
nections, DBUS (programmable clock) for DSP and CBUS (1.0MHz GSM and 1.08MHz
TDMA) for MCU. The UEM is a dual voltage circuit: the digital parts are run from 1.8V
and the analog parts are run from 2.78V. The Vbat (3,6V) voltage regulators's input is
also used.
Audio Codec
The baseband supports two external microphone input areas and one external earphone
output. The input can be taken from an internal microphone, a headset microphone or
from an external microphone signal source through a headset connector. The output for
the internal earpiece is a dual-ended type output, and the differential output is capable
of driving 4Vpp to the earpiece with a 60 dB minimum signal as the total distortion ratio.
The input and output signal source selection and gain control is performed inside the
UEM Asic, according to the control messages from the UPP.
UI Drivers
There is a single output driver for the buzzer, display, and keyboard LEDs inside the UEM.
These generate PWM square wave for the various devices.
AD Converters
The UEM is equipped with an 11-channel analog-to-digital converter. Some AD converter
channels (LS, KEYB1-2) are not used in RH-41. The AD converters are calibrated in the
production line.
UPP
Introduction
RH-41 uses the UPPv4M ASIC. The RAM size is 4M. The processor architecture consists of
both the DSP and the MCU processors.
Blocks
The UPP is internally partitioned into two main parts: (1) the Brain and (2) the Body.
1The Processor and Memory System (that is, the Processor cores, Mega-cells,
internal memories, peripherals and external memory interface) is known as the
Brain.
The Brain consists of the following blocks: (1) the DSP Subsystem (DSPSS), (2) the
MCU Subsystem (MCUSS), (3) the emulation control EMUCtl, (4) the program/
data RAM PDRAM, and (5) the Brain Peripherals–subsystem (BrainPer).
2The NMP custom cellular logic functions are known as the Body.
The Body contains interfaces and functions needed for interfacing other baseband and RF parts. The body consists of, for example, the following sub-blocks:
(1) MFI, (2) SCU, (3) CTSI, (4) RxModem, (5) AccIF, (6) UIF, (7) Coder, (8) BodyIF,
and (9) PUP.
The RH-41 transceiver uses a 16-Mbit flash as its external memory. The VIO regulator is
used as a power supply for normal in-system operation. An accelerated program/erase
operation can be obtained by supplying Vpp of 12 volt to the flash device.
The device has two read modes: asynchronous and burst. The burst read mode is utilized
in RH-41, except for the start-up, when the asynchronous read mode is used for a short
time.
User Interface Hardware
LCD
Introduction
RH-41 uses a black-and-white GD46 84x48 full dot matrix graphical display. The LCD
module includes the LCD glass, the LCD COG-driver, an elastomer connector, and a metal
frame. The LCD module is included in the lightguide assembly module.
Interface
The LCD is controlled by the UI SW and the control signals are from the UPP ASIC. The
VIO and Vflash1 regulators supply the LCD with power.
The LCD has an internal voltage booster and a booster capacitor is required between
Vout and GND.
Pin 3 (Vss9) is the LCD driver’s ground and Pin 9 (GND) is used to ground the metal
frame.
Keyboard
Introduction
The RH-41 keyboard style follows the Nokia Jack style, without side keys for volume control. The PWR key is located at the top of the phone.
All signals for the keyboard come from the UPP ASIC, except PWRONX line for the power
key signal which is connected directly to the UEM. The pressing of the PWR key grounds
the PWRONX line and the UEM generates an interrupt to UOO, which is then recognized
as a PWR key press.
Up
Down
S RightS Left
EndSend
12 3
4
7
*
Figure 3: Placement of keys
56
8
0
#
9
Keys
Other keys are detected so that when a key is pressed down, the metal dome connects
one S-line and one R-line of the UPP together and creates an interrupt for the SW. This
kind of detection is also known as metaldome detection. The matrix of how lines are connected and which lines are used for different keys is described in the following table. The
S-line S0 and R-line R5 are not used at all.