Nokia NSW–6, 8860 Schema

PAMS Technical Documentation

Block Diagram of SE2 Module (Version 5100 Edit 120)

NSW–6

System Module SE2

U I

Issue 1 12/1999

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PAMS Technical Documentation

Circuit Diagram of SE2 Module RX (Version 5100 Edit 236)

TP

NSW–6

System Module SE2

Issue 1 12/1999

 Nokia Mobile Phones Ltd.

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PAMS Technical Documentation

Circuit Diagram of SE2 Module TX (Version 5100 Edit 573)

NSW–6

System Module SE2

TP

Issue 1 12/1999

 Nokia Mobile Phones Ltd.

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PAMS Technical Documentation

Circuit Diagram of SE2 Module Audio (Version 5100 Edit 320)

NSW–6

System Module SE2

Issue 1 12/1999

 Nokia Mobile Phones Ltd.

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PAMS Technical Documentation

Circuit Diagram of SE2 Module CTRLU (Version 5100 Edit 406)

NSW–6

System Module SE2

Issue 1 12/1999

 Nokia Mobile Phones Ltd.

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PAMS Technical Documentation

Circuit Diagram of SE2 Module Synthesizer (Version 5100 Edit 195)

NSW–6

System Module SE2

Issue 1 12/1999

 Nokia Mobile Phones Ltd.

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PAMS Technical Documentation

Circuit Diagram of SE2 Module PWRU (Version 5100 Edit 409)

NSW–6

System Module SE2

Issue 1 12/1999

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PAMS Technical Documentation

Circuit Diagram of SE2 Module User interface (Version 5100 Edit 180)

NSW–6

System Module SE2

Issue 1 12/1999

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A–8

PAMS Technical Documentation

Parts Placement Diagram of SE2 Module (Version 10_v3) 1/2

NSW–6

System Module SE2

J162

Test point description

Test

Name From–to Level Description

point

J121 PCMSCLK COBBA A4– MAD L4 8.0 kHz (digital), 8.1 kHz

(analog)

J140 PURX CCONT A5–MAD M1, D201

B4, COBBA D5

J141 CCONTINT CCONT B7–MAD B10 Pulse active 2.8V,

Reset state 0V, nor­mal state 2.8V

RESET power up/down

Charger interrupt

non–active 0V

J142 RFCEN MAD J3– D201 A5, CCONT

G4

J143 SLEEPCLK CCONT B8– MAD M2 Pulsed DC <

Pulse active 2.8V,
non–active 0V

Active state

32.768 kHz, power on

0.8V/>2.4V

J150 WDDIS/PWRONX X101–CCONT E4 Pulse active 0V,

Watchdog disable

non–active 2.8V

J151 GND J156–GND Ground for WDDIS

J261

J131

J260

J265

J130

J142

J255

J262

Connect for

WD–disable

J213

J151

J210

J150

J212 J141

J140

J209

J211

J143 SLEEPCLK

J201

J207

J207 RAMSELX MAD M10– D200 B5
J208 ROM1SELX MAD N10– D201 D7
J209 COBBASIO MAD N4– COBBA B5 Bidirectional data line
J210 COBBACLK COBBA A2– MAD N2 Pulsed DC

COBBA system clock

(<0.5V/>2.15V)
J21 1 COBBADAX MAD N3– COBBA C3 Data ready flag
J212 DATASELX MAD J2– CCONT A7 Read/write enable
J213 RFCSETTLED MAD M5– COBBA C5 Pulse active 2.8V,

Active state

non–active 0 V
J262 COBBACSX MAD L5– COBBA A5 Chip select
J255 RFC EROTUS 25– COBBA B1 0.7 Vpp sinewave 19.44 MHz clock
J260 PCMRXDAT A MAD N5– COBBA A7 Receive data line
J261 PCMTXDAT A COBBA B4– MAD M4 Transmit data line
J265 PCMDCLK COBBA C4– MAD M3 1.08 MHz (digital), 1.215

MHz (analog)

Issue 1 12/1999

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PAMS Technical Documentation

Parts Placement Diagram of SE2 Module (Version 10_v3) 2/2

NSW–6

System Module SE2

001
002

003

004

005

Test point Name From–to Level Description

J163 TXPWR1
001 PCMSCLK
002 L–GND
003 FBUS–TX
004 FBUS–RX
005 MBUS

Issue 1 12/1999

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