Copyrightã 2000 Nokia Mobile Phones. All Rights Reserved
Page 4
Programmes After Market Services
This document is intended for use by qualified service personnel only.
Company Policy
Our policy is of continuous development; details of all technical modifications will be
included with service bulletins.
While every endeavour has been made to ensure the accuracy of this document, some
errors may exist. If any errors are found by the reader, NOKIA MOBILE PHONES Ltd.
should be notified in writing.
Please state:
Technical Documentation
IMPORTANT
Title of the Document + Issue Number/Date of publication
Latest Amendment Number (if applicable)
Page(s) and/or Figure(s) in error
Please send to: Nokia Mobile Phones Ltd.
PAMS Technical Documentation
PO Box 86
FIN-24101 SALO
Finland
Issue 1 06/00
Copyrightã 2000 Nokia Mobile Phones. All Rights Reserved
Page 5
Programmes After Market Services
Technical Documentation
Warnings and Cautions
Please refer to the phone's user guide for instructions relating to operation, care and
maintenance including important safety information. Note also the following:
Warnings:
1. CARE MUST BE TAKEN ON INSTALLATION IN VEHICLES FITTED WITH ELECTRONIC ENGINE MANAGEMENT SYSTEMS AND ANTI-SKID BRAKING SYSTEMS. UNDER CERTAIN FAULT CONDITIONS, EMITTED RF ENERGY CAN
AFFECT THEIR OPERATION. IF NECESSARY, CONSULT THE VEHICLE DEALER/
MANUFACTURER TO DETERMINE THE IMMUNITY OF VEHICLE ELECTRONIC
SYSTEMS TO RF ENERGY.
2. THE HANDPORTABLE TELEPHONE MUST NOT BE OPERATED IN AREAS LIKELY
TO CONTAIN POTENTIALLY EXPLOSIVE ATMOSPHERES EG PETROL STATIONS
(SERVICE STATIONS), BLASTING AREAS ETC.
3. OPERATION OF ANY RADIO TRANSMITTING EQUIPMENT, INCLUDING CELLU-
Cautions:
1. Servicing and alignment must be undertaken by qualified personnel only.
2. Ensure all work is carried out at an anti-static workstation and that an anti-
3. Ensure solder, wire, or foreign matter does not enter the telephone as dam-
4. Use only approved components as specified in the parts list.
5. Ensure all components, modules screws and insulators are correctly re-fit-
LAR TELEPHONES, MAY INTERFERE WITH THE FUNCTIONALITY OF INADEQUATELY PROTECTED MEDICAL DEVICES. CONSULT A PHYSICIAN OR THE
MANUFACTURER OF THE MEDICAL DEVICE IF YOU HAVE ANY QUESTIONS.
OTHER ELECTRONIC EQUIPMENT MAY ALSO BE SUBJECT TO INTERFERENCE.
static wrist strap is worn.
age may result.
ted after servicing and alignment. Ensure all cables and wires are repositioned correctly.
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Copyrightã 2000 Nokia Mobile Phones. All Rights Reserved
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Programmes After Market Services
Technical Documentation
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Copyrightã 2000 Nokia Mobile Phones. All Rights Reserved
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Programmes After Market Services
NSB-7 Series Transceivers
General Information
Issue 1 06/00ãNokia Mobile Phones Ltd.
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NSB-7
General InformationPAMS Technical Documentation
Table of Contents
Page No
General Information................................................................................................................1
Hand portables ...................................................................................................................................... 4
General Specifications of Transceiver NSB-7 ............................................................................... 8
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NSB-7
PAMS Technical DocumentationGeneral Information
List of Figures
Page No
Fig 1 Hand portables..................................................................................................................................... 4
System Module......................................................................................................................................... 8
AFC function ........................................................................................................................................57
DC Compensation ...............................................................................................................................58
Parts List of RB9 (EDMS Issue 5.3) (Code: 0201512)................................................................ 59
Schematic Diagrams: RB9 (at the back of the binder)
Circuit Diagram of Power Supply (Version 05.21 Edit 64) for layout 5 ............................... A-1
Circuit Diagram of CPU Block (Version 05.21 Edit 45) for layout 5 ..................................... A-2
Connection between RF and Baseband modules (Version 05.21 Edit 37) for layout 5... A-3
Fig 17 Power Control Loop Diagram......................................................................................................... 57
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NSB-7
System ModulePAMS Technical Documentation
Transceiver NSB-7
Introduction
The NSB-7 is a single band transceiver unit designed for the GSM1900 networks. It is
GSM1900 power class 1 (1W) transceiver.
The transceiver consists of System/RF module (RB9), Display module (UX7) and assembly
parts.
The transceiver has a full graphic display and the user interface is based on a jack style
UI with two soft keys.
A back mounted antenna is used, there is no connection to an external antenna.
The transceiver has a low leakage tolerant earpiece and an omnidirectional microphone,
providing excellent audio quality. The transceiver supports full rate, an enhanced full rate
and a half rate speech decoding.
An integrated IR link provides a connection between two NSB-7 transceivers or a transceiver and a PC (internal data), or a transceiver and a printer.
The small SIM (Subscriber Identity Module) card is located under the back cover of the
phone.
Operational Modes
There are five different operational modes:
•power off mode
•idle mode
•active mode
•charge mode
•local mode
In the power off mode only the circuits needed for power up are supplied.
In the idle mode circuits are powered down and only the sleep clock is running.
In the active mode all the circuits are supplied with power although some parts might be
in idle state part of the time.
The charge mode is effective in parallel with all previous modes. The charge mode itself
consists of two different states, i.e. the fast charge and the maintenance mode.
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The local mode is used for alignment and testing.
Interconnection Diagram
Keyboard LCD module
149
SIM
Antenna
Microphone IR Link Earpiece HF/HS
6
4
Battery
Radio
Module
2
RB9
2+2
Charger
2824
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System ModulePAMS Technical Documentation
System Module
Baseband Module
The ASICs are in the uBGA package. Flash and SRAM chips are inside the same package.
EEPROM is software emulated with Flash. These changes have decreased the number of
I/O between the ICs. Smaller I/O count has made using smaller packages possible
The baseband architecture supports a power saving function called ”sleep mode”. This
sleep mode shuts off the VCTCXO, which is used as system clock source for both RF and
baseband. During the sleep mode the system runs from a 32 kHz crystal. The phone is
waken up by a timer running from this 32 kHz clock supply. The sleeping time is determined by some network parameters. The sleep mode is entered when both the MCU and
the DSP are in stand-by mode and the normal VCTCXO clock has been switched off.
The battery charging is controlled by a PWM signal from the CCONT. The PWM duty cycle
is determined by a charging software and is fed to the CHAPS charging switch.
Two types of chargers can be connected to the phone. Standard chargers (two wires)
provide a coarse supply power, which is switched by the CHAPS for suitable charging
voltage and current. Advanced chargers (three wires) are equipped with a control input.
Three wire chargers are treated like two wire ones.
Block Diagram
TX/RX SIGNALS
COBBA SUPPLY
COBBA
UI
MAD
IR
+
MEMORIES
RF SUPPLIES
CCONT
BB SUPPLY
CHAPS
PA SUPPLY
SLEEP CLOCK
32kHz
CLK
VBAT
SIM
13MHz
CLK
SYSTEM CLOCK
BATTERY
BASEBAND
EXT. AUDIO
HS-connector
Charger
connector
Figure 1: Block Diagram
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PAMS Technical DocumentationSystem Module
Technical Summary
The baseband module consists of four ASICs; CHAPS, CCONT, COBBA-GJP and
MAD2WD1, which take care of the baseband functions of the engine.
The baseband is running from a 2.8V power rail, which is supplied by a power controlling
ASIC CCONT. MAD2WD1 supply voltages are VBB and VCORE (V2V), VBB feed I/O pins so
that MAD2WD1 is externally fully compatible with old versions. VCORE feed MAD2WD1
internal functions supply voltage; CPU, DSP and system logic. In the CCONT there are 6
individually controlled regulator outputs for RF-section and two outputs for the baseband. In addition there is one +5V power supply output (V5V). The CCONT contains also a
SIM interface, which supports both 3V and 5V SIM-cards. A real time clock function is
integrated into the CCONT, which utilizes the same 32kHz clock supply as the sleep
clock. A backup power supply is provided for the RTC, which keeps the real time clock
running when the main battery is removed. The backup power supply is a rechargable
battery. The backup time with the battery is ten minutes minimum.
The analog interface between the baseband and the RF section is handled by a COBBA
ASIC. COBBA provides A/D and D/A conversion of the in-phase and quadrature receive
and transmit signal paths and also A/D and D/A conversions of received and transmitted
audio signals to and from the user interface. The COBBA supplies the analog TXC and AFC
signals to RF section according to the MAD DSP digital control. Data transmission
between the COBBA and the MAD is implemented using serial bus for high speed signalling and for PCM coded audio signals. Digital speech processing is handled by the MAD
ASIC. COBBA is a dual voltage circuit, the digital parts are running from the baseband
supply VBB and the analog parts are running from the analog supply VCOBBA.
The baseband supports both internal and external microphone inputs and speaker outputs. Input and output signal source selection and gain control is done by the COBBA
according to control messages from the MAD. Keypad tones, DTMF and other audio tones
are generated and encoded by the MAD and transmitted to the COBBA for decoding. A
buzzer and an external vibra alert control signals are generated by the MAD with separate PWM outputs.
EMC shielding is implemented using a metallized plastic frame. On the other side the
engine is shielded with PCB grounding. Heat generated by the circuitry will be conducted
out via the PCB ground planes.
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Technical Specifications
Absolute Maximum Ratings
ParameterRating
Battery voltage-0.3... 5.3 V
Charger input voltage-5.0... 16V
DC Characteristics
Line SymbolMinimum
Supply battery voltage3.03.94.8V
Battery powerup voltage (HW)2.93.03.1V
Battery cut off voltage (HW)2.72.82.9V (3.1 V SW cutoff)
Regulated baseband supply voltage
Regulated baseband supply current
COBBA analog supply voltage2.72.82.85V
COBBA analog supply current520100mA
Regulated 5V supply voltage4.85.05.2V
Regulated 5V supply current0130mA
Regulated 5V SIM supply voltage4.85.05.2V
Regulated 5V SIM supply current31030mA
Regulated 3V SIM supply voltage2.83.03.2V
2.72.82.85V
350125mA
Typical /
Nominal
MaximumUnit / Notes
Regulated 3V SIM supply current1630mA
Voltage reference1.47751.51.5225V
External and Internal Signals and Connections
This section describes the external electrical connection and interface levels on the baseband. The electrical interface specifications are collected into tables that covers a connector or a defined interface.
DC (charger) connector
DC (charger) connector is physically integrated in the same component with the acces-
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sory interface connector. DC connector has both jack and contact pads for desk stand.
NameMinTyp MaxUnitNotes
VIN012V
0850mA
L_GND00.3V
Service Connector
NameParameterMinTypMaxUnitRemark
MBUSSerial clock from
the Prommer
FBUS_RXSerial data from the
Prommer
FBUS_TXData acknowledge
to the Prommer
GNDGND00VGround
0
2.0
0
2.0
0
2.0
logic low
logic low
logic low
logic high
logic low
logic high
0.8
2.85
0.8
2.85
0.5
2.85
VPrommer detection and Serial
Clock for synchronous communication
VReceive Data from Prommer to
Baseband
VTransmit Data from Baseband to
Prommer
The service connector is used as a flash programming interface for updating (i.e. re-programming) the flash program memory and an electrical access for services to the engine.
When the flash prommer is connected to the phone supply power is provided through the
battery contacts and the phone is powered up with a pulse given to the BTEMP line.
Battery connector
The BSI contact on the battery connector is used to detect when the battery is to be
removed to be able to shut down the operations of the SIM card before the power is lost
if the battery is removed with power on. The BSI contact disconnects earlier than the
supply power contacts to give enough time for the SIM and LCD shut down.
NameMinTypMaxUnitNotes
VBATT3.03.94.2VBattery voltage
BSI02.85VBattery size indication
Phone has 100kohm pull-up resistor.
SIM Card removal detection
(Threshold is 2.4V@VBB=2.8V)
68kohmBattery indication resistor (BLB-2)
kohmBattery indication resistor (service battery)
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NameMinTypMaxUnitNotes
BTEMP01.4VBattery temperature indication
Phone has a 100k (+/-5%) pull-up resistor,
Battery package has a NTC pull-down
resistor: 47k +/-5%@+25C, B=4050 +/3%
2.1
510330
01kohmLocal mode initialization (in production)
BGND00VBattery ground
V
ms
Phone power up by battery (input)
Power up pulse width
SIM card connector
The SIM card connector is located on the engine beside the battery pack.
PinNameParameterMinTypMaxUnitNotes
4GND GND00VGround
3, 5VSIM5V SIM Card
3V SIM Card
6DATA5V Vin/Vout
3V Vin/Vout
2SIMRST5V SIM Card
3V SIM Card
4.8
2.8
4.0
0
2.8
0
4.0
2.8
5.0
3.0
“1”
“0”
“1”
“0”
“1”
“1”
5.2
3.2
VSIM
0.5
VSIM
0.5
VSIM
VSIM
VSupply voltage
VSIM data
Trise/Tfall max 1us
VSIM reset
1SIMCLKFrequency
Trise/Tfall
3.25
25
MHz
ns
SIM clock
RTC backup battery
The RTC block in CCONT needs a power backup to keep the clock running when the
phone battery is disconnected. The backup power is supplied from a rechargable Li-ion
battery that can keep the clock running ten minutes minimum. The backup battery is
charged from the main battery through CHAPS.
SignalParameterMinTypMaxUnitNotes
VBACKBackup battery charging
from CHAPS
Backup battery charging
from CHAPS
VBACKBackup battery supply to
CCONT
3.023.153.28V
100200500uAVout@VBAT-0.2V
23.28V
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SignalParameterMinTypMaxUnitNotes
Backup battery supply to
CCONT
Functional Description
Power Distribution
In normal operation the baseband is powered from the phone‘s battery. The battery consists of one Lithium-Ion cell. An external charger can be used for recharging the battery
and supplying power to the phone.
The baseband contains parts that control power distribution to whole phone excluding
those parts that use continuous battery supply. The battery feeds power directly to the
CCONT and UI (buzzer and display and keyboard lights).
The power management circuit CHAPS provides protection against over voltages, charger
failures and pirate chargers etc. that would otherwise cause damage to the phone.
RF
UI
(LCD,
backlights,
buzzer)
80uA
RF supply voltages
VCobba
Vbb
Battery connector
VB
CCONTCOBBA GJP
Baseband
MAD2 +
MEMORY
CHRG_CTRL
VCORE
CHAPS
RTC backup
VChar
Charger & headset connector
Vbatt
Figure 2: Block Diagram of Power Distribution
Battery Interface
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System ModulePAMS Technical Documentation
Battery charging
The electrical specifications give the idle voltages produced by the acceptable chargers
at the DC connector input. The absolute maximum input voltage is 30V due to the transient suppressor that is protecting the charger input. At phone end there is no difference
between a plug-in charger or a desktop charger. The DC-jack pins and bottom connector
charging pads are connected together inside the phone.
MAD
MAD
VBAT
CCONTINT
CCONT
0R22
GND
ICHAR
PWM_OUT
VCHAR
LIM
VOUT
CHAPS
RSENSE
PWM
VCH
GND
22k
TRANSCEIVER
1u
100k
1n
10k
Figure 3: Charging Block Diagram
30V
CHARGER
2A
VIN
L_GND
Startup Charging
When a charger is connected, the CHAPS is supplying a startup current minimum of
130mA to the phone. The startup current provides initial charging to a phone with an
empty battery. Startup circuit charges the battery until the battery voltage level is
reaches 3.0V (+/- 0.1V) and the CCONT releases the PURX reset signal and program execution starts. Charging mode is changed from startup charging to PWM charging that is
controlled by the MCU software. If the battery voltage reaches 3.55V (3.75V maximum)
before the program has taken control over the charging, the startup current is switched
off. For accessory detection, startup current is possible cut via CCUT line. The startup
current is switched on again when the battery voltage is sunken 100mV (nominal).
Output overvoltage protection is used to protect phone from damage. This function is
also used to define the protection cutoff voltage for the Lithium-Ion battery. The power
switch is immediately turned OFF if the voltage in VOUT rises above the selected limit
VLIM.
ParameterSymbolLIM inputMinTypMaxUnit
Output voltage cutoff limit (during transmission or Li-battery)
VLIMLOW4.44.64.8V
The voltage limit (VLIM1 or VLIM2) is selected by logic LOW or logic HIGH on the CHAPS
(N101) VLIM input pin.
When the switch in output overvoltage situation has once turned OFF, it stays OFF until
the battery voltage falls below VLIM and PWM = LOW is detected. The switch can be
turned on again by setting PWM = HIGH.
VCH
VCH<VOUT
t
VOUT
VLIM
SWITCH
PWM (32Hz)
t
ONOFF
Figure 4: Output Overvoltage Protection (in principle; not in time scale)
ON
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"1"
3
4
5
6
7
System ModulePAMS Technical Documentation
Battery Removal During Charging
Output overvoltage protection is also needed in case the main battery is removed when
charger connected or charger is connected before the battery is connected to the phone.
With a charger connected, if VOUT exceeds VLIM, CHAPS turns switch OFF until the
charger input has sunken below Vpor (nominal 3.0V, maximum 3.4V). MCU software will
stop the charging (turn off PWM) when it detects that battery has been removed. The
CHAPS remains in protection state as long as PWM stays HIGH after the output overvoltage situation has occured.
2. VOUT exceedslimit VLIM(X),switch is turned immediatelyOFF
3
VOUT falls (because no battery) , also VCH<Vpor (standard chargers full-rectified
output).WhenVCH>VporandVOUT<VLIM(X)->switchturnedonagain(alsoPWM
is still HIGH) a nd VOUT again exceeds VLIM(X).
4. Software sets PWM = LOW -> CHAPS does n ot enter PWM mode
5. PWM low -> Startup mode, startup current flows until Vstart limit reached
6. VOUT exceeds limit Vstart, Istart is turned off
7. VCH falls below Vpor
2
1
& C in phone
Istart off due to VCH<Vpor
Vstarthys
t
t
t
Figure 5: Output Overvoltage Protection When Battery Removed (in principle; not in time scale)
PWM
When a charger is used, the power switch is turned ON and OFF by the PWM input. PWM
rate is 1Hz. When PWM is HIGH, the switch is ON and the output current Iout = charger
current - CHAPS supply current. When PWM is LOW, the switch is OFF and the output
current Iout = 0. To prevent the switching transients inducing noise in audio circuitry of
the phone soft switching is used.
Battery Identification
Different battery types are identified by a pulldown resistor inside the battery pack. The
BSI line inside transceiver has a 100k pull-up to VBB. The MCU can identify the battery
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by reading the BSI line DC-voltage level with a CCONT (N100) A/D-converter.
NameMinTypMaxUnitNotes
BSI02.8VBattery size indication 100k pull-up resistor to
VBB in phone
SIM Card removal detection (Threshold is
2.4V@VBB=2.8V)
68kohmIndication of a BLB-2 battery (600mAh Li-Ion)
22kohmIndication resistor for a service battery
-55%Indication resistor and pull-up resistor tolerance
VBATT
BATTERY
BTEMP
BSI
R
s
BGND
2.8V
10n
100k
10k
TRANSCEIVER
BSI
SIMCardDetX
CCONT
MAD
Figure 6: BSI connections for all battery types
The battery identification line is used also for battery removal detection. The BSI line is
connected to a SIMCardDetX line of MAD2. SIMCardDetX is a threshold detector with a
nominal input switching level 0.85xVcc for a rising edge and 0.55xVcc for a falling edge.
The battery removal detection is used as a trigger to power down the SIM card before the
power is lost. The BSI contact in the battery contact disconnects before the other con-
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tacts so that there is a delay between battery removal detection and supply power off.
Vcc
0.85 _ 0.05 Vcc
0.55 _ 0.05 Vcc
SIMCARDDETX
GND
Figure 7: SIMCardDetX Detection Levels
SigOut
Battery Temperature
The battery temperature is measured with a NTC inside the battery pack. The BTEMP line
inside transceiver has a 100k pull-up to VREF. The MCU can calculate the battery temperature by reading the BTEMP line DC-voltage level with a CCONT (N100) A/D-converter.
PinNameMinTypMaxUnitNotes
3BTEMP01.4VBattery temperature indication 100k pull-up
resistor to VREF in phone
Battery package has NTC pull-down resistor: 47k
+/-5%@+25C, B=4050 +/-3%
2.1
510320
47KohmService battery value
-55%100k pull-up resistor tolerance
V
ms
Phone power up by battery (input)
Power up pulse width
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VBATT
BATTERY
R
NTC
BSI
BTEMP
T
BGND
TRANSCEIVER
VREF
100k
10k
BTEMP
CCONT
Based on 47 kohm ± 5 % NTC with B = 4090 ±1.5 %. Without any alignment, with that
and 1 % pull-up resistor, ± 2.5 _C accuracy is achieved between - 20 and +60 _C (± 3.5
_C @ -40 ... +85 _C).
Supply Voltage Regulators
The heart of the power distribution is the CCONT. It includes all the voltage regulators
and feeds the power to the whole system. The baseband digital parts are powered from
the VBB regulator which provides 2.8V baseband supply. The baseband regulator is active
always when the phone is powered on. The VBB baseband regulator feeds MAD and
memories, VCORE for MAD core, COBBA digital parts and the LCD driver in the UI section.
There is a separate regulator for a SIM card. The regulator is selectable between 3V and
5V and controlled by the SIMPwr line from MAD to CCONT. The COBBA analog parts are
powered from a dedicated 2.8V supply VCOBBA. The CCONT supplies also 5V for RF and
for flash VPP. The CCONT contains a real time clock function, which is powered from a
RTC backup when the main battery is disconnected. The RTC backup is rechargable polyacene battery. The battery is charged from the main battery voltage by the CHAPS when
the main battery voltage is over 3.2V.
Figure 8: Standard Battery BTEMP connection
Operating ModeVrefRF REGVCOBBAVBBVSIMSIMIFVcore
Power offOffOffOffOffOffPull-downOff
Power onOnOn/OffOnOnOnOn/OffOn
ResetOnOff
OnOnOffPull-downOn
VR1 On
SleepOnOffOffOnOnOn/OffOn
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NOTE: COBBA regulator is off in SLEEP mode. Its output pin may be fed from VBB
in SLEEP mode by setting bit RFReg(5) to’1’ (default).
CCONT includes also five additional 2.8V regulators providing power to the RF section.
These regulators can be controlled either by the direct control signals from MAD or by
the RF regulator control register in CCONT which MAD can update. Below are the listed
the MAD control lines and the regulators they are controlling.
-TxPwr controls VTX regulator (VR5)
-RxPwr controls VRX regulator (VR2)
-SynthPwr controls all the rf regulators except VR1
-VCXOPwr controls VXO regulator (VR1)
CCONT generates also a 1.5 V reference voltage VREF to COBBA. The VREF voltage is also
used as a reference to some of the CCONT A/D converters.
In addition to the above mentioned signals MAD includes also TXP control signal which
goes to HAGAR power control block. The transmitter power control TXC is led from
COBBA to HAGAR.
CharacteristicsConditionMinTypMaxUnit
Output current VR1-VR6Vout@2.8V100mA
Output current VR7
Depends on external BJT
Output current VR7BASE
Base current limit
Output current VBB On
Current limit 250mA
Output current VBB Sleep
Current limit 5mA
Output voltage VR1-VR7over full temperature, input
Output voltage VBBover full temperature, input
Output voltage V2V
(VCORE)
Vout@2.8V150mA
Vout@2.8V-10mA
Vout@2.8V
Vout@2.8V
voltage and load range
voltage and load range
Programmable:
Vout=1.3V+225mV*n
N = 0,1,2,3,4,5,6
2.72.82.85V
2.72.82.85V
1.302.65V
125
1
mA
mA
Output voltage V2V
(VCORE) tolerance
Line regulation (not VBB)F v 10kHz, 2)
VBAT>3.15V
-5+5%
49DB
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CharacteristicsConditionMinTypMaxUnit
Line regulation (not VBB)F v 100kHz, 2)
VBAT>3.15v
Line regulation VBB, V2V
(VCORE)
Load regulationT = 25_C0.61mV/mA
Supply current (each regulator) VR1...VR7
Supply current VBBON modeI
Supply current VBBSLEEP modeI
Output voltage V2V
(VCORE)
F v 100kHz 2)30DB
ON modeI
MAD2WD1 C10
MAD2WD1 C07
MAD2WD1 C05
40DB
/
out
60+330
/60+
out
250
/60+
out
100
2.65
1.75
1.75
I
/
out
10+540
I
/10+
out
400
I
/10+
out
150
mA
mA
mA
V
NOTE 1: Characteristics above are NOT valid if Vbat < 3.0V.
NOTE 2: Line regulation is 20dB for f<100kHz when battery voltage is lower than 3.1V.
Switched Mode Supply VSIM
There is a switched mode supply for SIM-interface. SIM voltage is selected via serial IO.
The 5V SMR can be switched on independently of the SIM voltage selection, but can’t be
switched off when VSIM voltage value is set to 5V.
CharacteristicsConditionMinTypMaxUnit
Output voltage VSIMOver temperature
Over current
Output voltage V5VOver temp & current4.85.05.2V
Output voltage V5V_2Over temperature5.06.0V
Output current VSIM Continuous DC 30mA
Output current V5VContinuous DC 30mA
Current consumption VSIMon
sleep
2.8
4.8
3.0
5.0
200
100
3.2
5.2
330
150
NOTE: VSIM and V5V can give together a total of 30mA.
V
uA
uA
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In the next figure the principle of the SMR / VSIM-functions is shown.
CCONTExternal
VBAT
V5V_4
V5V_3
V5V_2
VSIM
Power Up and Power Down
The baseband is powered up by:
1Pressing the power key, that generates a PWRONX interrupt signal from the
power key to the CCONT, which starts the power up procedure.
2Connecting a charger to the phone. The CCONT recognizes the charger from the
VCHAR voltage and starts the power up procedure.
3A RTC interrupt. If the real time clock is set to alarm and the phone is switched
off, the RTC generates an interrupt signal, when the alarm is gone off. The RTC interrupt
signal is connected to the PWRONX line to give a power on signal to the CCONT just like
the power key.
5V reg
V5V
Figure 9: Principle of the SMR Power Functions
5V
5/3V
4A battery interrupt. Intelligent battery packs have a possibility to power up the
phone. When the battery gives a short (10ms) voltage pulse through the BTEMP pin, the
CCONT wakes up and starts the power on procedure.
Power up with charger
When the charger is connected CCONT will switch on the CCONT digital voltage as soon
as the battery voltage exceeds 3.0V. The reset for CCONT’s digital parts is released when
the operating voltage is stabilized (50 us from switching on the voltages). Operating
voltage for VCXO is also switched on. The counter in CCONT digital section will keep
MAD in reset for 62 ms (PURX) to make sure that the clock provided by VCXO is stable.
After this delay MAD reset is released, and VCXO -control (SLEEPX) is given to MAD. The
next diagram explains the power on procedure with charger (the picture assumes empty
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battery, but the situation would be the same with full battery):
SLEEPX
PURX
CCPURX
Vbat
VR6
VR1
VBB (2.8V)
Vchar
Vref
123
1: Battery voltage over 3.0==>Digital voltages to CCONT (VBB)
2: CCONT digital reset released. VCXO turned on
3: 62ms delay before PURX released
Figure 10: Power Up With Charger
When the phone is powered up with an empty battery pack using the standard charger,
the charger may not supply enough current for standard powerup procedure and the
powerup must be delayed.
Power Up with the Power Switch (PWRONX)
When the power on switch is pressed the PWRONX signal will go low. CCONT will switch
on the CCONT digital section and VCXO as was the case with the charger driven power
up. If PWRONX is low when the 64 ms delay expires, PURX is released and SLEEPX control
goes to MAD. If PWRONX is not low when 64 ms expires, PURX will not be released, and
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CCONT will go to power off (digital section will send power off signal to analog parts)
SLEEPX
PURX
CCPURX
PWRONX
VR1,VR6
VBB (2.8V)
Vchar
123
1:Power switch pressed ==> Digital voltages on in CCONT (VBB)
2: CCONT digital reset released. VCXO turned on
3: 62 ms delay to see if power switch is still pressed.
Power Up by RTC
RTC (internal in CCONT) can power the phone up by changing RTCPwr to logical 1.
Power Up by IBI
IBI can power CCONT up by giving a short pulse (10ms) through the BTEMP line. After
powerup BTEMP will act as any other input channel for ADC.
When the PURX reset is released, the MAD releases the system reset ExtSysResetX and
the internal MCUResetX signals and starts the boot program execution from MAD
bootrom if MAD GenSDIO pin is pulled low or from external memory if GenSDIO pin is
pulled high. In normal operation the program execution continues from the flash program memory. If the MBUS line is pulled low during the power up the bootrom starts a
flash programming sequence and waits for the prommer response through FBUS_RX line.
Power Down
The baseband is powered down by:
1Pressing the power key, that is monitored by the MAD, which starts the power
down procedure.
Figure 11: Power Up With Switch
2If the battery voltage is dropped below the operation limit, either by not charging
it or by removing the battery.
3Letting the CCONT watchdog expire, which switches off all CCONT regulators and
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the phone is powered down.
4Setting the real time clock to power off the phone by a timer. The RTC generates
an interrupt signal, when the alarm is gone off. The RTC interrupt signal is connected to
the PWRONX line to give a power off signal to the CCONT just like the power key.
The power down is controlled by the MAD. When the power key has been pressed long
enough or the battery voltage is dropped below the limit the MCU initiates a power
down procedure and disconnects the SIM power. Then the MCU outputs a system reset
signal and resets the DSP. If there is no charger connected the MCU writes a short delay
to CCONT watchdog and resets itself. After the set delay the CCONT watchdog expires,
which activates the PURX and all regulators are switched off and the phone is powered
down by the CCONT.
If a charger is connected when the power key is pressed the phone enters into the acting
dead mode.
Modes of Operation
Acting Dead
If the phone is off when the charger is connected, the phone is powered on but enters a
state called ”acting dead”. To the user the phone acts as if it was switched off. A battery
charging alert is given and/or a battery charging indication on the display is shown to
acknowledge the user that the battery is being charged.
Active Mode
In the active mode the phone is in normal operation, scanning for channels, listening to
a base station, transmitting and processing information. All the CCONT regulators are
operating. There are several sub-states in the active mode depending on if the phone is
in burst reception, burst transmission, if DSP is working etc.
Sleep Mode
In the sleep mode all the regulators except the baseband VBB and the SIM card VSIM
regulators are off. Sleep mode is activated by the MAD after MCU and DSP clocks have
been switched off. The voltage regulators for the RF section are switched off and the
VCXO power control, VCXOPwr is set low. In this state only the 32 kHz sleep clock oscillator in CCONT is running. The flash memory power down input is connected to the ExtSysResetX signal, and the flash is deep powered down during the sleep mode.
The sleep mode is exited either by the expiration of a sleep clock counter in the MAD or
by some external interrupt, generated by a charger connection, key press, headset connection etc. The MAD starts the wake up sequence and sets the VCXOPwr and ExtSysResetX control high. After VCXO settling time other regulators and clocks are enabled for
active mode.
If the battery pack is disconnect during the sleep mode, the CCONT pulls the SIM interface lines low as there is no time to wake up the MCU.
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Charging
Charging can be performed in any operating mode.The battery type/size is indicated by a
resistor inside the battery pack. The resistor value corresponds to a specific battery
capacity. This capacity value is related to the battery technology as different capacity
values are achieved by using different battery technology.
The battery voltage, temperature, size and current are measured by the CCONT controlled
by the charging software running in the MAD.
The power management circuitry controls the charging current delivered from the
charger to the battery. Charging is controlled with a PWM input signal, generated by the
CCONT. The PWM pulse width is controlled by the MAD and sent to the CCONT through a
serial data bus. The battery voltage rise is limited by turning the CHAPS switch off when
the battery voltage has reached 4.2 V. Charging current is monitored by measuring the
voltage drop across a 220 mohm resistor.
Watchdog
The Watchdog block inside CCONT contains a watchdog counter and some additional
logic which are used for controlling the power on and power off procedures of CCONT.
Watchdog output is disabled when WDDisX pin is tied low. The WD–counter runs during
that time, though. Watchdog counter is reset internally to 32 s at power up. Normally it
is reset by MAD writing a control word to the WDReg.
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Audio Control
PCM serial interface
The interface consists of following signals: a PCM codec master clock (PCMDClk), a
frame synchronization signal to DSP (PCMSClk), a codec transmit data line (PCMTX) and
a codec receive data line (PCMRX). The COBBA-GJP generates the PCMDClk clock, which
is supplied to DSP SIO. The COBBA-GJP also generates the PCMSClk signal to DSP by
dividing the PCMDClk. The PCMDClk frequency is 512 kHz. PCMSClk frequency is 8.0 kHz.
PCMDClk
PCMSClk
PCMTxData
PCMRxData
sign extended
1514131201110
sign extended
MSB
MSB
LSB
LSB
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Digital Control
The baseband functions are controlled by the MAD ASIC, which consists of a MCU, a system ASIC and a DSP. MAD with the GSM/PCN specific ASIC is named to MAD2.
MAD2 WD1
MAD2 WD1 contains following building blocks:
-ARM RISC processor with both 16-bit instruction set (THUMB mode) and 32-bit
instruction set (ARM mode)
-TI Lead DSP core with peripherals:
-API (Arm Port Interface memory) for MCU-DSP communication, DSP code
download, MCU interrupt handling vectors (in DSP RAM) and DSP booting.
-Serial port (connection to PCM)
-Timer
-DSP memory
-BUSC (BusController for controlling accesses from ARM to API, System Logic
and MCU external memories, both 8- and 16-bit memories)
-System Logic
-CTSI (Clock, Timing, Sleep and Interrupt control)
-MCUIF (Interface to ARM via BUSC). Contains MCU BootROM
-DSPIF (Interface to DSP)
-MFI (Interface to COBBA AD/DA Converters)
-CODER (Block encoding/decoding and A51&A52 ciphering)
-AccIF (Accessory Interface)
-SCU (Synthesizer Control Unit for controlling 2 separate synthesizer)
-UIF (Keyboard interface, serial control interface for COBBA PCM Codec, LCD
Driver and CCONT)
-SIMI (SimCard interface with enhanced features)
-PUP (Parallel IO, USART and PWM control unit for vibra and buzzer)
-Flexpool
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The MAD2 operates from a 13 MHz system clock, which is generated from the 13Mhz
VCXO frequency. The MAD2 supplies a 6,5 MHz or a 13 MHz internal clock for the MCU
and system logic blocks and a 13 MHz clock for the DSP, where it is multiplied to 45.5
MHz DSP clock. The system clock can be stopped for a system sleep mode by disabling
the VCXO supply power from the CCONT regulator output. The CCONT provides a 32 kHz
sleep clock for internal use and to the MAD2, which is used for the sleep mode timing.
The sleep clock is active when there is a battery voltage available i.e. always when the
battery is connected.
MAD2WD1 supply voltages are VBB and VCORE (V2V), VBB feed I/O pins so that
MAD2WD1 is externally fully compatible with old versions. VCORE feed MAD2WD1
internal functions supply voltage; CPU, DSP and system logic.
Pin
No:
A1MCUGemIO 0O20MCU General pur-
C2LEADGNDLead Ground
D2Col4I/OUIF2InputProgramma-
D3Col3I/OUIF2InputProgramma-
H11MCUGenIO1I/O2Input,
E4GNDGround
D4Col2I/OUIF2InputProgramma-
C4Col1I/OUIF2Inputprogramma-
Pin Name
Pin
Type
Connecte
d to/
from
Drive
req. mA
Reset
State
pullup
NoteExplanation
pose output port
I/O line for keyboard
ble pullup
PR0201
ble pullup
PR0201
Pullup
PR0201
ble pullup
PR0201
ble pullup
PR0201
column 4
I/O line for keyboard
column 3
General purpose I/O
port
I/O line for keyboard
column 2
I/O line for keyboard
column 1
C3Col0I/OUIF2Inputprogramma-
ble pullup
PR0201
D1LCDCSXI/OUIF2Inputexternal pul-
lup/down
E1LEADVCCLead Power
F12LoByteSelXNC
I/O line for keyboard
column 0
serial LCD driver chip
select, parallel LCD
driver enable
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Pin
No:
E3Row5LCDCDI/OUIF2Input,
N4VCC_CORECore VCC in
E2Row4I/OUIF2Input,
F4Row3I/OUIF2Input,
F3Row2I/OUIF2Input,
Pin Name
Pin
Type
Connecte
d to/
from
Drive
req. mA
Reset
State
pullup
pullup
pullup
pullup
NoteExplanation
pullup
PR0201
3325c10
pullup
PR0201
pullup
PR0201
pullup
PR0201
Keyboard row5 data
I/O, serial LCD driver
command/data indi-
cator, parallel LCD
driver read/write
select
Power
I/O line for keyboard
row 4, parallel LCD
driver register selec-
tion control
I/O line for keyboard
row 3, parallel LCD
driver data
I/O line for keyboard
row 2, parallel LCD
driver data
F2Row1I/OUIF2Input,
pullup
F1Row0I/OUIF2Input,
pullup
L11JTDOO2Tri-stateJTAG data out
L5GNDGround
N12JTRstIInput,
pulldown
M12JTClkIInputpulldown
N13JTDIIInput,
pullup
M13JTMSIInput,
pullup
G13VCC_IOIO VCC in
L12CoEmu0I/O2Input,
pullup
pullup
PR0201
pullup
PR0201
pulldown
PD0201
PD0201
pullup
PR0201
pullup
PR0201
3325c10
pullup
PR0201
I/O line for keyboard
row 1, parallel LCD
driver data
I/O line for keyboard
row 0, parallel LCD
driver data
JTAG reset
JTAG Clock
JTAG data in
JTAG mode select
Power
DSP/MCU emulation
port 0
L13CoEmu1I/O2Input,
pullup
H4LEADGNDLead Ground
pullup
PR0201
DSP/MCU emulation
port 1
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Pin
No:
L1ARMGNDARM Ground
N3MCUAd0OMCU
K4ARMVCCARM Power
N2MCUAd1OMCU
N1MCUAd2OMCU
M4MCUAd3OMCU
M3MCUAd4OMCU
M2MCUAd5OMCU
M1MCUAd6OMCU
Pin Name
Pin
Type
Connecte
d to/
from
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
Drive
req. mA
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
Reset
State
NoteExplanation
H1VCC_IOIO VCC in
3325c10
L4MCUAd7OMCU
MEMORY
L3MCUAd8OMCU
MEMORY
L2MCUAd9OMCU
MEMORY
K5MCUAd10OMCU
MEMORY
J4GNDGround
K3MCUAd11OMCU
MEMORY
K2MCUAd12OMCU
MEMORY
K1MCUAd13OMCU
MEMORY
J3MCUAd14OMCU
MEMORY
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
Power
J2MCUAd15OMCU
MEMORY
20MCU address bus
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Pin
No:
J1MCUAd16OMCU
M10VCC_CORECore VCC in
H3MCUAd17OMCU
H2MCUAd18OMCU
G4MCUAd19OMCU
G3MCUAd20OMCU
G2VCONTO
K6ExtMCUDa0I/OMCU
Pin Name
Pin
Type
Connecte
d to/
from
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
Drive
req. mA
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
20MCU address bus
2InputMCU data bus
Reset
State
NoteExplanation
3325c10
Power
K9GNDGround
L6ExtMCUDa1I/OMCU
MEMORY
M6ExtMCUDa2I/OMCU
MEMORY
N6ExtMCUDa3I/OMCU
MEMORY
L7ExtMCUDa4I/OMCU
MEMORY
M7ExtMCUDa5I/OMCU
MEMORY
N7ExtMCUDa6I/OMCU
MEMORY
N8ExtMCUDa7I/OMCU
MEMORY
M8MCUGenIODa0I/O 2InputMCU Data in
L8MCUGenIODa1I/O2 InputMCU Data in
2OutputMCU data bus
2OutputMCU data bus
2OutputMCU data bus
2OutputMCU data bus
2OutputMCU data bus
2OutputMCU data bus
2OutputMCU data bus
General purpose I/O
16-bit mode
16-bit mode
port
General purpose I/O
port
K8 MCUGenIODa2I/O 2InputMCU Data in
16-bit mode
N9MCUGenIODa3I/O 2 InputMCU Data in
16-bit mode
General purpose I/O
port
General purpose I/O
port
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Pin
No:
E10GNDGround
M9MCUGenIODa4I/O 2Input MCU Data in
L9 MCUGenIODa5I/O 2InputMCU Data in
N10MCUGenIODa6I/O2 InputMCU Data in
L10MCUGenIODa7I/O 2InputMCU Data in
M5MCURdXOMCU
G11VCC_CORECore VCC in
N5MCUWrXOMCU
Pin Name
Pin
Type
Connecte
d to/
from
MEMORY
MEMORY
Drive
req. mA
21MCU Read strobe
21MCU write strobe
Reset
State
NoteExplanation
General purpose I/O
16-bit mode
16-bit mode
16-bit mode
16-bit mode
3325c10
port
General purpose I/O
port
General purpose I/O
port
General purpose I/O
port
Power
N11ROM1SelXOMCU
ROM
M11RAMSelXOMCU
RAM
J11IRONOIR Mod21IR control
A1MCUGenIO1I/O2Input,
D8DSPXFO21External flag
K10SCVCCSpecial cell Power
K11RFClkIVCXOInputSystem clock from
K12RFClkGndInputSystem clock refer-
K13SIMCardDetXIInputSIM card detection
J10SCGNDSpecial cell Ground
D9BuzzPWMOBUZZER20Buzzer PWM control
D11LEADVCCLEAD Power
21ROM chip select
21RAM chip select
pullup
pullup
PR0201
General purpose I/O
port
VCTCXO
ence ground input
G12VibraPWMOVIBRA20Vibra PWM control
C9GNDGround
E12MCUGenIO3I/O2Input,
pullup
pullup
PR1001
General purpose I/O
port
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Pin
No:
E13MCUGenIO2I/O2Input,
J13KBLightsOUIF21
C5AccTxDataI/O4Tri- Stateexternal pul-
B6VCC_IOIO VCC in
F11HookDetIInputNon-MBUS acces-
F10HeadDetIInputHeadset detection
D6AccRxDataIInputAccessory RX data,
D5GNDGround
Pin Name
Pin
Type
Connecte
d to/
from
Drive
req. mA
Reset
State
pullup
NoteExplanation
pullup
PR1001
lup
3325c10
General purpose I/O
port
Accessory TX data,
Flash_TX
Power
sory connection
detector
interrupt
Flash_RX
G10MCUGenIO4I/O2Input,
pulldown
B5MBUSI/O2Input,
external pullup
E11VCXOPwrOCCONT21VCXO regulator con-
D13SynthPwrOCCONT20Synthesizer regula-
B7VCC_CORECore VCC in
C10GenCCO-
NTCSX
F13LEADGNDLEAD Ground
B10GenSDIOI/OCCONT,
OCCONT21Chip select to CCONT
2Input,
UIF
external
pullup/
down
pulldown
PD1001
external
pullup
3325c10
external pullup/down
depending on
how to boot
General purpose I/O
port
MBUS, Flash clock
trol
tor control
Power
Serial data in/out
A10GenSClkOCCONT,
UIF
C11SIMCardDataI/OCCONT20SIM data
J12GNDGround
B13PURXICCONTInputPower Up Reset
20Serial clock
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Pin
No:
B12CCONTIntICCONTInputCCONT interrupt
A13Clk32kICCONTInputSleep clock oscillator
D10VCC_IOIO VCC in
A12SIMCardClkOCCONT20SIM clock
B11SIMCardRstXOCCONT20SIM reset
A11SIMCardIOCOCCONT20SIM data in/out con-
D12SIMCardPwrOCCONT20SIM power control
H10LEADVCCLEAD Power
C13RxPwrO20(RX regulator control)
C12TxPwrO20(TX regulator control)
H12TestModeIInput,
Pin Name
Pin
Type
Connecte
d to/
from
Drive
req. mA
Reset
State
pulldown
NoteExplanation
input
Power
3325c10
trol
pulldown
PD0201
Test mode select
H13ExtSysResetXO20System Reset
B9PCMTxDataOCOBBA20Transmit data, DX
K7VCC_IOIO VCC in
3325c10
A9PCMRxDataICOBBAInputReceive data, RX
B8PCMDClkICOBBAInputTransmit clock, CLKX
A8PCMSClkICOBBAInputTransmit frame sync,
C6COBBAClkOCOBBA41COBBA clock, 13
A6COBBACSXCOBBACOBBA
A7COBBASDCOBBACOBBA
C7IDataCOBBACOBBA
D7QDataCOBBACOBBA
G1VCC_CORECore VCC in
3325c10
C1DSPGenOut3ORF20DSP general purpose
Power
FSX
MHz
Power
output
B4DSPGenOut2ORF20DSP general purpose
output
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Pin
No:
A4DSPGenOut1ORF20DSP general purpose
A5DSPGenOut0OCRFU20DSP general purpose
A3FrACtrlORF20RF front amplifier
B3SynthEnaOHAGAR20Synthesizer data
B1SynthClkOHAGAR20Synthesizer clock
B2SynthDataOHAGAR20Synthesizer data
A2TxPAOHAGAR20Power amplifier con-
Pin Name
Pin
Type
Connecte
d to/
from
Drive
req. mA
Reset
State
NoteExplanation
output
output
control
enable
trol
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Memories
MAD memory configuration
The MAD2WD1 used in NSB-7 contains 16 kWords RAM, and 80 kWords ROM memory.
Memory
The MCU program code resides in an external flash program memory, which size is
16Mbits (1024k x 16bit). The MCU work (data) memory size is 2048 kbits (256k x 16bit).
Flash and SRAM memory chips are packed in same combo memory package.
The BusController (BUSC) section in the MAD decodes the chip select signals for the
external memory devices and the system logic. BUSC controls internal and external bus
drivers and multiplexers connected to the MCU data bus. The MCU address space is
divided into access areas with separate chip select signals. BUSC supports a programmable number of wait states for each memory range.
Program and Data Memory
The MCU program code resides in the program memory. The program memory is 16Mbits
(1024k x 16bit) Flash memory.
The flash memory has a power down pin that should be kept low, during the power up
phase of the flash to ensure that the device is powered up in the correct state, read only.
The power down pin is utilized in the system sleep mode by connecting the ExtSysResetX
to the flash power down pin to minimize the flash power consumption during the sleep.
Nonvolatile data memory is implemented with program (Flash) memory. Special EEPROM
emulation (EEEMmu) software is utilized.
Work Memory
The work memory is a static RAM of size 2096k (256k x 16). The memory contents are
lost when the baseband voltage is switched off. All retained data must be stored into the
data memory when the phone is powered down.
MCU Memory Requirements
DeviceOrganisationAccess Time nsWait States UsedRemarks
FLASH1024kx161201uBGA 48
SRAM256kx161201uBGA 48
MCU Memory Map
MAD2 supports maximum of 4GB internal and 4MB external address space. External
memories use address lines MCUAd0 to MCUAd21 and 8-bit/16-bit databus. The BUSC
bus controller supports 8- and 16-bit access for byte, double byte, word and double word
data. Access wait states (0, 1 or 2) and used databus width can be selected separately for
each memory block.
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Flash Programming
The phone has to be connected to the flash loading adapter so that supply voltage for
the phone and data transmission lines can be supplied from/to the adapter. When
adapter switches supply voltage to the phone, the program execution starts from the
BOOT ROM and the MCU investigates in the early start-up sequence if the flash prommer
is connected. This is done by checking the status of the MBUS-line. Normally this line is
high but when the flash prommer is connected the line is forced low by the prommer.
The flash prommer serial data receive line is in receive mode waiting for an acknowledgement from the phone. The data transmit line from the baseband to the prommer is
initially high. When the baseband has recognized the flash prommer, the TX-line is pulled
low. This acknowledgement is used to start to toggle MBUS (FCLK) line three times in
order that MAD2 gets initialized. This must be happened within 15 ms after TX line is
pulled low. After that the data transfer of the first two bytes from the flash prommer to
the baseband on the RX-line must be done within 1 ms.
When MAD2 has received the secondary boot byte count information, it forces TX line
high. Now, the secondary boot code must be sent to the phone within 10 ms per 16 bit
word. If these time-out values are exceeded, the MCU (MAD2) starts normal code execution from flash. After this, the timing between the phone and the flash prommer is handled with dummy bites.
A 5V programming voltage is supplied inside the transceiver from the battery voltage
with a switch mode regulator (5V/30mA) of the CCONT. The 5V is connected to VPP pin
of the flash.
CharacteristicsMinTypMaxUnit
Time from boot indication to
MAD2 initialization sequence
Time from MAD2 initialization
sequence to byte length information
Time from byte length information
to end of secondary boot code
loading.
15 ms
1 ms
10 per16 bit
word
ms
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CCONT pin
(PurX)
MAD pin
(FCLK (MBUS))
MAD pin 109
(FRX (FRxData))
MAD pin
(FTX (FTxData))
SRAM D221 (Chip Sel)
FLASH D210 (Chip Sel)
COBBA GJP
CCONT pin
(PurX)
MAD pin
(FCLK (MBUS))
MAD pin
(FRX (FRxData))
MAD pin
(FTX (FTxData))
Figure 12: Flash Programming Sequence
COBBA GJP ASIC provides an interface between the baseband and the RF-circuitry.
COBBA performs analogue to digital conversion of the receive signal. For transmit path
COBBA performs digital to analogue conversion of the transmit amplifier power control
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ramp and the in-phase and quadrature signals. A slow speed digital to analogue converter will provide automatic frequency control (AFC).
COBBA is at any time connected to MAD asic with two interfaces, one for transferring TX
and RX data between MAD and COBBA and one for transferring codec RX/TX samples.
Real time clock
Requirements for a real time clock implementation are a basic clock (hours and minutes),
a calender and a timer with alarm and power on/off -function and miscellaneous calls.
The RTC will contain only the time base and the alarm timer but all other functions (e.g.
calendar) will be implemented with the MCU software. The RTC needs a power backup to
keep the clock running when the phone battery is disconnected. The backup power is
supplied from a rechargable Li-ion battery that can keep the clock running some ten
minutes. If the backup has expired, the RTC clock restarts after the main battery is connected. The CCONT keeps MCU in reset until the 32kHz source is settled (1s max).
The CCONT is an ideal place for an integrated real time clock as the asic already contains
the power up/down functions and a sleep control with the 32kHz sleep clock, which is
running always when the phone battery is connected. This sleep clock is used for a time
source to a RTC block.
RTC backup battery charging
CHAPS has a current limited voltage regulator for charging a backup battery. The regulator derives its power from VOUT so that charging can take place without the need to
connect a charger. The backup battery is only used to provide power to a real time clock
when VOUT is not present so it is important that power to the charging circuitry is
derived from VOUT and that the charging circuitry does not present a load to the backup
battery when VOUT is not present.
It should not be possible for charging current to flow from the backup battery into VOUT
if VOUT happens to be lower than VBACK. Charging current will gradually diminish as the
backup battery voltage reaches that of the regulation voltage.
Security
The phone flash program and IMEI code are software protected using an external security device that is connected between the phone and a PC. The security device uses the
phone given IMEI number, the software version number and a 24bit hardware random
serial number that is read from the COBBA and calculates a flash authority identification
number that is stored into the phone (emulated) EEPROM.
Baseband EMC Strategy
The baseband EMC strategy is divided into electrical and mechanical items. As electrical
guide lines, clocks and high speed signals should be routed in inner layers and away from
the PCB edges. Clock signals distributed to other circuits should have series resistors
incorporated to reduce rise times and reflections. Slew rate controlled buffers should be
used on custom components wherever possible to reduce the EMC produced by the circuit. Separate power supplies for digital, analog and rf-blocks should be used as much as
possible. Baseband and RF supply power rails should be isolated from each other by
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means of inductors in the power supply rail to prevent high frequency components produced on the baseband power supply rail to spread out over the RF power supply plane.
This might be required to avoid interference from digital circuits to affect the performance of RF section.
All external connectors and connection must be filtered using RC or LC networks to prevent the high frequency components from entering connection cables that then will act
as antennas. The amount of this type of EMC component is in straight relation to the
amount of external connections. The type of network and amount of components to be
used is determined by the AC and DC impedance characteristic of that particular signal.
Low impedance signals requires LC network while medium impedance level signals, input
signals at moderate band width can use RC networks.
The EMC protection should also prevent external or internal signals to cause interference
to baseband and in particular to audio signals. Internal interference is generated by the
transmitter burst frequency and the switchmode charging. The transmitter burst frequency interference is likely to cause noise to both microphone and earphone signals.
The transmitter RF interference is likely to cause more problems in the microphone circuitry than in the earphone circuitry since the earpiece is a low impedance dynamic type.
As mechanical guide lines, the baseband and RF sections should be isolated from each
other using EMC shielding, which suppresses radiated interferences. The transmitter
burst frequency can also generate mechanical vibrations that can be picked up by the
microphone if it is not properly isolated from the chassis using rubber or some other soft
material. Connection wires to internal microphone and earphone should be as short as
possible to reduce the interference caused by internal signals.
ESD protection has to be implemented on each external connection that is accessible
during normal operation of the phone.
Baseband Testing
The MCU software enters a local mode at startup if a dummy battery is attached and the
battery temperature value is high enough. This means that the fixed resistor on the
BTEMP line must correspond to a temperature higher than +85 C. In the local mode the
baseband can be controlled through MBUS or FBUS connections by a PC-locals software.
Baseband internal connections are tested with self tests if possible. By connecting MAD2
pin ROW5 to ground, MAD2 pins are toggled as a daisy chain, which can be used for
detecting short circuits in MAD2 pins. Test pads will be placed on engine pcb for service
and production trouble shooting purposes in some supply voltage and signal lines.
Alignments
Within alignment those parameters are adjusted, that cannot be set accurate enough by
design, because of component tolerances.
Due to use of 5% resistor values, the channels of the CCONT A/D converters need to be
aligned in the production phase.
Within battery voltage VBATT tuning the MCU software reads the A/D reading from
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CCONT at 3.6V and stores this reading to EEPROM memory as a reference point. Another
reference point is created by assuming that when the input voltage is zero, A/D reading
is also zero. Now the slope is known and A/D readings can be calibrated. Calibration is
included in VBATT A/D reading task.
Battery charging voltage VCHAR and current ICHAR are calibrated using one test setting.
Test jig in production line must have a connection to battery terminals. ICHAR is
adjusted to 500mA and VCHAR to 8.4V with appropriate load connected to the battery
terminals.
BTEMP is calibrated with 47kohm resistor.
BSI is calibrated with 22kohm resistor.
Baseband Startup for Testing
When an unprogrammed module is powered up the first time the MCU starts from the
boot rom inside the MAD2. The MBUS line is to be kept low to inform the MCU that the
flash prommer is connected and the MCU should stop after the boot and wait for a
download code.
When the flash programming is performed successfully the MCU switches to flash prom
software. If the baseband is powered up for the first time the MCU will remain in local
mode as the factory set has not been executed. To allow re-programming of working
modules the MCU is at startup forced into local mode by connecting the BSI and BTEMP
signals to ground using specified resistors.
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RF Module
This RF module takes care of all RF functions of GSM1900 single band engine. RF circuitry is on one side of a 8 layer transceiver PCB. PCB area for the RF circuitry is about 15
cm2. RF design is based on the first dualband direct conversion RF-IC ”Hagar”. So there is
no intermediate frequency. That means the number of components is lower than before
and there shall be much less interference problems than previously.
Shielding
EMC emissions are taken care by using metallized plastic shield which screens the whole
transceiver. Internal screening is realized by isolated partitions, these are the PA and the
VCO blocks. The baseband circuitry is located on the same side of pcb.
Minimum height on RF board is 1.8 mm and a little space has been reserved for higher
components (2.5 mm). In addition there is a possibility to put some higher (max. 2.0 mm)
components in low area (recesses can be made in plastic shield). Heat generated by the
circuitry will be conducted out via the PCB ground planes and metal shields.
Environmental Specifications
Normal and Extreme voltages
Lithium-Ion battery (1cell)
Nominal Voltage4.1 V
Lower Extreme Voltage3.45 V (0.85 x 4.1 V = 3.49 V, "the MS shall inhibit
Higher Extreme VoltageNominal
Absolute Maximum Voltage5.1 V
Software Cut-off Voltage3.1 V
Temperature Conditions
RF Specifications are met within
all RF transmissions when the power supply
voltage is below the manufacturer declared
shut-down voltage")
-10...+55 deg C ambient temperature.
Storage temperature range is
-40...+70 deg C.
Humidity
Relative humidity range is 5... 95%.
This module is not protected against water. Condensation or splashed water
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might cause malfunction momentary. Long term wetness will cause permanent
damage (corrosion etc.).
Vibration
All requirements must be met in following vibration conditions:
Freq.ASD (Acceleration Spectral Density) random vibration
10...100 Hz3 m2/s3 (0.0132 g2/Hz)
100...500 Hz-3 dB/Octave
ESD Strength
Module should withstand an electrostatic discharge from 150 pF capacitor
via 300 ohm resistor. Conducted discharge into antenna and battery connector
is 8 kV (>10 discharges) and air contact 15 kV (>10 discharges).
Main Technical Specifications
Maximum Ratings
ParameterRating
Normal battery voltage, idle mode3.6 V
Regulated supply voltage2.8 +/- 3% V
Voltage reference1.5 +/- 1.5% V
Operating temperature range-10...+55 deg. C
Absolute maximum voltage5.1 V
Software cut-off voltage3.1 V
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RF Frequency Plan
Figure 13: RF Frequency Plan
DC Characteristics
Regulators
Transceiver has a multi function power management IC at baseband section, which contains among other functions also 7 pcs of 2.8 V regulators. All regulators can be controlled individually with 2.8 V logic directly or through control register. In GSM direct
controls are used to get fast switching because the regulators are used to enable RF
functions.
VREF_2 from CCONT IC and RXREF from COBBA IC are used as the reference voltages for
HAGAR RF-IC, VREF_2 (1.5V) for bias reference and RXREF (1.2V) for RX ADC’s reference.
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Control Signals
VXCO
PWR
LLLLL<10 uALeakage current
HHLLL28 mASynthesizer
HHHLL81 mARX active
HHLHL138 mATX active except
HHLHH1700 mATX active, full
SYNTH
PWR
RX
PWR
TX
PWR
TXP
Typ.curre
nt cons.
Notes
(PA)
PA
power
All regulators are connected to HAGAR and directed with SYNTPWR. Different modes are
switched on via serial bus.
All control signals are coming from MAD2 (2.8 V logic signals).
List of the needed supply voltages:
Volt. sourceName of the supplyLoad
V5VVCPPLL charge pump, VCO
VR5VTXTX modulator
VR1VXOVCTCXO
VR2VRXHAGAR IC
(LNA2+mixer+DTOS)
VR4VSYN_2HAGAR IC (div+LO-buff+prescaler)
VR3VSYN_1LNA + HAGAR (Vdd_bb)
VR6COBBA analog parts
VREF_2ref. voltage for HAGAR
RXREF (COBBA)ref. voltage for HAGAR
TXVGSM (Hagar)Ant. sw. GSM
TXVDCS (Hagar)Ant. sw. DCS
TXVDET (Hagar)Power detector
VbattVBATTRF regulators in CCONT, PA
In-band (1910…2010 MHz); maximum of twelve occurrences are permitted.
Out-of-band; maximum of 24 occurrences are permitted.
AM Suppression Requirements
Frequency BandMinimum
[f – fo] >= 6 MHz *-29 dBm
Typical /
Nominal
MaximumUnit / Notes
* Interferer is TDMA signal, pseudo random GMSK modulated at integer multiple of 200
kHz distance from wanted signal.
Interferer is at least 2 channels separated from any identified spurious response.
Interferer is active one time slot and delayed in time between 61 and 86 bit periods relative to the wanted signal bursts. It’s also synchronized.
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Sensitivity, Inter modulation, Spurious Rejection and Emissions
ParameterMinimum
Reference Sensitivity Level -102dBm
Inter modulation Rejection50dB, fo=2*f1-f2, [f2-
Spurious Response Rejection56 *dB
Spurious Emissions -57 dBm, 9 kHz - 1 GHz
Typical /
Nominal
MaximumUnit / Notes
f1]=800 kHz
-47dBm, 1 GHz - 12.75
GHz
* 12 occurrences allowed in band 1910-2010 MHz/test ch. Rest of the occurrences have
to meet blocking requirements. Max. 24 spurious responses are allowed in combined
band 100 kHz-1830 MHz and 2010 MHz-12.75 GHz, other responses have to be in the
limits of blocking specification.
Reference Interference level
ParameterMinimum
Typical /
Nominal
MaximumUnit / Notes
Cochannel Interference Ratio 9 dB
Adjacent (200 kHz) Interference
Ratio
Adjacent (400 kHz) Interference
Ratio
Adjacent (600 kHz) Interference
Ratio
-9 dB
-41 dB
-49 dB
Interferer is modulated with random GMSK. Interferer and wanted signals are faded.
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RF Block Diagram
Architecture contains RF-IC (“Hagar”), PA module, VCO module, VCTCXO module and discrete LNA stage.
TXIP
TXIN
TXQP
AFC
RXREF
1.2 V
VREF_2
Q
I
1.5 V
SERIAL CTRL
BUS
TXC
TXQN
TXP
SHF
VCO
PLL
26 MH z
BIAS
f
f/2
f/2
Hagar
f
Figure 15: RF Block Diagram
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Frequency synthesizer
VCO frequency is locked by PLL into a stable frequency source, which is a VCTCXO module (Voltage Controlled Temperature Compensated Crystal Oscillator). VCTCXO is running
at 26 MHz. Temperature effect is controlled by AFC (Automatic Frequency Control) voltage. VCTCXO is locked to a frequency of base station. AFC is generated by baseband with
a 11 bit conventional DAC in COBBA asic.
PLL is located in HAGAR RF-IC and is controlled via serial bus by COBBA (in baseband).
There is a 64/65 (P/P+1) pre-scaler, an N- and A-divider, a reference divider, a phase
detector and a charge pump for an external loop filter. SHF (Super High Frequency) local
signal, generated by a VCO module (Voltage Controlled Oscillator), is fed to the prescaler. The pre-scaler is a dual modulus divider. Output of the pre-scaler is fed to the Nand A-divider which generates an input to the phase detector. The phase detector compares this signal to a reference signal (400kHz) which is divided by the reference divider
from VCTCXO output. Output of the phase detector is connected to the charge pump
which charges or discharges an integrator capacitor in the loop filter depending on a
phase of measured frequency compared to the reference frequency.
The loop filter filters out pulses and generates a DC control voltage to the VCO. The loop
filter defines a step response of PLL (Phase Locked Loop), i.e. Settling Time, and effects to
a stability of the loop - that’s why the integrator capacitor has got a resistor for phase
compensation. Other filter components are for sideband rejection. Dividers are controlled
via serial bus. SDATA is for data, SCLK is a serial clock for the bus and SENA1 is a latch
enable which stores new data into the dividers.
LO signal is generated by a SHF VCO module. The VCO has double frequency in GSM1900
compared to actual RF channel frequency. The LO signal is divided by two in HAGAR.
freq.
R
f
ref
f_out /
M
PHASE
DET.
CHARGE
PUMP
Kd
reference
FC-controlled
LP
f_out
VCO
Kvco
M
M = A(P+1) + (N-A)P=
=NP+A
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Figure 16: Phase Locked Loop
Receiver
Receiver is a direct conversion linear receiver. Received RF signal from antenna is fed via
Antenna Switch to the 1st RX SAW filter and a discrete LNA (Low Noise Amplifier). Gain
selection control of the LNA comes from HAGAR IC. Gain step is activated when RF level
in antenna is about -40 dBm.
After the LNA amplified signal (with low noise level) is fed to a bandpass filter (the 2nd
RX SAW filter). The RX filters define how good are the blocking characteristics against
spurious signals outside the receive band and the protection against spurious responses.
These bandpass filtered signals are then balanced with baluns. Differential RX signal is
amplified and mixed directly down to a BB frequency in HAGAR. Local Oscillator signal is
generated by an external VCO. The VCO signal is divided by 2. PLL and dividers are in
HAGAR IC.
From the mixer output to an ADC input RX signal is divided to I- and Q-signals. Accurate
phasing is generated by LO dividers. After the mixer DTOS amplifiers convert the differential signals to single ended. DTOS has two gain stages. The first one has constant gain
of 12dB and 85kHz cut off frequency. The gain of second stage is controlled by control
signal g10. If g10 is high (1) the gain is 6dB and if g10 is low (0) the gain is -4dB.
The active channel filters in HAGAR IC provides selectivity for channels (-3dB @ +/-100
kHz typ.). Integrated baseband filter is an active RC filter with two off-chip capacitors.
Long RC time constant needed in the channel selection filter of direct conversion
receiver is produced by large off-chip capacitors because the impedance levels could not
be increased due to noise specifications. The baseband filter consists of two stages, DTOS
and BIQUAD. DTOS is a differential to single-ended converter having 8dB or 18dB gain.
BIQUAD is a modified Sallen-Key Biquad.
Integrated resistors and capacitors are tunable. These are controlled by a digital control
word. The correct control words which compensate process variation of the integrated
resistors and capacitors and tolerance of the off-chip capacitors are found by a calibration circuit.
The next stage in receiver chain is an AGC amplifier - also integrated in HAGAR. The AGC
has a digital gain control via serial bus from COBBA IC. The AGC stage provides gain control range of 40 dB (10 dB steps) for the receiver and also necessary DC compensation.
The 10 dB AGC step is implemented by DTOS stages.
The DC compensation is made during DCN1 and DCN2 operations (controlled via serial
bus). DCN1 is carried out by charging large external capacitors in the AGC stages to a
voltage which cause a zero dc-offset. DCN2 sets the signal offset to a constant value
(RXREF 1.2 V). The RXREF signal (from COBBA GJP) is used as a zero level to RX ADCs.
Single ended filtered I/Q-signal is finally fed to the ADCs of COBBA. The input level for
ADC is 1.4 Vpp max.
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Transmitter
Transmitter chain consists of a final frequency IQ-modulator, a single band power amplifier and a power control loop.
I- and Q-signals are generated by baseband in COBBA asic. After post filtering (RC network) the signals are modulated by IQ-modulator in HAGAR IC. The LO signal for modulator is generated by a VCO and is divided by 2. After modulator the TX signal is amplified
and buffered. HAGAR TX output level is +3 dBm minimum.
Next the TX signal is converted to single ended by discrete baluns. The final amplification
is realized by the power amplifier (PA). It has a 50 ohm input and output. Right output
power is controlled by a power control loop. The PA is able to generate over 1 W output
power (0 dBm input level). The gain control range is over 35 dB to get desired power levels and power ramping up/down.
Harmonics generated by the nonlinear PA are filtered out by the diplexer inside the
antenna switch module.
Power control circuitry consists of a discrete power detector and an error amplifier (in
HAGAR). There is a directional coupler between the PA output and the antenna switch.
The directional coupler takes a sample from the TX power with a certain ratio. The sampled signal is rectified by a schottky-diode to produce a DC signal (after filtering). The
detected voltage is compared by the error amplifier in HAGAR to TXC voltage which is
generated by a DA converter in COBBA. The TXC has got a raised cosine form (cos4 function) which reduces switching transients when pulsing the TX power up and down.
Because dynamic range of the detector is not wide enough to control the TX power
(actually the RF output voltage) over the whole range there is a control named TXP to
work under the detected levels. Burst is enabled and set to rise with TXP until the output
level is high enough, i.e. when the feedback loop works. The loop controls the TX output
to rise to a wanted output level. The burst has got a template of TXC ramp. Because the
feedback loops can be unstable the loop is compensated by a dominating pole. The pole
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decreases gain at high frequencies to insure phase margins high enough.
PADIR.COUPLER
RF_OUT
DETECTOR
K
cp
R1
=-R1/R2
K
det
R2
Figure 17: Power Control Loop Diagram
K
ERROR
AMPLIFIER
RF_IN
K
PA
R
DOMINATING
C
POLE
TXC
AGC strategy
AGC amplifier is used to maintain output level of the receiver in certain range. AGC has
to be set before each received burst. This is called pre-monitoring. Receiver is switched
on roughly 280 µs before the burst begins. DSP measures received signal level and
adjusts AGC amplifier via serial bus from COBBA GJP.
There is a 50 dB accurate gain control (10 dB steps) and one larger step (~30 dB) in LNA.
LNA AGC gain step size depends on a channel with some amount.
RSSI must be measured accurately on range of -48...-110 dBm. Above -48 dBm level MS
reports to base station the same reading.
Production calibration is done by two RF levels. The LNA gain step is not calibrated.
AFC function
AFC is used to lock the transceivers clock to the frequency of base station. AFC voltage is
generated by COBBA asic with a 11 bit DA converter. In the AFC control line a RC filter is
used to reduce noise coming from the converter. Settling time requirement for the RC
network comes from signalling, i.e. how often PSW (Pure Sine Wave) slots occur. The
PSW is repeated in every 10th frame. It means there is a PSW every 46 ms. The AFC
tracks base station frequency continuously. This way the transceiver gets a stable frequency. Temperature does not affect to VCTCXO frequency very fast.
Settling time requirement comes also from the start-up time allowed. When the trans-
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ceiver is in sleep mode and ”wakes up" to a receive mode there is only ca. 5 ms for the
AFC voltage to settle. When the first burst comes in the system clock has to be settled
with +/- 0.1 ppm frequency accuracy. The VCTCXO module requires also 5 ms to settle to
the final frequency. Amplitude rises to full swing in 1... 2 ms. Because the frequency settling time is higher this oscillator must be powered up early enough.
DC Compensation
DC compensation is done during DCN1 and DCN2 operations (controlled via serial bus).
DCN1 is carried out by charging large external capacitors in AGC stages to a voltage
which causes a zero dc offset. DCN2 sets the signal offset to a constant value (RXREF 1.2
V).
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Parts List of RB9 (EDMS Issue 5.3) Code: 0201512
ITEMCODEDESCRIPTIONVALUETYPE
R1001430826Chip resistor680 k5 % 0.063 W 0402
R1011430804Chip resistor100 k5 % 0.063 W 0402
R1021430796Chip resistor47 k5 % 0.063 W 0402
R1031430770Chip resistor4.7 k5 % 0.063 W 0402
R1041430796Chip resistor47 k5 % 0.063 W 0402
R1051430754Chip resistor1.0 k5 % 0.063 W 0402
R1091620017Res network 0w06 2x100r j04040404
R1101430826Chip resistor680 k5 % 0.063 W 0402
R1111430820Chip resistor470 k5 % 0.063 W 0402
R1181430778Chip resistor10 k5 % 0.063 W 0402
R1201620025Res network 0w06 2x100k j04040404
R1221620019Res network 0w06 2x10k j04040404
R1241620017Res network 0w06 2x100r j04040404
R1281430718Chip resistor47 5 % 0.063 W 0402
R1311419003Chip resistor0.22 5 % 1210
R1541430325Chip resistor2.2 M5 % 0.063 W 0603
R2011430812Chip resistor220 k5 % 0.063 W 0402
R2021430804Chip resistor100 k5 % 0.063 W 0402
R2031430770Chip resistor4.7 k5 % 0.063 W 0402
R2051430762Chip resistor2.2 k5 % 0.063 W 0402
R2061430762Chip resistor2.2 k5 % 0.063 W 0402
R2071430726Chip resistor1005 % 0.063 W 0402
R2081430726Chip resistor100 5 % 0.063 W 0402
R2091825021Chip varistor vwm14v vc46v04020402
R2101825021Chip varistor vwm14v vc46v04020402
R2111430754Chip resistor1.0 k5 % 0.063 W 0402
R2151620023Res network 0w06 2x47k j04040404
R2521430754Chip resistor1.0 k5 % 0.063 W 0402
R2541430760Chip resistor1.8 k5 % 0.063 W 0402
R2561430718Chip resistor47 5 % 0.063 W 0402
R2571430718Chip resistor47 5 % 0.063 W 0402
R2581430746Chip resistor560 5 % 0.063 W 0402
R2601430744Chip resistor470 5 % 0.063 W 0402
R2611430726Chip resistor100 5 % 0.063 W 0402
R2621825021Chip varistor vwm14v vc46v04020402
R2631825021Chip varistor vwm14v vc46v04020402
R2661430796Chip resistor47 k5 % 0.063 W 0402
R2671430762Chip resistor2.2 k5 % 0.063 W 0402
R2681430744Chip resistor470 5 % 0.063 W 0402
R2691620025Res network 0w06 2x100k j04040404
R2701430792Chip resistor33 k5 % 0.063 W 0402
R2721430804Chip resistor100 k5 % 0.063 W 0402
R2731430792Chip resistor33 k5 % 0.063 W 0402
R2741430812Chip resistor220 k5 % 0.063 W 0402
R2751620105Res network 0w06 2x2k2 j04040404
R2771620025Res network 0w06 2x100k j04040404
R3101430778Chip resistor10 k5 % 0.063 W 0402
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R3111430778Chip resistor10 k5 % 0.063 W 0402
R3501430155Chip resistor15 5 % 0.1 W 0603
R3511430155Chip resistor15 5 % 0.1 W 0603
R3521430155Chip resistor15 5 % 0.1 W 0603
R3531430155Chip resistor15 5 % 0.1 W 0603
R3541825021Chip varistor vwm14v vc46v04020402
R3711430137Chip resistor1.0 k1 % 0.063 W 0402
R3721430137Chip resistor1.0 k1 % 0.063 W 0402
R3731430137Chip resistor1.0 k1 % 0.063 W 0402
R3741430137Chip resistor1.0 k1 % 0.063 W 0402
R4031430702Chip resistor12 5 % 0.063 W 0402
R4041430702Chip resistor12 5 % 0.063 W 0402
R5101620003Res network 0w03 4x100r j08040804
R5301620019Res network 0w06 2x10k j04040404
R5321430832Chip resistor2.7 k5 % 0.063 W 0402
R5331430778Chip resistor10 k5 % 0.063 W 0402
R5411620033Res network 0w06 2x5k6 j04040404
R5461620033Res network 0w06 2x5k6 j04040404
R5631430187Chip resistor47 k1 % 0.063 W 0402
R5641430746Chip resistor560 5 % 0.063 W 0402
R5651430770Chip resistor4.7 k5 % 0.063 W 0402
R6141430728Chip resistor1205 % 0.063 W 0402
R6401430738Chip resistor270 5 % 0.063 W 0402
R6431430832Chip resistor2.7 k5 % 0.063 W 0402
R6451430832Chip resistor2.7 k5 % 0.063 W 0402
R6721430728Chip resistor1205 % 0.063 W 0402
R7321430746Chip resistor560 5 % 0.063 W 0402
R7371430744Chip resistor470 5 % 0.063 W 0402
R7381430706Chip resistor155 % 0.063 W 0402
R7401430730Chip resistor150 5 % 0.063 W 0402
R7411430730Chip resistor150 5 % 0.063 W 0402
R7431430690Chip jumper0402
R7441430710Chip resistor22 5 % 0.063 W 0402
R7541430720Chip resistor56 5 % 0.063 W 0402
R7631430774Chip resistor6.8 k5 % 0.063 W 0402
R7641430776Chip resistor8.2 k5 % 0.063 W 0402
R7901430788Chip resistor22 k5 % 0.063 W 0402
R7911430770Chip resistor4.7 k5 % 0.063 W 0402
R7921430780Chip resistor12 k5 % 0.063 W 0402
R8001430778Chip resistor10 k5 % 0.063 W 0402
R8011430774Chip resistor6.8 k5 % 0.063 W 0402
R8021430764Chip resistor3.3 k5 % 0.063 W 0402
R8051620505Res network 0w042DB ATT 0404
R8061430738Chip resistor2705 % 0.063 W 0402
R8071430738Chip resistor2705 % 0.063 W 0402
R8291430752Chip resistor8205 % 0.063 W 0402
R8301430762Chip resistor2.2 k5 % 0.063 W 0402
R8311430718Chip resistor47 5 % 0.063 W 0402
R8321430788Chip resistor22 k5 % 0.063 W 0402
R8331430762Chip resistor2.2 k5 % 0.063 W 0402
R8341430812Chip resistor220 k5 % 0.063 W 0402
C1012320548Ceramic cap.33 p5 % 50 V 0402
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PAMS Technical DocumentationSystem Module
C1022320538Ceramic cap.12 p5 % 50 V 0402
C1032312411Ceramic cap.1.0 u20 % 25 V 1206
C1042320783Ceramic cap.33 n10 % 10 V 0402
C1052611719Tantalum cap.10 u 20 % 10 V 2.0x1.35x1.35
C1062320481Ceramic cap.5R 1 u10 % 0603
C1072320481Ceramic cap.5R 1 u10 % 0603
C1082312401Ceramic cap.1.0 u10 % 10 V 0805
C1132320508Ceramic cap.1.0 p0.25 % 50 V 0402
C1202320778Ceramic cap.10 n10 % 16 V 0402
C1212320778Ceramic cap.10 n10 % 16 V 0402
C1272320805Ceramic cap.100 n10 % 10 V 0402
C1282312401Ceramic cap.1.0 u10 % 10 V 0805
C1292312401Ceramic cap.1.0 u10 % 10 V 0805
C1312611719Tantalum cap.10 u 20 % 10 V 2.0x1.35x1.35
C1322611741Tantalum cap.4.7 u 20 % 10 V 2.0x1.3x1.2
C1332320481Ceramic cap.5R 1 u10 % 0603
C1402320481Ceramic cap.5R 1 u10 % 0603
C1422611719Tantalum cap.10 u 20 % 10 V 2.0x1.35x1.35
C1502320481Ceramic cap.5R 1 u10 % 0603
C1512320481Ceramic cap.5R 1 u10 % 0603
C1522320481Ceramic cap.5R 1 u10 % 0603
C1532320481Ceramic cap.5R 1 u10 % 0603
C1542320481Ceramic cap.5R 1 u10 % 0603
C1632320602Ceramic cap.4.7 p0.25 % 50 V 0402
C1652611737Tantalum cap.68 u 20 % 16 V 7.3x4.3x2.0
C1692320602Ceramic cap.4.7 p0.25 % 50 V 0402
C2002320544Ceramic cap.22 p5 % 50 V 0402
C2012320783Ceramic cap.33 n10 % 10 V 0402
C2032320778Ceramic cap.10 n10 % 16 V 0402
C2042320778Ceramic cap.10 n10 % 16 V 0402
C2052610203Tantalum cap.2.2 u 20 % 10 V 2.0x1.3x1.2
C2062320778Ceramic cap.10 n10 % 16 V 0402
C2072320778Ceramic cap.10 n10 % 16 V 0402
C2082320778Ceramic cap.10 n10 % 16 V 0402
C2092320778Ceramic cap.10 n10 % 16 V 0402
C2112320778Ceramic cap.10 n10 % 16 V 0402
C2122320779Ceramic cap.100 n10 % 16 V 0603
C2132320744Ceramic cap.1.0 n10 % 50 V 0402
C2212320778Ceramic cap.10 n10 % 16 V 0402
C2312320778Ceramic cap.10 n10 % 16 V 0402
C2412320778Ceramic cap.10 n10 % 16 V 0402
C2472320778Ceramic cap.10 n10 % 16 V 0402
C2482320481Ceramic cap.5R 1 u10 % 0603
C2492320778Ceramic cap.10 n10 % 16 V 0402
C2512320778Ceramic cap.10 n10 % 16 V 0402
C2532320783Ceramic cap.33 n10 % 10 V 0402
C2572320783Ceramic cap.33 n10 % 10 V 0402
C2582320783Ceramic cap.33 n10 % 10 V 0402
C2592320783Ceramic cap.33 n10 % 10 V 0402
C2602320481Ceramic cap.5R 1 u10 % 0603
C2622320783Ceramic cap.33 n10 % 10 V 0402
C2632320783Ceramic cap.33 n10 % 10 V 0402
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C2682320481Ceramic cap.5R 1 u10 % 0603
C2692320544Ceramic cap.22 p5 % 50 V 0402
C2702610207Tantalum cap.10 u20 % 2.0x1.3x1.2
C2762320481Ceramic cap.5R 1 u10 % 0603
C2912320546Ceramic cap.27 p5 % 50 V 0402
C2922320546Ceramic cap.27 p5 % 50 V 0402
C2932320546Ceramic cap.27 p5 % 50 V 0402
C2962610207Tantalum cap.10 u20 % 2.0x1.3x1.2
C2972610207Tantalum cap.10 u20 % 2.0x1.3x1.2
C2992320546Ceramic cap.27 p5 % 50 V 0402
C3032320744Ceramic cap.1.0 n10 % 50 V 0402
C3042320744Ceramic cap.1.0 n10 % 50 V 0402
C3062320598Ceramic cap.3.9 n5 % 50 V 0402
C3072320598Ceramic cap.3.9 n5 % 50 V 0402
C3102312401Ceramic cap.1.0 u10 % 10 V 0805
C3302320481Ceramic cap.5R 1 u10 % 0603
C3312320779Ceramic cap.100 n10 % 16 V 0603
C3422320560Ceramic cap.100 p5 % 50 V 0402
C3712320564Ceramic cap.150 p5 % 50 V 0402
C3722320564Ceramic cap.150 p5 % 50 V 0402
C3732320564Ceramic cap.150 p5 % 50 V 0402
C4002320481Ceramic cap.5R 1 u10 % 0603
C4012320805Ceramic cap.100 n10 % 10 V 0402
C4052320544Ceramic cap.22 p5 % 50 V 0402
C4062320805Ceramic cap.100 n10 % 10 V 0402
C5102320135Ceramic cap.150 n10 % 10 V 0603
C5112320135Ceramic cap.150 n10 % 10 V 0603
C5122320135Ceramic cap.150 n10 % 10 V 0603
C5132320135Ceramic cap.150 n10 % 10 V 0603
C5202320485Ceramic cap.470 p5 % 50 V 0603
C5212320485Ceramic cap.470 p5 % 50 V 0603
C5222320485Ceramic cap.470 p5 % 50 V 0603
C5232320485Ceramic cap.470 p5 % 50 V 0603
C5302320631Ceramic cap.180 p5 % 25 V 0402
C5312320631Ceramic cap.180 p5 % 25 V 0402
C5322320781Ceramic cap.47 n20 % 16 V 0603
C5332320781Ceramic cap.47 n20 % 16 V 0603
C5342320783Ceramic cap.33 n10 % 10 V 0402
C5352320546Ceramic cap.27 p5 % 50 V 0402
C5402320556Ceramic cap.68 p5 % 50 V 0402
C5412320556Ceramic cap.68 p5 % 50 V 0402
C5502320598Ceramic cap.3.9 n5 % 50 V 0402
C5572320554Ceramic cap.56 p5 % 50 V 0402
C5602320548Ceramic cap.33 p5 % 50 V 0402
C5612320778Ceramic cap.10 n10 % 16 V 0402
C5622320546Ceramic cap.27 p5 % 50 V 0402
C5642320783Ceramic cap.33 n10 % 10 V 0402
C6122320564Ceramic cap.150 p5 % 50 V 0402
C6212320805Ceramic cap.100 n10 % 10 V 0402
C6302320534Ceramic cap.8.2 p0.25 % 50 V 0402
C6312320534Ceramic cap.8.2 p0.25 % 50 V 0402
C6402320520Ceramic cap.2.2 p0.25 % 50 V 0402
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C6422320744Ceramic cap.1.0 n10 % 50 V 0402
C6432320540Ceramic cap.15 p5 % 50 V 0402
C6442320516Ceramic cap.1.5 p0.25 % 50 V 0402
C6452320540Ceramic cap.15 p5 % 50 V 0402
C7112320540Ceramic cap.15 p5 % 50 V 0402
C7122320744Ceramic cap.1.0 n10 % 50 V 0402
C7142320779Ceramic cap.100 n10 % 16 V 0603
C7172320778Ceramic cap.10 n10 % 16 V 0402
C7182320602Ceramic cap.4.7 p0.25 % 50 V 0402
C7212320536Ceramic cap.10 p5 % 50 V 0402
C7232320548Ceramic cap.33 p5 % 50 V 0402
C7312320596Ceramic cap.3.3 n5 % 50 V 0402
C7332320536Ceramic cap.10 p5 % 50 V 0402
C7342320536Ceramic cap.10 p5 % 50 V 0402
C7372320508Ceramic cap.1.0 p0.25 % 50 V 0402
C7432320540Ceramic cap.15 p5 % 50 V 0402
C7472320602Ceramic cap.4.7 p0.25 % 50 V 0402
C7522320560Ceramic cap.100 p5 % 50 V 0402
C7592320602Ceramic cap.4.7 p0.25 % 50 V 0402
C7612320536Ceramic cap.10 p5 % 50 V 0402
C7652320540Ceramic cap.15 p5 % 50 V 0402
C7722611741Tantalum cap.4.7 u 20 % 10 V 2.0x1.3x1.2
C7822320520Ceramic cap.2.2 p0.25 % 50 V 0402
C7832312401Ceramic cap.1.0 u10 % 10 V 0805
C7852320805Ceramic cap.100 n10 % 10 V 0402
C7902320518Ceramic cap.1.8 p0.25 % 50 V 0402
C7922320560Ceramic cap.100 p5 % 50 V 0402
C7932320540Ceramic cap.15 p5 % 50 V 0402
C7942312215Ceramic cap.2.2 n5 % 50 V 0805
C7992320534Ceramic cap.8.2 p0.25 % 50 V 0402
C8012320564Ceramic cap.150 p5 % 50 V 0402
C8022312221Ceramic cap.4.7 n5 % 25 V 0805
C8032320564Ceramic cap.150 p5 % 50 V 0402
C8042320520Ceramic cap.2.2 p0.25 % 50 V 0402
C8052610203Tantalum cap.2.2 u 20 % 10 V 2.0x1.3x1.2
C8062320508Ceramic cap.1.0 p0.25 % 50 V 0402
C8292320560Ceramic cap.100 p5 % 50 V 0402
C8302320560Ceramic cap.100 p5 % 50 V 0402
C8312310793Ceramic cap.2.2 u10 % 10 V 0805
C8322320778Ceramic cap.10 n10 % 16 V 0402
C8332320744Ceramic cap.1.0 n10 % 50 V 0402
C8342320744Ceramic cap.1.0 n10 % 50 V 0402
C8352320540Ceramic cap.15 p5 % 50 V 0402
C8362320544Ceramic cap.22 p5 % 50 V 0402
C8602320548Ceramic cap.33 p5 % 50 V 0402
L1033203705Ferrite bead 0.015r 42r/100m 08050805
L1043203705Ferrite bead 0.015r 42r/100m 08050805
L2003203709Ferrite bead 0.5r 120r/100m04020402
L2713203709Ferrite bead 0.5r 120r/100m04020402
L2723203709Ferrite bead 0.5r 120r/100m04020402
L3033203709Ferrite bead 0.5r 120r/100m04020402
L3043203709Ferrite bead 0.5r 120r/100m04020402
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L5053646053Chip coil4 nQ=28/800M 0402
L5534551019Dir.coup. 1880+-30mhz 14DB 2X1.22x1.25
L6003646055Chip coil8 n5 % Q=28/800 MHz 0402
L6013646085Chip coil6 n10 % Q=29/800 MHz 0402
L6303646055Chip coil8 n5 % Q=28/800 MHz 0402
L7393646087Chip coil1 nQ=31/800M 0402
L7513203705Ferrite bead 0.015r 42r/100m 08050805
L7523640043Chip coil4 n10 % Q=50/1GHZ 0805
L7583646027Chip coil33 n5 % Q=7/100 MHz 0402
L8003648808Chip coil10 % Q=50 1206
B1004510219Crystal32.768 k+-30PPM 9PF
B3015140157Buzzer 85db 3000hz 3.0v 8.5x8.5x8.5x8.5x3
G8004350237Vco 3700-3980mhz 2.7v 20ma pcs
G8304510261VCTCXO26 M+-5PPM 2.7V GSM
F1015119019SM, fuse f 1.5a 32v 0603
Z6004511167Saw filter1960+-30 M
Z6204511167Saw filter1960+-30 M
Z6704550203Ant.switch 1850-1990mhz 6.7x5x26.7x5x2
H4009510608Rf-can assembly dmc02694 hda56
T6303640431Transf balun 1920mhz+/-70mhz 08050805
T7403640431Transf balun 1920mhz+/-70mhz 08050805
T8003640423Transf balun 3.7ghz+/-300mhz 08050805
V1001825023Chip varistor vwm9v vc20v08050805
V1014210052TransistorDTC114EEnpn RB V EM3
V1044113651Trans. supr.QUAD6 V SOT23-5
V1164110067Schottky diodeMBR0520L 20 V 0.5 A SOD123
V2504210119TransistorBC849CW npn 30 V 0.1 A SOT323
V2514210119TransistorBC849CW npn 30 V 0.1 A SOT323
V2524210052TransistorDTC114EEnpn RB V EM3
V2544110089Diode x 2BAV70W 70 V .5 A 4 ns SOT323
V3204860005LedGreen0603
V3214860005LedGreen0603
V3224860005LedGreen0603
V3234860005LedGreen0603
V3244860005LedGreen0603
V3254860005LedGreen0603
V3314864389Led0603
V3324864389Led0603
V3334864389Led0603
V3344864389Led0603
V3354864389Led0603
V3364864389Led0603
V3434110089Diode x 2BAV70W 70 V .5 A 4 ns SOT323
V3604110089Diode x 2BAV70W 70 V .5 A 4 ns SOT323
V7604110078Schdix2 bas70-05w 70v 70ma sot323SOT323
V8004210119TransistorBC849CW npn 30 V 0.1 A SOT323
V9034210185TransistorSOT343
V9054210119TransistorBC849CW npn 30 V 0.1 A SOT323
D2004370677Mad2wd1 v18 rom5 f741541g ubga144UBGA144
D2104340747Combomemory 16m flash+2m sram cspCSP
N1004370467Ccont2i wfd163kg64t/8 lfbga8x8
N1014370621Chaps v2.0 u423v20g36t lbga6x6
Fig 12 IR Transmission................................................................................................................................. 19
Fig 13 IR Module............................................................................................................................................ 20
Issue 1 06/00ãNokia Mobile Phones Ltd.Page 3
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UI ModulePAMS Technical Documentation
UIF Module
Introduction
UI module is implemented on the same PCB board with BB-module and RF-module. UI
HW parts are LCD, backlighting, audio parts, IR, keyboard, power key and vibra.
BuzzerKeys
1
2
2
BASEBAND
1
LED
8
5
LCD
3
IR
1
Vibra
Figure 1: User Interface
BB Interface
SignalParameterMinTypMaxUnitNotes
IRONXIR-module on/off0
FBUS_RXIR receive pulse
IR receive no pulse
FBUS_TX
IR transmit pulse
IR transmit no pulse
VIBRA
From VB
ROW (0:4)ROWS0
COL (0:4)COL00
0.7 x VBB
0
0.7 x VBB
0.7 x VBB
0
0.91.0
115
0.7 x VBB
0.7 x VBB
0.3 x VBB
VBB
0.3 x VBB
VBB
VBB
0.3 x VBB
1.1
140
0.3 x VBB
VBB
0.3 x VBB
VBB
VIR on state
lout@2mA
V
V
lout@2mA
V
V
mA
VKeyboard matrix row
VKeyboard matrix
column
VBBattery Voltage3.04.8VBattery
voltage (for lights)
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SignalParameterMinTypMaxUnitNotes
PWRONX0
0.7 x VBB
ROW5/
LCDCD
SCLSerial clock for LCD0
SDASerial data for LCD0.3 x VBB
LCDENLCD enable0
LCDRSTXReset0
GND00VGround
BUZZER0
LCD command/data0
0.7 x VBB
0.7 x VBB
0.7 x VBB
0.7 x VBB
0.7 x VBB
440
0
0.3 x VBB
VBB
0.3 x VBB
VBB
0.3 x VBB
VBB
VBB
0.3 x VBB
VBB
0.3 x VBB
VBB
0.3 x VBB
VBB
4700
50
VPower on key
Vkeyboard matrix row 5
LCD driver code/data
selection
VLCD driver serial clock
VLCD driver serial data
VLCD driver chip select
VLCD driver reset
V
V
Hz
%
PWM low level
PWM high level
Buzzer PWM fre-
quency
PWM duty cycle
VBB2.72.82.9 VLogic supply voltage
LIGHT0
0.7 x VBB
EARN17.6788mVConnected to COBBA
EARP17.6788mVConnected to COBBA
CCUTCharging control0
0.7 x VBB
0.3 x VBB
VBB
0.3 x VBB
VBB
VIllumination control
EARN output.
EARP output.
Stops charging
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LCD Module Interface
Line
Pin
Symbol
ParameterMinTypicalMaxUnitNotes
1VBBSupply voltage2.72.82.9
300
2SCLKSerial clock input0
0
3SDASerial data input0
0.7 x VBB
4LCDCDXControl/display
data flag input
5LCDCSXChip select input0
6OSCExternal clock for
LCD
7GND Ground0V
8VOUT DC/DC voltage
converter output
9LCDRSTXReset0
0
0.7 x VBB
0.7 x VBB
30.432.033.6kHzConnected to VBB
0.7 x VBB
4.0
VBB
0.3 x VBB
VBB
0.3 x VBB
VBB
0.3 x VBB
VBB
9V
0.3 x VBB
VBB
V
uA
MHzVBB=2.7V
V
VControl
VActive
VActive
Data
on PCB
Display Driver
Viewing through LCD cell
Figure 2: View through LCD Cell
19
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PAMS Technical DocumentationUI Module
Bottom Connector Signals
NameMinTypMaxUnitNotes
XMICP,
XMICN
XEARP,
XEARN
1.47
2.5
100
16
16
2.2
60
47
10
6.8
22
10
2.8
1
1.55
2.9
600
350
300
1.0
626
1500
kΩ
Vpp
V
V
µA
mV
W
µF
W
kΩ
Vpp
mV
kΩ
W
V
Input AC impedance
Maximum signal level
Mute (output DC level)
Unmute (output DC level)
Bias current
Maximum signal level
Output AC impedance (ref.GND)
Series output capacitance
Load AC impedance to GND (Headset)
Load AC impendance to GND (Accessory)
Maximum output level (no load)
Output signal level
Load DC resistance to GND (Accessory)
Load DC resistance to GND (Headset)
DC voltage (100k pull-up to VBB)
HEADDET21µAWhen accessory is not connected
An external headset device is connected to the system connector XMIC and XEAR lines,
from which the signals are routed to COBBA MIC3 microphone inputs and HF earphone
outputs.
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Functional Description
Audio Control
The audio control and processing is taken care of by the COBBA-GJP, which contains the
audio and RF codecs, and the MAD2, which contains the MCU, ASIC and DSP blocks handling and processing the audio signals.
DSP
MAD
MCU
Buzzer
Driver in
UISWITCH
Buzzer
MICP/N
XMICP/N
XEARP/N
Bias +
EMC
EMC + Acc.
Interf.
EMC
MIC2
MIC1
MIC3
HFCM
AuxOut
HF
EARP/N
Preamp
AmpMultipl.
Multipl.Premult.
COBBA
Pre
& LP
LP
A
D
D
A
Figure 3: Audio Control
The baseband supports three microphone inputs and two earphone outputs. The inputs
can be taken from an internal microphone, a headset microphone or PPH-1 microphones.
The microphone signals from different sources are connected to separate inputs at the
COBBA-GJP ASIC. Inputs for the microphone signals are differential type.
The MIC1 inputs are used for a headset microphone that can be connected directly to the
HS/HF connector. The internal microphone is connected to MIC2 inputs. In COBBA there
are also three audio signal outputs of which dual ended EAR lines are used for internal
ear piece and HF line accessory audio output. The third audio output AUXOUT is used for
bias supply to the headset microphone. PData(2) is used for PPH-1 mute control.
The output for the internal earphone is a dual ended type output capable of driving a
dynamic type speaker. The output for the external accessory and the headset is dual
ended (differential). Input and output signal source selection and gain control is performed inside the COBBA-GJP ASIC according to control messages from the MAD2. Keypad tones, DTMF, and other audio tones are generated and encoded by the MAD2 and
transmitted to the COBBA-GJP for decoding.
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PAMS Technical DocumentationUI Module
External audio connections
The external audio connections are presented on the next page. A headset and PPH-1
can be connected directly to the system connector. The headset microphone bias is supplied from COBBA AUXOUT output and fed to microphone through XMICP line.
10k
10k
CTIM
CHAPS
Baseband
MAD
HeadDet
CCUT
HookDet
CCONT
COBBA
EAD
AUXOUT
PData(2)
HF
HFCM
MIC1P
33n
10k
10k
100k
10ı
10ı
100k
2k2
100k
2.8 V
470R
100R
470R
220k
2.8 V
100k
33k
XEARP
XEARN
33k
100R
XMICP
MIC1N
33n
MIC3N
MIC3P
33n
33n
2k2
1k
100R
XMICN
Figure 4: External Audio Connections
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Analog audio accessory detection
In XERP signal there is a 100 kΩ pull-up and 33k pull-down in the transceiver for HeadDet. The HeadDet is pulled up when an accessory is connected, and pulled down when
disconnected. To get HeadDet working properly the system connector must be assembled
otherwise the transceiver will assume that some accessory is connected. In XMICN signal
there is a 1.2 kΩ pull-down in the transceiver and serial 1.2 kΩ from AUXOUT to XMICP.
The XMICN is connected to the transistor which is then connected to the HookDet line
(in MAD).
External accessory notices powered-up phone by detecting voltage in HeadDet line.
Accessory connectedHookDet*)HeadDet**)Notes
No accessory connectedHighLow
Headset with a button switch pressedLowHighXEAR and XMIC loaded (dc)
Headset with a button switch releasedHighHighXEAR and XMIC loaded (dc)
Hands free (PPH-1)LowHighXMIC loaded (dc)
‘) HookDet is used only for detect button in headset.
‘’’) HeadDet is used only for detect that some accessory is connected into system connector.
NOTE: Charging must stop when the detection sequences are done! CCUT signal at high
stops charging.
Headset detection
The external headset device is connected to the headset connector, from which the signals are routed to COBBA headset microphone inputs and earphone outputs. In the
XMICN line there is a 1.0 kΩ pulldown in the transceiver. The microphone is a low resistance pull-up compared to the transceiver pulldown.
When there is no call going, the AUXOUT is in high impedance state and the XMICN and
XMICP are pulled down. When a headset is connected, the XMICP is pulled up. The
switch inside the system connector is connected to the HeadDet line (in MAD), an interrupt is given due to both connection and disconnection.
NOTE: If the headset is connected switch closed, the transceiver can not detect if the
headset or PPH-1 in power off mode is connected. When switch is released to open the
transceiver can not any more detect the headset without polling by SW.
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Headset switch detection
In the XMICN line there is a 1.0 kΩ pulldown in the transceiver. The microphone is a low
resistance pull-up compared to the transceiver pulldown. When a remote control switch
is open, there is a capacitor in parallel with the microphone, so the XMICN is pulled up
and HookDet pulled closed, the XMICN is pulled down via the microphone and HookDet
is pulled up. So both pressing and releasing of the button gives an interrupt when AUXOUT is set to 2.1 V.
PPH-1 detection
The external Plug and Play PPH-1 device is connected to the system connector, from
which the signals are routed to COBBA headset microphone inputs and earphone outputs. In the XMICN line there is a 1.0 kΩ pull-down in the transceiver. The PPH-1 has a
low resistance pull-up compared to the transceiver pull-down. When there is no call
going, the AUXOUT is in high impedance state and the XMICN and XMICP is pulled down.
When a powered PPH-1 is connected, the XMICP is pulled up. The switch inside the system connector is connected to the HeadDet line (in MAD), an interrupt is given due to
both connection and disconnection.
The PPH-1 device has two operating mode devices with external microphone and without external microphone. When internal microphone is used the detection signal (EAD) is
higher than when external microphone is used.
NOTE I: If the PPH-1 is connected in power off mode, the transceiver can not detect if
the device is a headset or a PPH-1 connected. When PPH-1 is powered on it is possible to
detect when case of PPH-1.
NOTE II: If the external microphone is connected from or disconnected to PPH-1 it is not
possible for the transceiver to detect when that happens.
Internal audio connections
The speech coding functions are performed by the DSP in the MAD2 and the coded
speech blocks are transferred to the COBBA for digital to analog conversion, down link
direction. In the up link direction the PCM coded speech blocks are read from the COBBA
by the DSP.
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Display Circuit
The display circuit includes LCD module UX7 and two capacitors. The LCD module is COG
(Chip on Glass) technology. The connection method for chip on the glass is ACF, Adhesive
Conductive Film. The LCD module is connected to the UI board with STAX elastomer.
Capacitors are placed on the PCB.
The display driver includes HW-reset, voltage tripler or quadrupler which depends on
temperature, temperature compensating circuit and low power control. Driver includes
84x48 RAM memory which is used when some elements are created on the display. Elements can be created with software. Driver doesn't include CG-ROM. One bit in RAM is
the same as one pixel on the display.
GENSIO(1:0)
ROW5
LCDEN
LCDRSTX
Figure 5: Display Circuit
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Keyboard
Matrix size is 5 rows and 5 columns. Scanning is used for keyboard reading. Rows and
columns are connected to the MAD interface
Figure 6: Keyboard
ROW/COL01234
0SLIDE SWTSide KeySendEnd/ModeSide key
1NCSoft leftUpDownSoft right
2 NC 1 47*
3 NC 2 580
4 PWR switch3 69#
NC = Not Connected
Power Key
Micro switch is used as a power key on the UI module. Circuitry includes the micro
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switch and two diodes which are needed for MAD interface. Power key is connected to
CCONT. Power switch is active in LOW state. Power key is connected to ROW4.
Backlighting
Switching circuits for backlighting are placed on the UI module. Display and keyboard
lighting are connected together. When LIGHT-signal is HIGH the lights are on and when
LIGHT-signal is LOW state lights are off.
Figure 7: Backlighting
Backlighting is made by LED’s, three LED’s on the right and three on the left side of the
display. LED’s are compatible with CL270-YG and those are side illuminating. Light is on
when LIGHT-signal is in the HIGH state.
The keyboard backlighting is made by 6 LED’s.. The LED’s are compatible with CL190-YG.
Backlighting is on when LIGHT-signal is on HIGH state.
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Buzzer
Alerting tones and/or melodies as a signal of an incoming call are generated with a
buzzer that is controlled with a PWM signal by the MAD via UISWITCH. Also key press
and user function response beeps are generated with the buzzer. The buzzer is a SMD
device and is placed on the mother board. Target for SPL is 100dB (A) at 5cm.
Figure 8: Buzzer
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Speaker
Speaker circuit includes pads for speaker and 2 capacitors, 2 ferrites for EMC protection.
The speaker is sealed to the A-cover with gasket and UI PCB with supporting light guide.
With that the frequency response is more constant. The speaker does not need holes for
PCB. This gives reliable sound quality for the phone and it can be estimated in several
environments. Arrangement is a leak tolerant speaker.
The low impedance, dynamic type earphone is connected to a differential output in the
COBBA audio codec. The electrical specifications for the earphone output are shown
below. The voltage level at each output is given as reference to ground. Earphone levels
are given to 32 ohm load.
17.6mV788mVENGINE - UI Interface; Estimate,
must be checked with final earpiece construction
-7dBPa+26dBPaMeasured as shielded (in brackets
with leak ring)
Figure 9: Speaker
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Microphone
The internal microphone is placed on the B-cover. Microphone is OMNI directional. The
microphone requires a bias current to operate. The bias current is generated from
VCOBBA supply with a transistor. EMC protection parts are implemented on the motherboard.
PinNameMinTypMaxUnitNotes
X300/2MICP0.554.1mVConnected to COBBA MIC2N input. The maxi-
mum value corresponds to 1kHz, 0 dBmO network level with input amplifier gain set to 32
dB. Typical value is maximum value - 16 dB
X300/1MICN0.554.1mVConnected to COBBA MIC2P input. The maxi-
mum value corresponds to 1kHz, 0 dBmO network level with input amplifier gain set to 32
dB. Typical value is maximum value - 16 dB
Figure 10: Microphone
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Vibra Alerting Device
A vibra alerting device is used for giving silent signal to the user of an in coming call.
Vibra is located in the phone. The vibra is controlled with a PWM signal by the MAD via
UISWITCH.
SignalParameterMinTypMaxUnitNotes
M300/11.01.12.0VMeasured against
M300/2
I
vibra
Rated load current
Rated load speed7000
115
8000
140
12000
mA
rpm
Figure 11: Vibra Alerting Device
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IR Module
An infrared transceiver module is designed to substitute an electrical cable between the
phone and a PC. The infrared transceiver module is a stand alone component capable to
perform infrared transmitting and receiving functions by transforming signals transmitted in infrared light from and to electrical data pulses running in two wire asynchronous
databus. IR is located at the left bottom corner of the product.
SignalParameterMinTypMaxUnitNotes
IRONXIR-module on/off0.7 x VBB
0
FBUS_RXIR receive no pulse
IR receive pulse
FBUS_TXIR transmit pulse
IR transmit no pulse
0.7 x VBB
0
0.7 x VBB
0
VBB
0.3 x VBB
VBB
0.3 x VBB
VBB
0.3 x VBB
Vlout@2mA, IR is at
off state
IR, is at on state
V
Vlout@2mA
The module is activated with an IRONX signal by the MAD, which supplies power to the
module. The IR datalines are connected to the MAD accessory interface AccIf via FBUS.
The AccIf in MAD performs pulse encoding and shaping for transmitted data and detection and decoding for received data pulses.
The data is transferred over the IR link using serial data at speeds 9.6, 19.2, 38.4, 57.6 or
115.2 kbits/s, which leads to maximum throughput of 92.160 kbits/s. The IR module used
does not comply with the IrDA 1.0 specification (InfraRed Data Association), which is
based on the HP SIR (Hewlett-Packard`s Serial InfraRed) concept. Maximum transmission
distance is set to 60cm.
In IR transmission a light pulse corresponds to 0-bit and a "dark pulse" corresponds to 1bit.
constant pulse
IR TX
UART TX
startbitstopbit10100110
Figure 12: IR Transmission
The FBUS cannot be used for external accessory communication, when the infrared mode
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is selected. Infrared communication reserves the FBUS completely.
Figure 13: IR Module
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