Datasheet UPD75P048GC-AB8, UPD75P048CW Datasheet (NEC)

DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P048
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75P048 is a One-Time PROM version of the µPD75048. The µPD75P048 is suitable for small-scale
production or experimental production in system development.
Detailed functions are described in the following user’s manual. Read this manual when designing your
system.
µ
PD75048 User’s Manual: IEU-1278

FEATURES

The
8064 × 8 bits of one-time programmable ROM
512 × 4 bits of RAM
1024 × 4 bits of EEPROM (Data memory area)
Ports 0 to 3 and 6 to 8 with software-selectable pull-up resistors
Port 9 with software-selectable pull-down resistors
12 N-channel open drain input/output ports (ports 4, 5, and 10)
Low-voltage operation possible (VDD = 2.7 to 6.0 V)
µ
PD75048 compatible
• The µPD75P048 for evaluation/pre-production, while the µPD75048 for mass-production

ORDERING INFORMATION

Part number Package Quality grade
µ
PD75P048CW 64-pin plastic shrink DIP (750 mil) Standard
µ
PD75P048GC-AB8 64-pin plastic QFP ( 14 mm) Standard
Caution Pull-up/pull-down resistor mask options are not available.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Document No. IC-3239 (O.D. No. IC-8720) Date Published August 1994 P
Printed in Japan
The information in this document is subject to change without notice.
The mark shows major revised points.
©
1994

PIN CONFIGURATION (Top View)

• 64-pin plastic shrink DIP
µ
PD75P048
• 64-pin plastic QFP
SB1/SI/P03
SB0/SO/P02
SCK/P01
INT4/P00
BUZ/P23 PCL/P22
PPO/P21
PTO0/P20 MAT/P103 MAZ/P102
MAI/P101
MAR/P100
RESET
X1 X2
V XT1 XT2
V
AVDD
AVREF+
AVREF–
AN7 AN6 AN5
AN4 AN3/P113 AN2/P112 AN1/P111 AN0/P110
AV
TI0/P13
1 2 3 4 5 6 7 8
9 10 11 12 13 14
µ
PD75P048CW
15 16
PP
17 18 19
DD
20 21 22 23 24 25 26 27 28 29 30 31
SS
32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
V
SS
P30/MD0 P31/MD1 P32/MD2 P33/MD3 P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 P81 P82 P83 P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2
P43 P42 P41
P40 MD3/P33 MD2/P32 MD1/P31 MD0/P30
V
SB1/SI/P03
SB0/SO/P02
SCK/P01
INT4/P00
BUZ/P23
PCL/P22
PPO/P21
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 2 3 4 5 6 7 8 9
SS
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
µ
PD75P048GC-AB8
X1
X2
RESET
MAI/P101
PTO0/P20
MAT/P103
MAZ/P102
MAR/P100
P70/KR4
P71/KR5
P72/KR6
VPP
XT1
XT2
P73/KR7
P80
P81
VDD
AVDD
AVREF+
P82
AVREF–
P83
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AN7
P90 P91 P92 P93 P10/INT0 P11/INT1 P12/INT2 TI0/P13 AV
SS
AN0/P110 AN1/P111 AN2/P112 AN3/P113 AN4 AN5 AN6
2
µ
PD75P048

PIN IDENTIFICATION

P00-03 : Port0
P10-13 : Port1
P20-23 : Port2
P30-33 : Port3
P40-43 : Port4
P50-53 : Port5
P60-63 : Port6
P70-73 : Port7
P80-83 : Port8
P90-93 : Port9
P100-103 : Port10
P110-113 : Port11
KR0-7 : Key Return
SCK : Serial Clock
SI : Serial Input
SO : Serial Output
SB0, 1 : Serial Bus 0, 1
RESET : Reset Input
TI0 : Timer Input 0
PTO0 : Programmable Timer Output 0
BUZ : Buzzer Clock
PCL : Programmable Clock
INT0,1,4 : External Vectored Interrupt 0, 1, 4
INT2 : External Test Input 2
X1, 2 : Main System Clock Oscillation 1, 2
XT1, 2 : Subsystem Clock Oscillation 1, 2
MAR : Reference Integration Control
MAI : Integration Control
MAZ : Autozero Control
MAT : External Comparate Timing Input
PPO : Programmable Pulse Output ... MFT timer mode
AN0-7 : Analog Input 0-7
AVREF+ : Analog Reference (+)
REF- : Analog Reference (-)
AV
AVDD : Analog VDD
AVSS : Analog VSS
VDD : Positive Power Supply
VSS : Ground
VPP : Programming Power Supply
MD0-MD3 : Mode Selection
MFT A/D mode
Remarks MFT: Multi-function timer
3
4
TI0/P13
PTO0/P20
BASIC INTERVAL TIMER
INTBT
TIMER/ COUNTER #0
INTT0
PROGRAM COUNTER
SP
CY
ALU
BIT SEQ. BUFFER
PORT 0
PORT 1 P10 - P13
P00 - P03

BLOCK DIAGRAM

SI/SB1/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0 - KR3/P60 - P63 KR4 - KR7/P70 - P73
BUZ/P23
AVDD
AVREF+
AVREF–
AVSS
AN0 - AN3/P110 - P113
AN4 - AN7
MAR/P100
MAI/P101
MAZ/P102
MAT/P103
PPO/P21
SERIAL INTERFACE
INTCSI
INTERRUPT CONTROL
WATCH TIMER
INTW
A/D CONVERTER
MULTI­FUNCTION TIMER
PROM PROGRAM MEMORY 8064 × 8 BITS
CLOCK OUTPUT CONTROL
PCL/P22
N
fx/2
CLOCK DIVIDER
DECODE AND CONTROL
CLOCK GENERATOR
SUB
XT1 XT2
MAIN
X1 X2
BANK
DATA MEMORY
GENERAL REG.
RAM
512 × 4 BITS
EEPROM
1024 × 4 BITS
CPU CLOCK
Φ
STAND BY CONTROL
PORT 2 P20 - P23
PORT 3 P30/MD0 - P33/MD3
PORT 4 P40 - P43
PORT 5 P50 - P53
PORT 6 P60 - P63
PORT 7 P70 - P73
PORT 8 P80 - P83
PORT 9 P90 - P93
PORT 10 P100 - P103
PORT 11 P110 - P113
µ
PD75P048
INTMFT
VSSVDDVPP
RESET
µ
PD75P048
CONTENTS
1. PIN FUNCTIONS ························································································································· 6
1.1 PORT PINS ·········································································································································· 6
1.2 NON-PORT PINS ································································································································· 8
1.3 PIN INPUT/OUTPUT CIRCUITS ········································································································ 10
2. DIFFERENCES BETWEEN THE µPD75P048 AND THE µPD75048 ······································· 13
3. PROM (PROGRAM MEMORY) WRITE AND VERIFY····························································· 14
3.1 PROM WRITE AND VERIFY OPERATION MODE ·········································································· 14
3.2 PROM WRITE PROCEDURE ·············································································································· 15
3.3 PROM READ PROCEDURE ················································································································ 16
4. SCREENING OF ONE-TIME PROM MODEL··········································································· 17
5. ELECTRICAL SPECIFICATIONS ·································································································· 18
6. PERFORMANCE CURVE (REFERENCE VALUE) ····································································· 32
7. PACKAGE DRAWINGS··············································································································· 34
8. RECOMMENDED SOLDERING CONDITIONS ········································································· 36
APPENDIX A. DEVELOPMENT TOOLS ·························································································· 37
APPENDIX B. RELATED DOCUMENTS ·························································································· 38
5

1. PIN FUNCTIONS

1.1 PORT PINS (1/2)
µ
PD75P048
Pin Name
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
Note 2
P30
Note 2
P31
Note 2
P32
Note 2
P33
P40 - P43
Note 2
Input/
Output
Input
I/O
I/O
I/O
Input
I/O
I/O
I/O
Shared Pin
INT4
SCK
SO/SB0
SI/SB1
INT0
INT1
INT2
TI0
PTO0
PPO
PCL
BUZ
MD0
MD1
MD2
MD3
Function
4-bit input port (PORT0). For P01 to P03, pull-up resistors can be provided by software in units of 3 bits.
With noise elimination function
4-bit input port (PORT1). Pull-up resistors can be provided by software in units of 4 bits.
4-bit I/O port (PORT2). Pull-up resistors can be provided by software in units of 4 bits.
Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits.
N-ch open-drain 4-bit I/O port (PORT4). Can withstand 10 V. Data input/output pins for the PROM write and verity (Four low-order bits).
8-Bit I/O
×
×
×
×
When Reset
Input
Input
Input
Input
High impedance
I/O Circuit
Note 1
Type
B
-A
F
-B
F
-C
M
-C
B
E-B
E-B
M-A
P50 - P53
Note 2
I/O
N-ch open-drain 4-bit I/O port (PORT5). Can withstand 10 V. Data input/output pins for the PROM write and verify (Four high-order bits).
Note 1. The circle ( ) indicates the Schmitt trigger input.
2. Can directly drive LEDs.
High impedance
M-A
6
1.1 PORT PINS (2/2)
µ
PD75P048
Pin Name
P60
P61
P62
P63
P70
P71
P72
P73
P80 - P83
P90 - P93
P100
P101
P102
P103
P110
P111
P112
P113
Input/
Output
I/O
I/O
I/O
I/O
I/O
Input
Shared Pin
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
MAR
MAI
MAZ
MAT
AN0
AN1
AN2
AN3
Function
Programmable 4-bit I/O port (PORT 6). Pull-up resistors can be provided by software in units of 4 bits.
4-bit I/O port (PORT 7). A pull-up resistor can be provided by software in units of 4 bits
4-bit I/O port (PORT 8). A pull-up resistor can be provided by software in units of 4 bits.
4-bit I/O port (PORT 9). A pull-up resistor can be provided by software in units of 4 bits.
N-ch open drain 4-bit I/O port (PORT 10). Can withstand 10 V in open-drain mode.
4-bit input port (PORT 11).
8-Bit I/O
×
×
When Reset
Input
Input
Input
Input
High impedance
Input
I/O Circuit
Note
Type
-A
F
-A
F
E-B
E-D
M-A
Y
Note The circle ( ) indicates the Schmitt trigger input.
7
1.2 NON-PORT PINS (1/2)
µ
PD75P048
Pin Name
TI0
PTO0
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 - KR3
KR4 - KR7
MAR
MAI
MAZ
MAT
PPO
AN0 - AN3
AN4 - AN7
AVREF+
AVREF–
AVDD
AVSS
Input/
Output
Input
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
Shared Pin
P13
P20
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60 - P63
P70 - P73
P100
P101
P102
P103
P21
P110 - P113
Function
Input for receiving external event pulse signal for timer/event counter
Timer/event counter output
Clock output
Output for arbitrary frequency output (for buzzer output or system clock trimming)
Serial clock I/O
Serial data output Serial bus I/O
Serial data input Serial bus I/O
Edge detection vectored interrupt input (either rising edge or falling edge detection)
Edge detection vectored interrupt input (detection edge selectable)
Edge detection testable input (rising edge detection)
Parallel falling edge detection testable input
Parallel falling edge detection testable input
In MFT integrat­ing A/D converter mode
In MFT timer mode
For A/D converter only
Reverse integration signal output
Integration signal output
Auto-zero signal output
Comparator input
Timer pulse output
8-bit analog input
Reference voltage input (AVDD side)
Reference voltage input (AVSS side)
Positive power supply
GND potential
When Reset
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
High impedance
High impedance
High impedance
High impedance
Input
I/O Circuit
Note
Type
-C
B
E-B
E-B
E-B
-A
F
-B
F
-C
M
B
-C
B
-C
B
-A
F F
-A
M-A
M-A
M-A
M-A
E-B
Y-A
Y-A
Z-A
Z-A
Note The circle ( ) indicates the Schmitt trigger input.
Remark MFT: Multi-Function Timer
8
1.2 NON-PORT PINS (2/2)
µ
PD75P048
Pin Name
X1, X2
XT1, XT2
RESET
MD0 - MD3
Note 2
VPP
VDD
VSS
Input/
Output
Input
Input
Input
I/O
Shared Pin
P30 - P33
Function
Crystal/ceramic resonator connection for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2.
Crystal connection for subsystem clock generation. When external clock signal is used, it is applied to XT1, and its reverse phase signal is applied to XT2. XT1 can be used as a 1-bit input (test).
System reset input
Operation mode selection pins during the PROM write/verify cycles.
Normally connected to VDD directly; +12.5 V is applied as the programming voltage during the PROM write/verify cycles.
Positive power supply
GND potential
When Reset
Input
Note 1. The circle ( ) indicates the Schmitt trigger input.
2. The VPP should be connected to VDD directly in normal operation mode. If VPP and VDD pins are not
µ
connected, the
PD75P048 does not operate correctly.
I/O Circuit
Note 1
Type
B
E-B
9

1.3 PIN INPUT/OUTPUT CIRCUITS

The input/output circuit of each µPD75P048 pin is shown below in a simplified manner.
Type A (For Type E-B)
Type D (For Type E-B, F-A)
µ
PD75P048
(1/3)
Type B
VDD
Data
P-ch
IN
N-ch
CMOS input buffer
Type E-B
IN
Output disable
Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch)
P.U.R.
enable
Data
Output disable
Type D
VDD
P-ch
OUT
N-ch
VDD
P.U.R.
P-ch
IN/OUT
Schmitt trigger input with hysteresis
Type B-C Type E-D
VDD
P.U.R.
P-ch
IN
P.U.R.: Pull-Up Resistor P.D.R.: Pull-Down Resistor
P.U.R. enable
Data
Output disable
Type A
P.U.R.: Pull-Up Resistor
Type D
Type A
P.D.R.
enable
IN/OUT
N-ch
P.D.R.
10
Type F-A Type M-C
VDD
µ
PD75P048
VDD
(2/3)
Output disable
Type F-B
Output disable
(P)
Data
Output disable
Data
Output disable
(N)
P.U.R.
enable
Type D
Type B
P.U.R.: Pull-Up Resistor
P.U.R.
enable
VDD
P-ch
N-ch
P.U.R.
P-ch
IN/OUT
VDD
P.U.R.
P-ch
IN/OUT
Output disable
Type Y
IN
AVDD
Data
P.U.R.
enable
P.U.R.: Pull-Up Resistor
P-ch N-ch
AVSS
Sampl­ing C
Input enable
P.U.R.
P-ch
IN/OUT
N-ch
AVDD
+
AVSS
Reference voltage (from voltage tap of series resistor string)
P.U.R.: Pull-Up Resistor
Type M-A Type Y-A
IN/OUT
Data
Output disable
Middle-voltage input buffer (Can withstand + 10 V)
P.U.R.: Pull-Up Resistor
N-ch (Can with­ stand + 10 V)
AVDD
IN
P-ch N-ch
AVSS
Input buffer
+ Sampl­ing C
Reference voltage (from voltage tap of series resistor string)
IN instruction
AVDD
AVSS
11
Type Z-A
AVREF+
AVREF–
Reference voltage
(3/3)
µ
PD75P048
12
µ
PD75P048
2. DIFFERENCES BETWEEN THE µPD75P048 AND THE µPD75048
The µPD75P048 is a One-Time PROM version of the µPD75048. The µPD75P048 has the same CPU and internal hardwares. Table 2-1 shows the differences between the µPD75P048 and the µPD75048. Bear in mind the differences between these two products when debugging or developing on an experimental basis your application system by using the one-time PROM model, and then mass-producing the application system by using the mask ROM model.
µ
Details for the CPU functions and internal hardwares are available in
µ
Table 2-1 Differences between the
Program Memory
Pull-up Resistors
Pull-Down Resistors
XT1 Feedback Resistor
Pin Connection
Electrical Specification
Other
Items
Ports 0 to 3 and 6 to 8
Ports 4, 5 and 10
Port 9
60 - 63 (SDIP) 5 - 8 (QFP)
16 (SDIP) 25 (QFP)
PD75P048 and the µPD75048
µ
PD75P048
One-time PROM Mask ROM
N/A Mask-option
On-chip Mask-option
P33/MD3 - P30/MD0 P33 - P30
VPP IC
Current dissipation differs. For details, refer to Data Sheet of each model.
Circuit scale and mask layout differ. Consequently, noise immunity and noise radiation differ.
PD75048 User’s Manual (IEU-1278).
µ
PD75048
• 0000H to 1F7FH
• 8064 × 8 bits
Software-selectable
Software-selectable
Note The noise immunity and noise radiation of the PROM and mask ROM models differ. To replace the PROM
mode, which has been used for experimental production of your application system with the mask ROM model for mass production of the application system, be sure to perform thorough evaluation by using the CS model (not ES model) of the mask ROM model.
13
µ
PD75P048

3. PROM (PROGRAM MEMORY) WRITE AND VERIFY

The µPD75P048 contains 8064 bytes of PROM. The following table shows the pin functions during the write and verify cycles. Note that it is not necessary to enter an address, because the address is updated by pulsing the X1 clock pins.
Pin Name
VPP
X1, X2
MD0 - MD3 (P30 - P33)
P40 - P43 (lower 4 bits) P50 - P53 (higher 4 bits)
VDD
Normally 2.7 to 6 V; 12.5 V is applied during write/verify
After a write/verify write, the X1 and X2 clock pins are pulsed. The inverted signal of the X1 should be input to the X2. Note that these pins are also pulsed during a read.
Operation mode selection pins.
8-bit data input/output pins for write and verify
Supply voltage. Normally 2.7 to 6 V; 6 V is applied during write/verify
Function
Caution The µPD75P048CW/GC do not have a UV erase window, thus the PROM contents cannot be erased
with ultra-violet ray.

3.1 PROM WRITE AND VERIFY OPERATION MODE

When 6 V and 12.5 V are applied to the V
DD and VPP pins, respectively, the PROM is placed in the write/verify
mode. The operation is selected by the MD0 to MD3 pins, as shown in the table.
The other pins should be returned to VSS potential via pull-down resistors.
VPP
+12.5 V
Operation Mode Specification
VDD
+6 V
MD0
H
L
L
H
MD1
L
H
L
×
MD2
H
H
H
H
MD3
L
H
H
H
Clear program memory address to 0
Write mode
Verify mode
Program inhibit
Operation Mode
14
×: Don’t care.
µ
PD75P048

3.2 PROM WRITE PROCEDURE

PROMs can be written at high speed using the following procedure: (see the following figure)
(1) Pull unused pins to V
SS through resistors. Set the X1 pin low.
(2) Supply 5 volts to the VDD and VPP pins. (3) Wait for 10 µs. (4) Select the zero clear program memory address mode. (5) Supply 6 volts to the V
DD and 12.5 volts to the VPP pins.
(6) Select the program inhibit mode. (7) Write data in the 1 ms write mode. (8) Select the program inhibit mode. (9) Select the verify mode. If the data is correct, proceed to step (10). If not, repeat steps (7), (8) and (9). (10) Perform one additional write (duration of 1 ms × number of writes at (7) to (9)). (11) Select the program inhibit mode. (12) Apply four pulses to the X1 pin to increment the program memory address by one. (13) Repeat steps (7) to (12) until the end address is reached. (14) Select the zero clear program memory address mode. (15) Return the V
DD and VPP pins back to + 5 volts.
(16) Turn off the power.
The following figure shows steps (2) to (12).
X repetition
Write Verify Additional write
VPP
VPP
VDD
VDD+1
VDD
VDD
X1
P40-P43 P50-P53
MD0 (P30)
Input data
Output data
Address increment
Input data
MD1 (P31)
MD2 (P32)
MD3 (P33)
15
µ
PD75P048

3.3 PROM READ PROCEDURE

The PROM contents can be read in the verify mode by using the following procedure: (see the following figure) (1) Pull unused pins to V
SS through resistors. Set the X1 pin low.
(2) Supply 5 volts to the VDD and VPP pins.
µ
(3) Wait for 10
s. (4) Select the clear program memory address mode. (5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins. (6) Select the program inhibit mode. (7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored
in one address. (8) Select the program inhibit mode. (9) Select the clear program memory address mode. (10) Return the V
DD and VPP pins back to + 5 volts.
(11) Turn off the power.
The following figure shows steps (2) to (9).
VPP
VPP
VDD
VDD+1
VDD
VDD
X1
P40-P43 P50-P53
MD0 (P30)
MD1 (P31)
MD2 (P32)
“L”
Output data
Output data
16
MD3 (P33)
µ
PD75P048

4. SCREENING OF ONE-TIME PROM MODEL

Because of their structure, the one-time PROM models (µPD75P48CW and µPD75P48GC-AB8) cannot be fully tested by NEC before shipment. It is therefore recommended that you implement screening to verify the PROM after necessary data have been written to it, and after the PROM has been stored at high temperature under the following conditions:
Storage Temperature Storage Time
125 ˚C 24 hours
17

5. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Parameter Symbol Conditions Ratings Unit Supply Voltage VDD -0.3 to +7.0 V Input Voltage VI1 Other than ports 4, 5, 10 -0.3 to VDD+0.3 V
VI2 Ports 4, 5, 10 w/pull-up -0.3 to VDD+0.3
Output Voltage VO -0.3 to VDD+0.3 V High-Level Output IOH 1 pin -10 mA
Current
Low-Level Output IOL Current
Operating Temperature Topt -10 to +70 °C Storage Temperature Tstg -65 to +150 °C
Note
µ
PD75P048
resistor Open drain -0.3 to +11 V
All pins -30 mA Ports 0, 3, 4, 5 Peak 30 mA
1 pin
Other than ports 0, 3, 4, 5 Peak 20 mA 1 pin
Total of ports 0, 3 - 9, 11 Peak 170 mA
Total of ports 0, 2, 10 Peak 30 mA
rms 15 mA
rms 5 mA
rms 120 mA
rms 20 mA
V
Note rms = Peak value x Duty
Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality
of the product may be degraded. The absolute maximum rating therefore specifies the upper or
lower limit of the value at which the product can be used without physical damages. Be sure not
to exceed or fall below this value when using the product.
EEPROM RATINGS (T
Parameter Symbol Conditions Ratings Unit Write Times 100,000 times Data Retention Time 10 years
a = -10 to +70°C, VDD = 2.7 to 6.0 V)
CAPACITANCE (Ta = 25°C, VDD = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Input Capacitance CI f = 1 MHz 15 pF Output Capacitance CO Pins other than those measured are at 0 V 15 pF Input/Output CIO
15 pF
18
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(Ta = -10 to +70°C, VDD = 2.7 to 6.0 V)
µ
PD75P048
Oscillator
Ceramic Oscillation VDD = oscillation
Crystal Oscillation
External Clock X1 input frequency
Recommended
Constants
X1 X2
C1 C2
VDD
X1 X2
C1 C2
VDD
X1 X2
µ
PD74HCU04
Item Conditions MIN. TYP. MAX. Unit
Note 2
Note 2
Note 1
Note 1
voltage range
MIN. value of oscillation voltage range
2.0 5.0
2.0 4.19 5.0
2.0 5.0
Note 3
MHz
4ms
Note 3
MHz
10 ms
30 ms
Note 3
MHz
frequency(fX)
Oscillation stabiliza- After VDD come to tion time
frequency (fX)
Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time
Note 1
(fX)
X1 input high-, low-level widths 100 250 ns (tXH, tXL)
Note 1. Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to
AC Characteristics.
2. Time required for oscillation to stabilize after VDD has reached the minimum volue of the oscillation
voltage range or the STOP mode has been released.
3. When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction
µ
execution time: otherwise, one machine cycle is set to less than 0.95
µ
minimum value of 0.95
s.
s, falling short of the rated
Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted
line in the figures as follows to avoid adverse influences on the wiring capacity:
• Keep the wiring length as short as possible.
• Do not cross the wiring over the other signal lines.
• Do not route the wiring in the vicinity of lines through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillator circuit at the same potential as
DD. Do not connect the ground pattern through which a high curent flows.
V
• Do not extract signals from the oscillation circuit.
19
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(Ta = -10 to +70°C, VDD = 2.7 to 6.0 V)
µ
PD75P048
Oscillator
Crystal Oscillation
External Clock XT1 input frequency
Recommended
Constants
XT1 XT2
C3 C4
V
DD
XT1 XT2
Item Conditions MIN. TYP. MAX. Unit
frequency (fXT)
R
Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time
Note 1
(fXT)
XT1 input high-, low-level widths (tXTH, tXTL)
Note 1
Note 2
32 32.768 35 kHz
1.0 2 s
10 s
32 100 kHz
515
µ
s
Note 1. Indicates only the characteristics of the oscillator circuit. For instruction execution time, refer to AC
Characteristics.
2. Time required for oscillation to stabilize after V
DD has reached the minimum value of the oscillation
voltage range.
Caution When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line
in the figures as follows to avoid adverse influences on the wiring capacity:
• Keep the wiring length as short as possible.
• Do not cross the wiring over the other signal lines.
• Do not route the wiring in the vicinity of lines through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillator circuit at the same potential as
DD. Do not connect the ground pattern through which a high current flows.
V
• Do not extract signals from the oscillation circuit.
The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce
the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise
more easily than the main system clock oscillation circuit. When using the subsystem clock,
therefore, exercise utmost care in wiring the circuit.
20
µ
PD75P048
DC CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-Level Input VIH1 Ports 2,3,8,9,11 0.7VDD VDD V Voltage
Low-level Input VIL1 Ports 2-5, 8-11 0 0.3VDD V Voltage
High-Level Output VOH VDD = 4.5 to 6.0V, IOH = -1 mA VDD-1.0 V Voltage
Low-Level Output VOL Ports 3,4,5 VDD = 4.5 to 6.0V, Voltage IOL = 15mA
High-Level Input ILIH1 VI = VDD Other than below 3 Leakage Current
Low-Level Input ILIL1 VI = 0V Other than below -3 Leakage Current
High-Level Output ILOH1 VO = VDD Other than below 3 Leakage Current
Low-Level Output ILOL VO = 0V Leakage Current
Internal Pull-Up Resistor RU1 Ports 0,1,2,3,6,7,8 VDD = 5.0V±10% 15 40 80 k
Internal Pull-Down RD Port 9 VIN = VDD VDD = 5.0V±10% 15 40 70 k Resistor
VIH2 Ports 0,1,6,7, RESET 0.8VDD VDD V VIH3 Ports 4,5,10 w/pull-up resistor 0.7VDD VDD V
Open-drain 0.7VDD 10 V
VIH4 X1, X2, XT1, XT2 VDD-0.5 VDD V
VIL2 Ports 0, 1, 6, 7, RESET 0 0.2VDD V VIL3 X1, X2, XT1, XT2 0 0.4 V
IOH = -100 µA VDD-0.5 V
0.4 2.0 V
VDD = 4.5 to 6.0V, IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V SB0, 1 Open-drain pull-up
ILIH2 X1,X2,XT1 20 ILIH3 VI = 9V Ports 4,5,10
ILIL2 X1,X2,XT1 -20
ILOH2 VO = 9V Ports 4,5,10
(except P00) VI = 0V
RU2 Ports 4,5,10 VDD = 5.0V±10% 15 40 70 k
VO = VDD-2.0 V
resistor 1 k
(open-drain)
(open-drain)
VDD = 3.0V±10% 30 300 k
VDD = 3.0V±10% 10 60 k
VDD = 3.0V±10% 10 60 k
0.2VDD V
20
20
-3
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
21
µ
PD75P048
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply IDD1 4.19MHz crystal VDD = 5V±10%
Note 1
Current
IDD2
IDD3 32.768kHz
IDD4 HALT mode VDD = 3V±10% 35 110 IDD5 XT1 = 0V VDD = 5V±10% 0.5 20
IDD6 32.768kHz oscillator VDD = 3V±10%
oscillator C1 = C2 = 22pF
Note 4
crystal oscillator mode
STOP mode VDD = 3V±10% 0.3 10
STOP mode
VDD = 3V±10% HALT mode VDD = 5V±10% 900 2700
Operation VDD = 3V±10%
Note 2
Note 3
VDD = 3V±10% 450 1400
Ta = 25°C 5
Note 5
5.5 17 mA
1.7 5.1 mA
100 300
620
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
Note 1. Current flowing through internal pull-up resistor. Current flowing when EEPROM is accessed is not
included.
2. When µPD75048 operates in high-speed mode with processor clock control register (PCC) set to 0011.
µ
3. When
PD75048 operates in low-speed mode with PCC set to 0000.
4. When the system clock control register (SCC) is set to 1001, the oscillation of the main system clock is stopped, and the subsystem clock is used.
5. When STOP instruction is executed with SCC set to 0000.
Note Supply current when EEPROM is accessed is shown in EEPROM Characteristics.
22
µ
PD75P048
AC CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CPU Clock Cycle Time tCY w/main system clock VDD = 4.5 to 6.0V 0.95 32 (Minimum Instruction Execution Time = 1 Machine Cycle)
TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz
TI0 Input High-, Low- tTIH, VDD = 4.5 to 6.0 V 0.48 Level Widths t
Interrupt Input High-, tINTH, INT0 Low-Level Widths t
RESET Low-Level Width tRSL 10
Note 1
TIL
INTL
w/subsystem clock
INT1, 2, 4 10
KR0-7 10
3.8 32
114 122 125
0 275 kHz
1.8
Note 2
Note 1. The CPU clock (Φ) cycle time is de-
termined by the oscillation frequency
of the connected oscillator, system
clock control register (SCC), and
processor clock control register (PCC).
The figure on the right is cycle time t
vs. supply voltage VDD characteristics
at the main system clock.
tCY or 128/fX depending on the set-
2. 2
ting of the interrupt mode register
(IM0).
CY
32
6
5
4
3
µ
tCY vs VDD
(with main system clock)
Operation quaranteed range
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
2
Cycle time tCY [ s]
1
0.5 0123 4 56
Supply voltage V
DD [V]
23
µ
SERIAL TRANSFER OPERATION
Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY1 VDD = 4.5 to 6.0 V 1600 ns
3800 ns
SCK High-, Low-Level tKL1 VDD = 4.5 to 6.0 V tKCY1/2-50 ns Widths
SI Set-Up Time (vs. SCK ) tSIK1 150 ns SI Hold Time (vs. SCK ) tKSI1 400 ns SCK ↓→ SO Output tKSO1 RL = 1k,
Delay Time CL = 100pF
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY2 VDD = 4.5 to 6.0V 800 ns
SCK High-, Low-Level tKL2 VDD = 4.5 to 6.0V 400 ns Widths
SI Set-Up Time (vs. SCK ) tSIK2 100 ns SI Hold Time (vs. SCK ) tKSI2 400 ns SCK ↓→ SO Output tKSO2 RL = 1k, CL = 100 pF
Delay Time
Note RL and CL are load resistance and load capacitance of the SO output line.
tKH1 tKCY1/2-150 ns
Note
VDD = 4.5 to 6.0V 250 ns
1000 ns
3200 ns
tKH2 1600 ns
Note
VDD = 4.5 to 6.0V 300 ns
1000 ns
PD75P048
24
µ
PD75P048
SBI MODE (SCK: internal clock output (master))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY3 VDD = 4.5 to 6.0 V 1600 ns
3800 ns
SCK High-, Low-Level tKL3 VDD = 4.5 to 6.0 V tKCY3/2-50 ns Widths t
SB0, 1 Set-Up Time tSIK3 (vs. SCK )
SB0, 1 Hold Time tKSI3 (vs. SCK )
SCK ↓→ SB0, 1 Output tKSO3 RL = 1k, Delay Time
SCK ↑→ SB0, 1 tKSB tKCY3 ns SB0,1 ↓→ SCK tSBK tKCY3 ns SB0, 1 Low-Level Width tSBL tKCY3 ns SB0, 1 High-Level Width tSBH tKCY3 ns
KH3
CL = 100pF
tKCY3/2-150 ns
150 ns
tKCY3/2 ns
Note
VDD = 4.5 to 6.0V 0 250 ns
0 1000 ns
SBI MODE (SCK: external clock input (slave))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY4 VDD = 4.5 to 6.0 V 800 ns
3200 ns
SCK Ligh-, Low-Level tKL4 VDD = 4.5 to 6.0 V 400 ns Widths tKH4
SB0, 1 Set-Up Time tSIK4 (vs. SCK )
SB0, 1 Hold Time tKSI4 (vs. SCK )
SCK ↓→ SB0, 1 Output tKSO4 RL = 1k, Delay Time
SCK ↑→ SB0, 1 tKSB tKCY4 ns SB0,1 ↓→ SCK tSBK tKCY4 ns SB0, 1 Low-Level Width tSBL tKCY4 ns SB0, 1 High-Level Width tSBH tKCY4 ns
CL = 100pF
Note
VDD = 4.5 to 6.0V 0 300 ns
1600 ns
100 ns
tKCY4/2 ns
0 1000 ns
Note RL and CL are load resistance and load capacitance of the SB0 and SB1 output lines.
25
µ
A/D CONVERTER (Ta = -10 to +70°C, VDD = 2.7 to 6.0V, AVSS = VSS = 0V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 bit
Note 2
Note 3
Note 1
2.5V AVREF VDD ±1.5 LSB
tCONV 168/fX tSAMP 44/fX
µ
s: fX = 4.19 MHz)
Absolute Accuracy Conversion Time Sampling Time Analog Input Voltage VIAN AVREF- AVREF+ V Analog Supply Voltage AVDD 2.5 VDD V Reference Input Voltage AVREF+ 2.5V (AVref+) – (AVref-) 2.5 AVDD V Reference Input Voltage AVREF- 2.5V (AVref+) – (AVref-) 0 1.0 V Analog Input Impedance RAN 1000 M AVREF Current AIREF 0.25 2.0 mA
Note 1. Absolute accuracy excluding quantization error (±1–2LSB)
2. Time since execution of conversion start instruction until end of conversion (EOC = 1) (40.1 µs: fX = 4.19
MHz)
3. Time since execution of conversion start instruction until end of sampling (10.5
PD75P048
µ
s
µ
s
26
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
0.8 V
DD
Test points
0.2 VDD
CLOCK TIMING
t
XL
1/f
µ
PD75P048
0.8 VDD
0.2 VDD
X
t
XH
TI0 TIMING
X1 input
XT1 input
1/f
XT
t
XTL
t
1/fTI
tTIL tTIH
XTH
V
DD
0.4 V
V
DD
0.4 V
–0.5V
–0.5V
TI0
27
SERIAL TRANSFER TIMING
THREE-LINE SERIAL I/O MODE:
SCK
µ
PD75P048
t
KCY1
t
KL1
t
SIK1
t
KH1
t
KSI1
SI
SO
TWO-LINE SERIAL I/O MODE:
SCK
t
KS01
Input data
tKCY2
tKL2
tSIK2 tKSI2
Output data
tKH2
28
SB0,1
tKSO2
SERIAL TRANSFER TIMING
BUS RELEASE SIGNAL TRANSFER:
SCK
t
KSB
SB0,1
COMMAND SIGNAL TRANSFER:
µ
PD75P048
t
KCY3,4
t
KL3,4
t
t
t
SBL
SBH
SBK
t
KH3,4
t
KS03,4
t
SIK3,4
t
KSI3,4
SCK
SB0,1
INTERRUPT INPUT TIMING
INT0, 1, 2, 4
KR0-7
RESET INPUT TIMING
tKCY3,4
tKL3,4
tKH3,4
tSBKtKSB
tINTL tINTH
tKS03,4
tSIK3,4
tKSI3,4
RESET
tRSL
29
µ
PD75P048
EEPROM CHARACTERISTICS
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current for IDD7 4.19MHz crystal oscillator VDD = 5V+10% EEPROM access
Note 1
C1 = C = 22pF
VDD = 3V+10%
Note 2
Note 3
6.5 20 mA 26mA
Note 1. Current flowing through the internal pull-up resistor is not included.
2. When the processor clock control register (PCC) is set to 0011 and the high-speed mode is used.
3. When PCC is set to 0000 and the low-speed mode is used.
EEPROM WRITE TIME
Select the write time of the EEPROM in accordance with the oscillation frequency of the main system clock
as follows:
Oscillation Frequency of Main Setting of EEPROM Control Register System Clock (fX)
fX = 2.0 to 5.0 MHz 0 0 212 x 18/fX (17.6 ms) fX = 2.0 to 4.2 MHz 0 1 211 x 18/fX (8.8 ms) fX = 2.0 MHz 1 0 210 x 18/fX
EWTC1 EWTC0
Write time
Remarks ( ): fX = 4.19 MHz
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(Ta = –10 to +70°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data Retention Supply VDDDR Voltage
Data Retention Supply
Note 1
Current
Release Signal Set Time tSREL 0
Oscillation Stabilization Wait Time
Note 2
IDDDR VDDDR = 2.0 V
tWAIT Released by RESET 217/fX ms
Released by interrupt request ms
2.0 6.0 V
0.1 10
Note 3
Note 1. Does not include current flowing through internal pull-up resistor
2. The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable
operation when oscillation is started.
3. Depends on the setting of the basic interval timer mode register (BTM) as follows:
µ
A
µ
s
BTM3 BTM2 BTM1 BTM0 WAIT time ( ): fX = 4.19 MHz
0 0 0 220/fX (approx. 250 ms) – 0 1 1 217/fX (approx. 31.3 ms) – 1 0 1 215/fX (approx. 7.82 ms) –1112
13
/fX (approx. 1.95 ms)
30
DATA RETENTION TIMING (releasing STOP mode by RESET)
Internal reset operation
HALT mode
STOP mode
Data retention mode
DD
V
STOP instruction execution
RESET
VDDDR
tSREL
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
µ
PD75P048
tWAIT
Operation mode
DD
V
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
VDDDR
HALT mode
Operation mode
tSREL
tWAIT
31

6. PERFORMANCE CURVE (REFERENCE VALUE)

10
DD vs VDD (Crystal oscillation)
I
µ
PD75P048
(T = 25 °C)
a
5.0
1.0
0.5
0.1
High-speed mode PCC = 0011
Medium-speed mode
Low-speed mode PCC = 0000
Main system clock HALT mode
Subsystem clock operation mode
Main system lock stopped
Main system clock stopped
Subsystem clock HALT mode
PCC = 0010
+
+
Supply current IDD [mA]
0.05
Main system clock STOP mode
Subsystem clock oscillation
0.01
X1 X2 XT1 XT2
0.005
0.001 01234567
Crystal oscillator
4.19 MHz
22 pF 22 pF 22 pF22 pF
V
DD VDD
Crystal oscillator
32.768 kHz
Supply voltage VDD [V]
+
330 k
Note Does not include current flowing through EEPROM.
32
10
5.0
I
DD
vs VDD (Crystal oscillation)
µ
PD75P048
(T = 25 °C)
a
High-speed mode PCC = 0011
1.0
0.5
[mA]
DD
0.1
Supply current I
0.05
Medium-speed mode
Low-speed mode PCC = 0000
Main system clock HALT mode
Subsystem clock operation mode
Main system clock stopped
Subsystem clock HALT mode
Main system clock stopped
Main system clock STOP mode
Subsystem clock oscillation
PCC = 0010
+
+
+
0.01
X1 X2 XT1 XT2
0.005
0.001 01234567
Crystal oscillator
2.0 MHz
22 pF 22 pF 22 pF22 pF
V
DD
Crystal oscillator
32.768 kHz
V
DD
Supply voltage VDD [V]
Note Does not include current flowing through EEPROM.
330 k
33

7. PACKAGE DRAWINGS

64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
A
µ
PD75P048
321
K
I
J
H
G
NOTE
Each lead centerline is located within 0.17 mm (0.007 inch) of
1) its true position (T.P.) at maximum material condition.
Item "K" to center of leads when formed parallel.2)
F
M
D
N
L
B
C
ITEM MILLIMETERS INCHES
A B
C D
F G H
I J K L
M N
R
M
58.68 MAX.
1.78 MAX.
1.778 (T.P.)
0.50±0.10
0.9 MIN.
3.2±0.3
0.51 MIN.
4.31 MAX.
5.08 MAX.
19.05 (T.P.)
17.0 +0.10
0.25
–0.05
0.17
0~15°
2.311 MAX.
0.070 MAX.
0.070 (T.P.)
0.020
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.010
0.007 0~15°
P64C-70-750A,C-1
+0.004 –0.005
+0.004 –0.003
R
34
64 PIN PLASTIC QFP ( 14)
µ
PD75P048
A
B
48
49
64
F
1
G
H
M
I
P
N
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
33
32
detail of lead end
C
D
S
Q
17
16
J
K
M
L
ITEM MILLIMETERS INCHES
A
B
C
D
F
G
H
I
J
K
L
M
N
17.6±0.4
14.0±0.2
14.0±0.2
17.6±0.4
1.0
1.0
0.35±0.10
0.15
0.8 (T.P.)
1.8±0.2
0.8±0.2
+0.10
0.15
–0.05
0.15
P 2.55 0.100
Q
0.1±0.1
S 2.85 MAX. 0.112 MAX.
5°±5°
P64GC-80-AB8-2
0.693±0.016
+0.009
0.551
–0.008
+0.009
0.551
–0.008
0.693±0.016
0.039
0.039
+0.004
0.014
–0.005
0.006
0.031 (T.P.)
0.071±0.008
+0.009
0.031
–0.008
+0.004
0.006
–0.003
0.006
0.004±0.004
35

8. RECOMMENDED SOLDERING CONDITIONS

It is recommended that µPD75P048 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-1207). For other soldering methods and conditions, consult NEC.
Table 8-1 Soldering Conditions of Surface-Mount Type
µ
PD75P048GC-AB8: 64-pin plastic QFP ( 14 mm)
µ
PD75P048
Soldering Method Soldering Conditions
Infrared Reflow Package peak temperature: 235°C, IR35-00-2
time: 30 seconds max. (210°C min.), number of times: 2 max. <Caution> (1) Start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) Do not clean flux with water after first reflow.
VPS Package peak temperature: 215°C, VP15-00-2
time: 40 seconds max. (200°C min.), number of times: 1 max. <Caution> (1) Start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) Do not clean flux with water after first reflow.
Pin Partial Heating Pin temperature: 300°C max.,
time: 3 seconds max. (per side)
Symbol for Recommended Condition
Caution Do not use two or more soldering methods in combination (except the pin partial heating method).
Table 8-2 Soldering Conditions of Through-Hole Type
µ
PD75P048CW: 64-pin plastic shrink DIP (750 mil)
Soldering Method Soldering Conditions Wave soldering Soldering bath temperature: 260°C max.,
(lead parts only) time: 10 seconds max.,
Pin Partial Heating Pin temperature: 260oC max.,
time: 10 seconds max.
Caution The wave soldering must be performed at the lead part only. Note that the soldering must not be
directly contacted to the board.
36
µ
PD75P048

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are readily available to support development of systems using µPD75P048:
Hardware IE-75000-R
IE-75001-R IE-75000-R-EM EP-75028CW-R Common emulation probe commonly used with µPD75028CW EP-75028GC-R Emulation probe commonly used with µPD75028GC, provided with
PG-1500 PROM programmer PA-75P036CW PROM programmer adapter commonly used with µPD75P036. It is connected
PA-75P036GC PROM programmer adapter commonly used with µPD75P036GC. It is connected
Software IE Control Program Host machine
PG-1500 Controller PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A RA75X Relocatable IBM PC/ATTM (Refer to OS for IBM PC.) Assembler
Note 1. Maintenance product
2. Not provided with IE-75001-R.
3. Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software.
Note 1
Note 2
EV-9200GC-64
In-circuit emulator for 75X series
Emulation board for IE-75000-R and IE-75001-R
EV-9200GC-64, 64-pin conversion socket
to PG-1500.
to PG-1500.
Note 3
)
Remarks For development tools from other companies, refer to 75X Series Selection Guide (IF-1027).
OS for IBM PC
As OS for IBM PC, the followings are supported.
OS Version
PC DOS
MS-DOS Ver. 3.30 to Ver. 5.00A
IBM DOS
TM
TM
Ver. 5.02 to Ver. 6.1
Note 2
5.0/V
J5.02/V
Note 2
Note 1
Note 1. Version later than 5.0 have a task swap function, but this function cannot be used with this software.
2. This supports English mode only.
37

APPENDIX B. RELATED DOCUMENTS

Documents related to device
Document Document No.
User’s manual IEU-1278
Instruction list
75X series selection guide IF-1027
Documents related to development tools
Hardware IE-75000-R/IE-75001-R user’s manual EEU-1416
IE-75000-R-EM user’s manual EEU-1294
EP-750028CW-R user’s manual EEU-1314
EP-75028GC-R user’s manual EEU-1306
PG-1500 user’s manual EEU-1335
Software RA75X assembler package user’s manual Operation EEU-1346
PG-1500 controller user’s manual EEU1291
µ
PD75P048
Doument Document No.
Language EEU-1343
Other related documents
Document Document No.
Package manual IEI-1213
Semiconductor device - mounting maual IEI-1207
NEC semiconductor device quality grade IEI-1209
NEC semiconductor device reliabiliy quality control
Static electricity discharge (ESD) test
Semiconductor device quality guarantee guide MEI-1202
Product guide related to microcomputer - other manufacturers
Note The documents listed above are subject to change without notice. Be sure to use the latest document
for designing.
38
µ
PD75P048
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immedi-
ately after power-on for devices having reset function.
39
[MEMO]
µ
PD75P048
NEC is manufacturing and selling the products under microcomputer (with on-chip EEPROM) patent license with the BULL CP8. This product should not be used for IC cards (SMART CARD).
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation.
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