1.1 PORT PINS ··········································································································································6
Note The circle () indicates the Schmitt trigger input.
Remark MFT: Multi-Function Timer
8
1.2 NON-PORT PINS (2/2)
µ
PD75P048
Pin Name
X1, X2
XT1, XT2
RESET
MD0 - MD3
Note 2
VPP
VDD
VSS
Input/
Output
Input
Input
Input
I/O
–
–
–
Shared
Pin
–
–
–
P30 - P33
–
–
–
Function
Crystal/ceramic resonator connection for main
system clock generation. When external clock
signal is used, it is applied to X1, and its
reverse phase signal is applied to X2.
Crystal connection for subsystem clock
generation. When external clock signal is
used, it is applied to XT1, and its reverse
phase signal is applied to XT2. XT1 can be
used as a 1-bit input (test).
System reset input
Operation mode selection pins during the
PROM write/verify cycles.
Normally connected to VDD directly; +12.5 V is
applied as the programming voltage during the
PROM write/verify cycles.
Positive power supply
GND potential
When Reset
–
–
–
Input
–
–
–
Note 1. The circle () indicates the Schmitt trigger input.
2. The VPP should be connected to VDD directly in normal operation mode. If VPP and VDD pins are not
µ
connected, the
PD75P048 does not operate correctly.
I/O Circuit
Note 1
Type
–
–
B
E-B
–
–
–
9
1.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuit of each µPD75P048 pin is shown below in a simplified manner.
Type A (For Type E-B)
Type D (For Type E-B, F-A)
µ
PD75P048
(1/3)
Type B
VDD
Data
P-ch
IN
N-ch
CMOS input buffer
Type E-B
IN
Output
disable
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
Reference voltage
(from voltage tap of
series resistor string)
–
IN instruction
AVDD
AVSS
11
Type Z-A
AVREF+
AVREF–
Reference voltage
(3/3)
µ
PD75P048
12
µ
PD75P048
2. DIFFERENCES BETWEEN THE µPD75P048 AND THE µPD75048
The µPD75P048 is a One-Time PROM version of the µPD75048. The µPD75P048 has the same CPU and
internal hardwares. Table 2-1 shows the differences between the µPD75P048 and the µPD75048. Bear in mind
the differences between these two products when debugging or developing on an experimental basis your
application system by using the one-time PROM model, and then mass-producing the application system by
using the mask ROM model.
µ
Details for the CPU functions and internal hardwares are available in
µ
Table 2-1 Differences between the
Program Memory
Pull-up Resistors
Pull-Down Resistors
XT1 Feedback Resistor
Pin Connection
Electrical Specification
Other
Items
Ports 0 to 3 and 6 to 8
Ports 4, 5 and 10
Port 9
60 - 63 (SDIP)
5 - 8 (QFP)
16 (SDIP)
25 (QFP)
PD75P048 and the µPD75048
µ
PD75P048
One-time PROMMask ROM
N/AMask-option
On-chipMask-option
P33/MD3 - P30/MD0P33 - P30
VPPIC
Current dissipation differs. For details,
refer to Data Sheet of each model.
Circuit scale and mask layout differ.
Consequently, noise immunity and noise
radiation differ.
PD75048 User’s Manual (IEU-1278).
µ
PD75048
• 0000H to 1F7FH
• 8064 × 8 bits
Software-selectable
Software-selectable
★
★
★
Note The noise immunity and noise radiation of the PROM and mask ROM models differ. To replace the PROM
mode, which has been used for experimental production of your application system with the mask ROM
model for mass production of the application system, be sure to perform thorough evaluation by using
the CS model (not ES model) of the mask ROM model.
13
★
µ
PD75P048
3. PROM (PROGRAM MEMORY) WRITE AND VERIFY
The µPD75P048 contains 8064 bytes of PROM. The following table shows the pin functions during the write
and verify cycles. Note that it is not necessary to enter an address, because the address is updated by pulsing
the X1 clock pins.
Normally 2.7 to 6 V; 12.5 V is applied during write/verify
After a write/verify write, the X1 and X2 clock pins are
pulsed. The inverted signal of the X1 should be input to the
X2.
Note that these pins are also pulsed during a read.
Operation mode selection pins.
8-bit data input/output pins for write and verify
Supply voltage.
Normally 2.7 to 6 V; 6 V is applied during write/verify
Function
Caution The µPD75P048CW/GC do not have a UV erase window, thus the PROM contents cannot be erased
with ultra-violet ray.
3.1 PROM WRITE AND VERIFY OPERATION MODE
When 6 V and 12.5 V are applied to the V
DD and VPP pins, respectively, the PROM is placed in the write/verify
mode. The operation is selected by the MD0 to MD3 pins, as shown in the table.
The other pins should be returned to VSS potential via pull-down resistors.
VPP
+12.5 V
Operation Mode Specification
VDD
+6 V
MD0
H
L
L
H
MD1
L
H
L
×
MD2
H
H
H
H
MD3
L
H
H
H
Clear program memory address to 0
Write mode
Verify mode
Program inhibit
Operation Mode
14
×: Don’t care.
µ
PD75P048
3.2 PROM WRITE PROCEDURE
PROMs can be written at high speed using the following procedure: (see the following figure)
(1) Pull unused pins to V
SS through resistors. Set the X1 pin low.
(2) Supply 5 volts to the VDD and VPP pins.
(3) Wait for 10 µs.
(4) Select the zero clear program memory address mode.
(5) Supply 6 volts to the V
DD and 12.5 volts to the VPP pins.
(6) Select the program inhibit mode.
(7) Write data in the 1 ms write mode.
(8) Select the program inhibit mode.
(9) Select the verify mode. If the data is correct, proceed to step (10). If not, repeat steps (7), (8) and (9).
(10) Perform one additional write (duration of 1 ms × number of writes at (7) to (9)).
(11) Select the program inhibit mode.
(12) Apply four pulses to the X1 pin to increment the program memory address by one.
(13) Repeat steps (7) to (12) until the end address is reached.
(14) Select the zero clear program memory address mode.
(15) Return the V
DD and VPP pins back to + 5 volts.
(16) Turn off the power.
The following figure shows steps (2) to (12).
X repetition
WriteVerifyAdditional write
VPP
VPP
VDD
VDD+1
VDD
VDD
X1
P40-P43
P50-P53
MD0
(P30)
Input data
Output
data
Address
increment
Input data
MD1
(P31)
MD2
(P32)
MD3
(P33)
15
µ
PD75P048
3.3 PROM READ PROCEDURE
The PROM contents can be read in the verify mode by using the following procedure: (see the following
figure)
(1) Pull unused pins to V
SS through resistors. Set the X1 pin low.
(2) Supply 5 volts to the VDD and VPP pins.
µ
(3) Wait for 10
s.
(4) Select the clear program memory address mode.
(5) Supply 6 volts to the VDD and 12.5 volts to the VPP pins.
(6) Select the program inhibit mode.
(7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored
in one address.
(8) Select the program inhibit mode.
(9) Select the clear program memory address mode.
(10) Return the V
DD and VPP pins back to + 5 volts.
(11) Turn off the power.
The following figure shows steps (2) to (9).
VPP
VPP
VDD
VDD+1
VDD
VDD
X1
P40-P43
P50-P53
MD0
(P30)
MD1
(P31)
MD2
(P32)
“L”
Output data
Output data
16
MD3
(P33)
µ
PD75P048
4. SCREENING OF ONE-TIME PROM MODEL
Because of their structure, the one-time PROM models (µPD75P48CW and µPD75P48GC-AB8) cannot be
fully tested by NEC before shipment. It is therefore recommended that you implement screening to verify
the PROM after necessary data have been written to it, and after the PROM has been stored at high temperature
under the following conditions:
Storage TemperatureStorage Time
125 ˚C24 hours
★
17
5. ELECTRICAL SPECIFICATIONS
★
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
ParameterSymbolConditionsRatingsUnit
Supply VoltageVDD-0.3 to +7.0V
Input VoltageVI1Other than ports 4, 5, 10-0.3 to VDD+0.3V
VI2Ports 4, 5, 10w/pull-up-0.3 to VDD+0.3
Output VoltageVO-0.3 to VDD+0.3V
High-Level OutputIOH1 pin-10mA
Current
Low-Level OutputIOL
Current
Operating TemperatureTopt-10 to +70°C
Storage TemperatureTstg-65 to +150°C
Note
µ
PD75P048
resistor
Open drain-0.3 to +11V
All pins-30mA
Ports 0, 3, 4, 5Peak30mA
1 pin
Other than ports 0, 3, 4, 5Peak20mA
1 pin
Total of ports 0, 3 - 9, 11Peak170mA
Total of ports 0, 2, 10Peak30mA
rms15mA
rms5mA
rms120mA
rms20mA
V
Note rms = Peak value x √Duty
Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality
of the product may be degraded. The absolute maximum rating therefore specifies the upper or
lower limit of the value at which the product can be used without physical damages. Be sure not
to exceed or fall below this value when using the product.
EEPROM RATINGS (T
ParameterSymbolConditionsRatingsUnit
Write Times—100,000times
Data Retention Time—10years
a = -10 to +70°C, VDD = 2.7 to 6.0 V)
CAPACITANCE (Ta = 25°C, VDD = 0 V)
ParameterSymbolConditionsMIN.TYP.MAX.Unit
Input CapacitanceCI f = 1 MHz15pF
Output CapacitanceCOPins other than those measured are at 0 V15pF
Input/OutputCIO
15pF
18
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(Ta = -10 to +70°C, VDD = 2.7 to 6.0 V)
µ
PD75P048
Oscillator
CeramicOscillationVDD = oscillation
CrystalOscillation
External ClockX1 input frequency
Recommended
Constants
X1X2
C1C2
VDD
X1X2
C1C2
VDD
X1X2
µ
PD74HCU04
ItemConditionsMIN.TYP.MAX.Unit
Note 2
Note 2
Note 1
Note 1
voltage range
MIN. value of
oscillation voltage
range
2.05.0
2.04.195.0
2.05.0
Note 3
MHz
4ms
Note 3
MHz
10ms
30ms
Note 3
MHz
frequency(fX)
Oscillation stabiliza-After VDD come to
tion time
frequency (fX)
Oscillation stabiliza-VDD = 4.5 to 6.0 V
tion time
DATA RETENTION TIMING (releasing STOP mode by RESET)
Internal reset operation
HALT mode
STOP mode
Data retention mode
DD
V
STOP instruction
execution
RESET
VDDDR
tSREL
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
µ
PD75P048
tWAIT
Operation
mode
DD
V
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
VDDDR
HALT mode
Operation
mode
tSREL
tWAIT
31
★
6. PERFORMANCE CURVE (REFERENCE VALUE)
10
DD vs VDD (Crystal oscillation)
I
µ
PD75P048
(T = 25 °C)
a
5.0
1.0
0.5
0.1
High-speed mode PCC = 0011
Medium-speed mode
Low-speed mode PCC = 0000
Main system clock
HALT mode
Subsystem clock operation mode
Main system lock stopped
Main system clock stopped
Subsystem clock HALT mode
PCC = 0010
+
+
Supply current IDD [mA]
0.05
Main system clock STOP mode
Subsystem clock oscillation
0.01
X1X2XT1XT2
0.005
0.001
01234567
Crystal
oscillator
4.19 MHz
22 pF22 pF22 pF22 pF
V
DDVDD
Crystal
oscillator
32.768 kHz
Supply voltage VDD [V]
+
330 k
Ω
Note Does not include current flowing through EEPROM.
32
10
5.0
I
DD
vs VDD (Crystal oscillation)
µ
PD75P048
(T = 25 °C)
a
High-speed mode PCC = 0011
1.0
0.5
[mA]
DD
0.1
Supply current I
0.05
Medium-speed mode
Low-speed mode PCC = 0000
Main system clock
HALT mode
Subsystem clock operation mode
Main system clock stopped
Subsystem clock HALT mode
Main system clock stopped
Main system clock STOP mode
Subsystem clock oscillation
PCC = 0010
+
+
+
0.01
X1X2XT1XT2
0.005
0.001
01234567
Crystal
oscillator
2.0 MHz
22 pF22 pF22 pF22 pF
V
DD
Crystal
oscillator
32.768 kHz
V
DD
Supply voltage VDD [V]
Note Does not include current flowing through EEPROM.
330 k
Ω
33
7. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
6433
A
µ
PD75P048
321
K
I
J
H
G
NOTE
Each lead centerline is located within 0.17 mm (0.007 inch) of
1)
its true position (T.P.) at maximum material condition.
Item "K" to center of leads when formed parallel.2)
F
M
D
N
L
B
C
ITEM MILLIMETERSINCHES
A
B
C
D
F
G
H
I
J
K
L
M
N
R
M
58.68 MAX.
1.78 MAX.
1.778 (T.P.)
0.50±0.10
0.9 MIN.
3.2±0.3
0.51 MIN.
4.31 MAX.
5.08 MAX.
19.05 (T.P.)
17.0
+0.10
0.25
–0.05
0.17
0~15°
2.311 MAX.
0.070 MAX.
0.070 (T.P.)
0.020
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.010
0.007
0~15°
P64C-70-750A,C-1
+0.004
–0.005
+0.004
–0.003
R
34
64 PIN PLASTIC QFP ( 14)
µ
PD75P048
A
B
48
49
64
F
1
G
H
M
I
P
N
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
33
32
detail of lead end
C
D
S
Q
17
16
J
K
M
L
ITEMMILLIMETERSINCHES
A
B
C
D
F
G
H
I
J
K
L
M
N
17.6±0.4
14.0±0.2
14.0±0.2
17.6±0.4
1.0
1.0
0.35±0.10
0.15
0.8 (T.P.)
1.8±0.2
0.8±0.2
+0.10
0.15
–0.05
0.15
P2.550.100
Q
0.1±0.1
S2.85 MAX.0.112 MAX.
5°±5°
P64GC-80-AB8-2
0.693±0.016
+0.009
0.551
–0.008
+0.009
0.551
–0.008
0.693±0.016
0.039
0.039
+0.004
0.014
–0.005
0.006
0.031 (T.P.)
0.071±0.008
+0.009
0.031
–0.008
+0.004
0.006
–0.003
0.006
0.004±0.004
35
★
8. RECOMMENDED SOLDERING CONDITIONS
It is recommended that µPD75P048 be soldered under the following conditions. For details on the recommended
soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-1207). For
other soldering methods and conditions, consult NEC.
Table 8-1 Soldering Conditions of Surface-Mount Type
time: 30 seconds max. (210°C min.),
number of times: 2 max.
<Caution>
(1) Start second reflow after device temperature
(which has risen because of first reflow) has returned to
room temperature.
(2) Do not clean flux with water after first reflow.
VPSPackage peak temperature: 215°C,VP15-00-2
time: 40 seconds max. (200°C min.),
number of times: 1 max.
<Caution>
(1) Start second reflow after device temperature
(which has risen because of first reflow) has returned to
room temperature.
(2) Do not clean flux with water after first reflow.
Pin Partial HeatingPin temperature: 300°C max.,—
time: 3 seconds max. (per side)
Symbol for Recommended
Condition
Caution Do not use two or more soldering methods in combination (except the pin partial heating method).
Table 8-2 Soldering Conditions of Through-Hole Type
Caution The wave soldering must be performed at the lead part only. Note that the soldering must not be
directly contacted to the board.
36
µ
PD75P048
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are readily available to support development of systems using µPD75P048:
HardwareIE-75000-R
IE-75001-R
IE-75000-R-EM
EP-75028CW-RCommon emulation probe commonly used with µPD75028CW
EP-75028GC-REmulation probe commonly used with µPD75028GC, provided with
PG-1500PROM programmer
PA-75P036CWPROM programmer adapter commonly used with µPD75P036. It is connected
PA-75P036GCPROM programmer adapter commonly used with µPD75P036GC. It is connected
SoftwareIE Control ProgramHost machine
PG-1500 ControllerPC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A
RA75X RelocatableIBM PC/ATTM (Refer to OS for IBM PC.)
Assembler
Note 1. Maintenance product
2. Not provided with IE-75001-R.
3. Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software.
Note 1
Note 2
EV-9200GC-64
In-circuit emulator for 75X series
Emulation board for IE-75000-R and IE-75001-R
EV-9200GC-64, 64-pin conversion socket
to PG-1500.
to PG-1500.
Note 3
)
★
Remarks For development tools from other companies, refer to 75X Series Selection Guide (IF-1027).
OS for IBM PC
As OS for IBM PC, the followings are supported.
OSVersion
PC DOS
MS-DOSVer. 3.30 to Ver. 5.00A
IBM DOS
TM
TM
Ver. 5.02 to Ver. 6.1
Note 2
5.0/V
J5.02/V
Note 2
Note 1
Note 1. Version later than 5.0 have a task swap function, but this function cannot be used with this software.
Product guide related to microcomputer - other manufacturers—
Note The documents listed above are subject to change without notice. Be sure to use the latest document
for designing.
38
µ
PD75P048
NOTES FOR CMOS DEVICES
1PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.
2HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered
to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.
3STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immedi-
ately after power-on for devices having reset function.
39
[MEMO]
µ
PD75P048
NEC is manufacturing and selling the products under microcomputer (with
on-chip EEPROM) patent license with the BULL CP8.
This product should not be used for IC cards (SMART CARD).
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation.
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