NEC UPD72862GC-9EU Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

PD72862

µµµµ

IEEE1394 OHCI HOST CONTROLLER

The µPD72862 is IEEE1394 OHCI-Link controller. The µPD72862 complies with the P1394a draft 2.0

specifications and works up to 400 Mbps.

It supports both of the Cardbus interface and the PCI bus interface.

FEATURES

• Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0

• Compliant with protocol enhancement as defined in P1394a draft 2.0

• Modular 32-bit host interface compliant to PCI Specification release 2.1

• Supports PCI-Bus Power Management Interface Specification release 1.0

• Supports Cardbus

• Equipped CIS register

• Cycle Master and Isochronous Resource Manager capable

• Compatible to PHY Layer implementation of 100/200/400 Mbps via 2/4/8-bit data interface

• Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes)

• 32-bit CRC generation and checking for receive/transmit packets

• 4-isochronous transmit DMAs and 4-isochronous receive DMAs supported

• Support both IEEE1394-1995 compliant PHY and P1394a compliant PHY

• Internal control and operational registers direct-mapped to PCI configuration space

• 2-wire Serial EEPROMTM interface supported

ORDERING INFORMATION

Part number Package

PD72862GC-9EU 100-pin plastic TQFP (Fine pi tch) (14 x 14)

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. S14265EJ2V0DS00 (2nd edition) Date Published December 1999 NS CP (K) Printed in Japan

The mark

★★★★

shows major revised points.

1999

Firewarden™ ROADMAP

µµµµ

Firewarden Series

PD72862

IEEE1394-1995

Core Development

Hotline

Link

1997

OHCI Link

1998

PD72860

OHCI Link

PD72862

OHCI Link

PD72861

1 Chip

OHCI+PHY

PD72870A

1 Chip

OHCI+PHY

PD72870

800M/1.6G

p1394.b Link

PD7286x

1999 2000

PC Application

2001

Data Sheet S14265EJ2V0DS00

BLOCK DIAGRAM

(

)

Serial ROM Interface

µµµµ

PD72862

PCI Controller Interface

(Master, Parity Check & Generator)

Byte

Buf

Swap

Cardbus Interface

PCI Bus /

OPCIBUS_AR B

PCIS_CNT

PCI-DMA

OPCI Internal Bus

PCIS Bus

PCICFG

IOREG

PCI Slave Bus

IRDMA0-

ATDMA : Asynchronous Transmit DMA ATF : Asynchronous Transmit FIFO CIS : CIS Register

CSR : Control and Status Registers IOREG : IO Registers

IRDMA : Isochronous Receive DMA ITCF : Isochronous Transmit Control FIFO ITDMA : Isochronous Transmit DMA ITF : Isochronous Transmit FIFO OPCIBUS_ARB : OPCI Internal Bus Arbitration PAU : Physical Response and Request Unit PCICFG : PCI Configuration Registers PCIS_CNT : PHY Control Isochronous Control PFCOMM : Pre Fetch Command FIFO RCF : Receive Control FIFO RF : Receive FIFO SFIDU : Self-ID DMA

CSR

(CIS)

ATDMA

PAU GRSU GRQU

ITDMA

IRDMA3

SFIDU

PFCOMM

Byte

Swap

Byte

Swap

ATF

ITF

ITCF

Byte

Swap

RCF

IOREG

Link Layer

Core

PHY/Link Interface

Data Sheet S14265EJ2V0DS00

µµµµ

PD72862

PIN CONFIGURATION (Top View)

Though the current implementation of the µPD72862 includes signal pins for debugging and testing purpose, the

package remains a cost efficient 100-pin TQFP package.

• 100-pin plastic TQFP (Fine pitch) (14 x 14)

3.3V V AD21 AD20 AD19 AD18

V AD17 AD16

CBE2

FRAME

PCI V

IRDY

TRDY

DEVSEL

STOP PERR SERR

PAR

CBE1

AD15 AD14 AD13 AD12

3.3V V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

AD22

AD23

IDSEL

3.3V V

CBE3

AD24

PCI V

AD25

AD26

AD28

AD27

AD29

AD30

VSSAD31

REQ

GNT

PCLK

INTA

PRST

PME

CLKRUN

485049

VSSLINKON

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

3.3V V LPS LREQ SCLK

V CTL0 CTL1 DIRECT D0 D1 D2 D3

V D4 D5 D6 D7 NC GROM_EN GROM_SCL GROM_SDA CARD_ON NC NC

3.3V V

AD10

AD11

AD9

AD8

AD5

AD6

AD7

CBE0

Data Sheet S14265EJ2V0DS00

AD4

PCI V

AD3

AD2

AD1

AD0

IC(H)

PIN_EN

IC(L)

CIS_ON

IC(L)

PIN NAME

AD0-AD31 : PCI Multiplexed Address and Data CARD_ON : PCI/Card Select

CBE0-CBE3 : Command/Byte Enables CIS_ON : CIS Register ON CLKRUN : PCICLK Running CTL0, CTL1 : PHY/Link Bi-directional Control DEVSEL : Device Select DIRECT : Auxiliary PHY/Link Signal D0-D7 : PHY/Link Bi-directional Data FRAME : Cycle Frame GNT : Bus_master Grant GROM_EN : Serial EEPROM Enable GROM_SCL : Serial EEPROM Clock Output GROM_SDA : Serial EEPROM Data Input / Output IC (H) : Internally Connected (High Clamped) IC (L) : Internally Connected (Low Clamped) IDSEL : ID Select INTA : Interrupt IRDY : Initiator Ready LINKON : Link-On Request LPS : Link Power Status LREQ : PHY/Link Request NC : Non-Connection PAR : Parity PCLK : PCI Clock PERR : Parity Error PIN_EN : Pin Enable Input PME : PME Output PRST : Reset REQ : Bus_master Request SCLK : PHY Clock SERR : System Error STOP : PCI Stop TRDY : Target Ready V

: Supply Voltage : Ground

µµµµ

PD72862

Data Sheet S14265EJ2V0DS00

µµµµ

PD72862

CONTENTS

1. PIN FUNCTIONS.....................................................................................................................................8

1.1 PCI Bus Interface Signals: (52 pins) ..............................................................................................8

1.2 PCI/Cardbus Select Signals: (2 pins).............................................................................................9

1.3 PHY/Link Interface Signals: (15 pins) ..........................................................................................10

1.4 Serial ROM Interface Signals: (3 pins).........................................................................................10

1.5 Miscellaneous Signal: (1 pin) .......................................................................................................10

1.6 IC: (3 pins) ......................................................................................................................................10

1.7 NC: (5 pins).....................................................................................................................................10

1.8 V

1.9 V

: (8 pins)....................................................................................................................................10

: (11 pins).................................................................................................................................. 10

2. REGISTER DESCRIPTIONS.................................................................................................................11

2.1 PCI Bus Mode Configuration Register ( CARD_ON=Low )........................................................ 11

2.1.1 Offset_00 VendorID Register.............................................................................................................12

2.1.2 Offset_02 DeviceID Register..............................................................................................................12

2.1.3 Offset_04 Command Register............................................................................................................12

2.1.4 Offset_06 Status Register..................................................................................................................13

2.1.5 Offset_08 Revision ID Register..........................................................................................................14

2.1.6 Offset_09 Class Code Register..........................................................................................................14

2.1.7 Offset_0C Cache Line Size Register..................................................................................................14

2.1.8 Offset_0D Latency Timer Register.....................................................................................................14

2.1.9 Offset_0E Header Type Register.......................................................................................................14

2.1.10 Offset_0F BIST Register...................................................................................................................14

2.1.11 Offset_10 Base Address 0 Register.................................................................................................15

2.1.12 Offset_2C Subsystem Vendor ID Register.......................................................................................15

2.1.13 Offset_2E Subsystem ID Register....................................................................................................15

2.1.14 Offset_30 Expansion Rom Base Address Register..........................................................................15

2.1.15 Offset_34 Cap_Ptr Register.............................................................................................................15

2.1.16 Offset_3C Interrupt Line Register.....................................................................................................16

2.1.17 Offset_3D Interrupt Pin Register......................................................................................................16

2.1.18 Offset_3E Min_Grant Register.........................................................................................................16

2.1.19 Offset_3F Max Lat Register .............................................................................................................16

2.1.20 Offset_40 PCI_OHCI_Control Register............................................................................................16

2.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register...................................................................................17

2.1.22 Offset_62 Power Management Capabilities Register.......................................................................17

2.1.23 Offset_64 Power Management Control/Status Register...................................................................17

2.2 CardBus Mode Configuration Register ( CARD_ON=High )...................................................... 18

2.2.1 Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers)............................................19

2.2.2 Offset_28 Cardbus CIS Pointer..........................................................................................................20

2.2.3 Offset_80 CIS Area............................................................................................................................20

3. SERIAL ROM INTERFACE.................................................................................................................. 21

3.1 Serial EEPROM Register ............................................................................................................... 21

3.2 Serial EEPROM Register Description ..........................................................................................21

3.3 Load Control................................................................................................................................... 25

3.4 Programming Sequence Example................................................................................................25

Data Sheet S14265EJ2V0DS00

µµµµ

PD72862

4. ELECTRICAL SPECIFICATIONS.........................................................................................................27

5. APPLICATION CIRCUIT EXAMPLE....................................................................................................30

6. PACKAGE DRAWING .......................................................................................................................... 31

7. RECOMMENDED SOLDERING CONDITIONS...................................................................................32

Data Sheet S14265EJ2V0DS00

1. PIN FUNCTIONS

1.1 PCI Bus Interface Signals: (52 pins)

Name I/O Pin No. I

PAR I/O 18

AD0-AD31 I/O 2-5, 7, 8,

21-24, 27-30, 33-36, 39-42, 86-91, 93, 94, 98, 99

CBE0-CBE3 I 9, 20,

32, 95

FRAME I/O 10

PCI/Cardbus

★★★★

TRDY I/O 13

IRDY I/O 12

REQ O 84

GNT I 83 - 5/3.3

IDSEL I 96 - 5/3.3

PCI/Cardbus

★★★★

DEVSEL I/O 14

STOP I/O 15

PCI/Cardbus

Volts(V) Function

5/3.3

- 5/3.3

5/3.3

µµµµ

PD72862

(1/2)

Parity

is even parity across AD0-AD31 and CBE0-CBE3. It is an input when AD0-AD31 is an input; it is an output when AD0-AD31 is an output.

PCI Multiplexed Address and Data

Command/Byte Enabl es

enables.

Cycle Frame

beginning and is kept asserted duri ng the burst cycle. If Cardbus mode (CARD_ON = 1), this pi n i s should be pulled up to

Target Ready

transaction is ready t o be completed.

Initiator Ready

complete the current data phas e. During a write, its assertion indicates that the ini tiator is driving valid dat a onto the data bus. During a read, its assertion i ndi cates that the initiator is ready to accept data from the currently-addressed target.

Bus_master Request

wants to become a bus mast er.

Bus_master Grant

has been granted.

ID Select

selected for configurat i on read/write transaction during the phas e of device initialization. If Cardbus mode (CARD_ON = 1), this pi n i s should be pulled up to

Device Select

has decoded its address as the target of the current acc ess.

PCI Stop

requesting the current bus mas ter to stop the transacti on.

is asserted by the initiator to indicate the cycle

indicates that the c urrent data phase of the

indicates that the c urrent bus master is ready to

when actively driven, i ndi cates that the IUHC is chip-

when actively driven, i ndi cates that the driving dev i ce

when actively driven, i ndi cates that the target is

are multiplexed Bus Commands & Byte

indicates to the bus arbiter that this device

indicates to this device that access to the bus

Data Sheet S14265EJ2V0DS00

Name I/O Pin No. I

PME O 79

PCI/Cardbus

Volts(V) Function

5/3.3

PME Output

for power management enable.

µµµµ

PD72862

(2/2)

★★★★

CLKRUN I/O 78

INTA O 80 PERR I/O 16

SERR O 17

PRST I 81 - 5/3.3 PCLK I 82 - 5/3.3

PCI/Cardbus

PCI/Cardbus PCI/Cardbus

PCI/Cardbus

5/3.3

5/3.3 5/3.3

5/3.3

Caution

PCICLK Running

output, to request starting or speeding up clock.

Interrupt Parity Error

transactions, except a Special Cycle. It is an output when AD0AD31 and PAR are both inputs. It is an input when AD0-AD31 and PAR are both outputs.

System Error

errors during the Special Cycle, or any other system error where the effect can be catas t rophi c. When reporting address parity errors , it is an output.

Reset PCI Clock

The PME pin is not an N- c ha nne l open drain str uc t ure pin. Therefore, when using S3, S4, S5 state in ACPI, a circuit that can separate between the power supply and the PME pin externally is needed.

ACPI: Advanced Configuration and Power Interface.

Please refer to ACPI Specification.

as input, to determine the status of PCLK; as

the PCI interrupt request A .

is used for reporting data parity errors during all PCI

is used for reporting address parity errors, data parity

PCI reset

33 MHz system bus clock.

1.2 PCI/Cardbus Select Signals: (2 pins)

Name I/O Pin No. I CARD_ON I 54 - 3.3 CIS_ON I 45 - 3.3

Volts(V) Function

PCI/Card Select CIS Register ON

CARD_ON CIS_ON CIS PME

(1:Cardbus, 0:PCI bus)

0 0 1

1 0 X

off on on

PME CSTSCHG CSTSCHG

Data Sheet S14265EJ2V0DS00

1.3 PHY/Link Interface Signals: (15 pins)

µµµµ

PD72862

Name I/O Pin No. I

D0-D7 I/O 59-62,

64-67 CTL0,CTL1 I/O 69, 70 9mA 3.3 LREQ O 73 9mA 3.3 LINKON I 77 - 3.3 LPS O 74 9mA 3.3 SCLK I 72 - 3.3 DIRECT I 68 - 3.3

9mA 3.3

Volts(V) Function

1.4 Serial ROM Interface Signals: (3 pins)

Name I/O Pin No. I GROM_SDA I/O 55 6mA 3.3 GROM_SCL O 56 6mA 3.3 GROM_EN I 57 - 3.3

Volts(V) Function

PHY/Link Bi-directional Data

PHY/Link Bi-directional Control PHY/Link Request Link-On Request Link Power Status PHY Clock Auxiliary PHY/Link Signal

interconnection between Link and PHY has isolation (‘low’: I SObarrier; ‘high’: no ISO-barrier).

Serial EEPROM Data Input / Output Serial EEPROM Clock Output Serial EEPROM Enable

Load disabled)

(ISO-barrier supported)

49.152 MHz (ISO-barrier supported)

(ISO-barrier supported)

is used to determine whether the

(‘high’: GUID Load enabled; ‘low’: GUID

1.5 Miscellaneous Signal: (1 pin)

Name I/O Pin No. I PIN_EN I 43 - 5/3.3

Volts(V) Function

1.6 IC: (3 pins)

Name I/O Pin No. I IC(H) I 44 - 3.3 IC(L) I 46, 47 - 3.3

Volts(V) Function

1.7 NC: (5 pins)

Name I/O Pin No. I NC - 48, 49,

52, 53, 58

Volts(V) Function

1.8 VDD: (8 pins)

VDD (5 V PCI or 3.3 V PCI) for PCI I/Os: 11, 37, 92 VDD 3 V for digital core & PHY/Link I/Os: 1, 25, 51, 75, 97

Pin Enable Input

Internally Connected Internally Connected

Non- Connection

Leave them unconnected.

(High clamped)

(High clamped) (Low clamped)

(Open)

1.9 VSS: (11 pins)

VSS : 6, 19, 26, 31, 38, 50, 63, 71, 76, 85, 100

Data Sheet S14265EJ2V0DS00

2. REGISTER DESCRIPTIONS

2.1 PCI Bus Mode Configuration Register ( CARD_ON=Low )

µµµµ

PD72862

31 24 23 16 15 08 07 00

DeviceID VendorID

Status Command

Class Code Revision ID

BIST Header Type Latency Timer Cache Line Size

Base Address 0 (OHCI Regis ters)

Base Address 1 Base Address 2 Base Address 3 Base Address 4 Base Address 5

CardBus CIS Pointer

Subsystem ID Subsystem Vendor ID

Expansion Rom Base Addres s Register

000000H Cap_Ptr

00000000H

Max_Lat Min_Gnt Interrupt Pin Interrupt Line

PCI_OHCI_Control

00000000H 00000000H

00000000H Diagnostic register0 Diagnostic register1 Diagnostic register2 Diagnostic register3

Power Management Capabilities Next_It em_P t r Cap_ID

Data PMCSR_BSE Power Management Control/Status

00000000H

User Area (GENERAL_RegisterA) User Area (GENERAL_RegisterB) User Area (GENERAL_RegisterC) User Area (GENERAL_RegisterD)

00000000H

00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H

FCH

Data Sheet S14265EJ2V0DS00

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