NEC UPD16681W-011, UPD16681P-011 Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
µ
µ µ
PD16681
LCD CONTROLLER/DRIVER FOR DOT MATRIX DISPLAY OF JIS LEVEL 1
AND JIS LEVEL 2 KANJI SETS
DESCRIPTION
The µPD16681 is a single-chip controller driver that can display Japanese text; including JIS Level 1 kanji, JIS Level
2 kanji, hiragana, and katakana. Each chip can display up to four lines containing up to eight full width characters (11
x 12 dots), or up to four lines containing up to 16 half width characters (5 x 12 dots), as well 96 pictographs.
FEATURES
LCD controller/driver for dot matrix display of JIS Level 1 and JIS Level 2 kanji sets
•
On-chip ROM for character generation
•
JIS Level 1 + Level 2 kanji (11 x 12 dots) : 6,355 characters
−
JIS non-kanji characters (11 x 12 dots) : 453 characters
−
Other characters (symbols, etc.) (11 x 12 dots): 256 characters
−
Half width alphanumeric characters (5 x 12 dots) : 192 characters
−
On-chip RAM for character generation
•
8 types (12 x 13 dots)
−
On-chip boost circuit : switchable between 3x and 4x modes
•
RAM for pictograph data displays : 96 bits
•
Outputs : 96 segments, 52 commons
•
Duty settings : 1/39 or 1/52
•
Switchable data inputs : serial or 8-bit parallel
•
On-chip divider resistor
•
Selectable bias settings (1/8 bias, 1/7 bias, or 1/6 bias)
•
On-chip oscillation circuit
•
ORDERING INFORMATION
Part number Package ROM code
PD16681W-011 Wafer Standard
µ
PD16681P-011 Chip (COG compliant) Standard
µ
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published November
Printed in Japan
S13104EJ5V0DS00(5th edition)
1999 NS CP(K)
The mark
★★★★
shows major revised points.
©
1999
1. BLOCK DIAGRAM
/RESET
INV
SEG
COM
INV
OSC
OSC
IN
Oscillation Circuit
OUT
OSC
µµµµ
PD16681
BRI
Timing Generator
E/SCK
D0/DATA
D
1
TEST
V
V
V
STB
to D
OUT
WS
DD
LCD
SS
Index
Register
RAM Address
Control
Register
Display Data RAM
Common
Driver
COM1 to COM
PCOM1,PCOM
51
2
Counter
I/O
Buffer
7
8
RAM Data
8
8
96 bits
Shift
Register
96 bits
Latch
Circuit
Segment
Driver
SEG1 to SEG
96
Register
8
8
Pictograph
Data RAM
84
Character
Generator
RAM
Address Formation Circuit
3
Full-width
Character
Generator
ROM
12
7
Half-width
Character
Generator
ROM
DA
CHA
+
C1 , C
+
C2 , C
+
C3 , C
V
EXT
Remark
2
D/A
Converter
−
1
−
2
−
3
DC/DC
Converter
AMP
IN(+)
/xxx indicates active low signals.
66
Display Attribute Control Circuit
Cursor Control
Circuit
OP Amp.
AMP
IN(−)
AMP
OUT
AMP
CHA
V
LC1
Data Sheet S13104EJ5V0DS00
6
6
Parallel/Serial Conversion Circuit
Smooth Scroll Control Circuit
LCD Voltage Generator
V
V
LC2
LCBS1
V
LC3
V
LCBS2
V
LCBS3
6
V
LC5
V
LC4
2. PIN CONFIGURATION (Pad Layout)
µµµµ
PD16681
Chip size : 2.80 x 10.48 mm
2
241
1
219
218
Y
X
82
83
Data Sheet S13104EJ5V0DS00
108
107
3
Table 2-1. Pad Layout
µµµµ
PD16681
PAD
Pin Name X (µm) Y (µm)
No.
PAD
No.
1 DUMMY1−1273 4800 61 DA
2V
LCBS1
3V
LCBS1
4V
LCBS2
5V
LCBS2
6V
LCBS3
7V
LCBS3
8AMP
OUT
9AMP
10 AMP
11 AMP
12 AMP
13 AMP
14 V
15 V
16 V
17 V
18 V
19 V
20 V
21 V
22 V
23 V
24 V
25 V
26 V
27 V
28 V
29 V
30 V
31 V
32
33
34
35 C1
36 C1
37 C1
38
39
40
41 C2
42 C2
43 C2
44
45
46
47 C3
48 C3
49 C3
50 V
51 V
52 V
53 V
54 V
55 V
56 V
57 V
58 V
59 V
60 V
OUT
IN(−)
IN(−)
IN(+)
IN(+)
LC5
LC5
LC5
LC4
LC4
LC4
LC3
LC3
LC3
LC2
LC2
LC2
LC1
LC1
LC1
LCD
LCD
LCD
+
C1
+
C1
+
C1
−
−
−
+
C2
+
C2
+
C2
−
−
−
+
C3
+
C3
+
C3
−
−
−
DD1
DD1
DD2
DD2
DD2
SS
SS
SS
SS
SS
EXT
1273 4680 62 AMP
−
1273 4560 63 SEG
−
1273 4440 64 COM
−
1273 4320 65 OSC
−
1273 4200 66 OSC
−
1273 4080 67 OSC
−
1273 3960 68 D
−
1273 3840 69 D
−
1273 3720 70 D
−
1273 3600 71 D
−
1273 3480 72 D
−
1273 3360 73 D
−
1273 3240 74 D
−
1273 3120 75 D
−
1273 3000 76 WS
−
1273 2880 77 STB
−
1273 2760 78 E/SCK
−
1273 2640 79 /RESET
−
1273 2520 80 TEST
−
1273 2400 81 DUMMY2−1273−4800 141 SEG
−
1273 2280 82 DUMMY3−1273−4920 142 SEG
−
1273 2160 83 DUMMY4−1120−5113 143 SEG
−
1273 2040 84 DUMMY5−1030−5113 144 SEG
−
1273 1920 85 COM
−
1273 1800 86 COM
−
1273 1680 87 COM
−
1273 1560 88 COM
−
1273 1440 89 COM
−
1273 1320 90 COM
−
1273 1200 91 COM
−
1273 1080 92 COM
−
1273 960 93 COM
−
1273 840 94 COM
−
1273 720 95 COM
−
1273 600 96 COM
−
1273 480 97 COM
−
1273 360 98 COM
−
1273 240 99 COM
−
1273 120 100 COM
−
1273 0 101 COM
−
1273−120 102 COM
−
1273−240 103 COM
−
1273−360 104 COM
−
1273−480 105 COM
−
1273−600 106 DUMMY6 950−5113 166 SEG
−
1273−720 107 DUMMY7 1040−5113 167 SEG
−
1273−840 108 DUMMY8 1273−4905 168 SEG
−
1273−960 109 COM
−
1273−1080 110 COM
−
1273−1200 111 COM
−
1273−1320 112 COM
−
1273−1440 113 DUMMY9 1273−4455 173 SEG
−
1273−1560 114 PCOM
−
1273−1680 115 SEG
−
1273−1800 116 SEG
−
1273−1920 117 SEG
−
1273−2040 118 SEG
−
1273−2160 119 SEG
−
1273−2280 120 SEG
−
Pin Name X (µm) Y (µm)
CHA
/DATA
0
1
2
3
4
5
6
7
CHA
INV
INV
IN
OUT
BRI
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
96
95
94
93
92
91
1273−2400 121 SEG
−
1273−2520 122 SEG
−
1273−2640 123 SEG
−
1273−2760 124 SEG
−
1273−2880 125 SEG
−
1273−3000 126 SEG
−
1273−3120 127 SEG
−
1273−3240 128 SEG
−
1273−3360 129 SEG
−
1273−3480 130 SEG
−
1273−3600 131 SEG
−
1273−3720 132 SEG
−
1273−3840 133 SEG
−
1273−3960 134 SEG
−
1273−4080 135 SEG
−
1273−4200 136 SEG
−
1273−4320 137 SEG
−
1273−4440 138 SEG
−
1273−4560 139 SEG
−
1273−4680 140 SEG
OUT
−
940−5113 145 SEG
−
850−5113 146 SEG
−
760−5113 147 SEG
−
670−5113 148 SEG
−
580−5113 149 SEG
−
490−5113 150 SEG
−
400−5113 151 SEG
−
310−5113 152 SEG
−
220−5113 153 SEG
−
130−5113 154 SEG
−
−40−
50−5113 156 SEG
140−5113 157 SEG
230−5113 158 SEG
320−5113 159 SEG
410−5113 160 SEG
500−5113 161 SEG
590−5113 162 SEG
680−5113 163 SEG
770−5113 164 SEG
860−5113 165 SEG
1273−4815 169 SEG
1273−4725 170 SEG
1273−4635 171 SEG
1273−4545 172 SEG
1273−4365 174 SEG
2
1273−4275 175 SEG
1273−4185 176 SEG
1273−4095 177 SEG
1273−4005 178 SEG
1273−3915 179 SEG
1273−3825 180 SEG
5113 155 SEG
PAD
Pin Name X (µm) Y (µm)
No.
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PAD
Pin Name X (µm) Y (µm)
1273−3735 181 SEG
1273−3645 182 SEG
1273−3555 183 SEG
1273−3465 184 SEG
1273−3375 185 SEG
1273−3285 186 SEG
1273−3195 187 SEG
1273−3105 188 SEG
1273−3015 189 SEG
1273−2925 190 SEG
1273−2835 191 SEG
1273−2745 192 SEG
1273−2655 193 SEG
1273−2565 194 SEG
1273−2475 195 SEG
1273−2385 196 SEG
1273−2295 197 SEG
1273−2205 198 SEG
1273−2115 199 SEG
1273−2025 200 SEG
1273−1935 201 SEG
1273−1845 202 SEG
1273−1755 203 SEG
1273−1665 204 SEG
1273−1575 205 SEG
1273−1485 206 SEG
1273−1395 207 SEG
1273−1305 208 SEG
1273−1215 209 SEG
1273−1125 210 SEG
1273−1035 211 COM
1273−945 212 COM
1273−855 213 COM
1273−765 214 COM
1273−675 215 COM
1273−585 216 COM
No.
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
26
25
24
23
22
21
1273 1665
1273 1755
1273 1845
1273 1935
1273 2025
1273 2115
1273 2205
1273 2295
1273 2385
1273 2475
1273 2565
1273 2655
1273 2745
1273 2835
1273 2925
1273 3015
1273 3105
1273 3195
1273 3285
1273 3375
1273 3465
1273 3555
1273 3645
1273 3735
1273 3825
1273 3915
1273 4005
1273 4095
1273 4185
1273 4275
1273 4365
1273 4455
1273 4545
1273 4635
1273 4725
1273 4815
1273−495 217 DUMMY10 1273 4905
1273−405 218 DUMMY11 1273 4995
1273−315 219 DUMMY12 950 5113
1273−225 220 COM
1273−135 221 COM
1273−45 222 COM
1273 45 223 COM
1273 135 224 COM
1273 225 225 COM
1273 315 226 COM
1273 405 227 COM
1273 495 228 COM
1273 585 229 COM
1273 675 230 COM
1273 765 231 COM
1273 855 232 COM
1273 945 233 COM
1273 1035 234 COM
1273 1125 235 COM
1273 1215 236 COM
1273 1305 237 COM
1273 1395 238 COM
1273 1485 239 COM
1273 1575 240 PCOM
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
860 5113
770 5113
680 5113
590 5113
500 5113
410 5113
320 5113
230 5113
140 5113
50 5113
40 5113
−
130 5113
−
220 5113
−
310 5113
−
400 5113
−
490 5113
−
580 5113
−
670 5113
−
760 5113
−
850 5113
−
940 5113
−
241 DUMMY13−1030 5113
4
Data Sheet S13104EJ5V0DS00
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Pin Symbol Pin Name Pad No. I/O Description
µµµµ
PD16681
V
V
V
V
V
C
C
C
DD
SS
LCD
LC1
LCBS1
+
1
, C
+
2
, C
+
3
, C
- V
- V
-
1
-
2
-
3
Logic power supply pin
Boost circuit power supply
pin
Logic ground
Driver ground
Driver power supply pins 29-31
LC5
Reference power supply
pins for driver
LCBS3
Bias value setting pins 2-7
Capacitor connection pins 32-49
50-54
55-59
14-28
Power supply pins for logic and boost circuit
−
Ground pins for logic and driver circui t
−
Power supply pins for driver. Output pin f or i nternal boost circuit.
−
Connect a 1-
F capacitor between these pins and the V
µ
for boosting.
If not using the internal boost circuit, a direct driver power supply
can be input.
These are reference power supply pins for the LCD driver.
−
Leave these pins open if an internal bias has been selected.
Connect a capacitor to ground.
When select i ng an i nt ernal bi as, the bias value can be changed
−
connecting these pins out side of the IC.
These are capacitor connecti on pi ns for the boost circuit.
−
Connect a 1-
F capacitor.
µ
SS
pins
Data Sheet S13104EJ5V0DS00
5
3.2 Logic System Pins
Pin Symbol Pin Name Pad No. I/O Description
WS Select word length 76 I Use this pin to select the word length. An 8-bit parallel interface is used
for high level and a serial interfac e i s used for low level. This setting
cannot be changed after the power has been switched on.
CHA
DA
STB Strobe 77 I This is used for the device’s selec t signal and strobe signal for
E/SCK Enable/shift clock 78 I This is an input enabl e pi n for data when the parallel interface is used.
D0/DATA Data bus/data 68 I/O This pi n i s used for data bus bit D0 when using the parallel interface.
7
D1-D
OUT
TEST
/RESET Reset 79 I This pin is used for internal resets at low-level.
CHA
AMP
EXT
V
INV
SEG
INV
COM
•
OSC
OSC
OSC
IN
OUT
BRI
Select D/A convert er 61 I Use this pin to select whether or not to use the D/A converter for
regulating the LCD driver voltage. Selec t high level to use the D/A
converter or low level to not use it .
communication. Communication is initialized at the rising edge or falling
edge of STB.
Command data receive standby status occurs at the falling edge of STB .
Communication i s enabl ed when STB i s low.
Also, enabled status or t he shift clock is ignored when STB i s high.
During the read-in operation, data is c aptured in the interface buffer at
the signal’s rising edge. Duri ng a read-out operation, data is read-out
from the interface buf fer at the signal’s falling edge.
When using a serial i nterface, this pin is used f or the data shift clock.
During the read-in operation, data is c aptured in the shift register at t he
signal’s rising edge. During a read-out operation, data is read from the
shift register at t he signal’s falling edge.
When using the s eri al i nt erface, it is an I/O pin (tri -s tate) for commands
and display data.
Data bus 69-75 I/O These pins are used for data bus bits D1 to D7 when using the parallel
interface.
It should be fixed high or low when using the serial interface.
Test output 80 O This is a test output pin. Leave t hi s pin open when using the device.
Op amp switch for
LCD driver’s power
supply level
Reference power
supply switch
Segment direction
switch
Common scan
direction switch
62 I This pin is used to control the op amp that works with the LCD driver’s
power supply level. High-power mode is set when at lo w level and
normal mode is set when at high l evel .
60 I This pin is used to select the reference power supply circuit’s supply
mode. High level sets external mode and low level sets internal mode.
63 I This pin is used to control the segment output direction. Low level sets
forward direction and high level sets revers e di rection.
64 I This pin is used to switch the com mon scan direction. Low level sets
forward direction and high level sets revers e di rection.
Oscillator pins 65 I Thes e pins are connected to a 100-kΩ resistance. When using an
External clock for
blink function
66
O
external oscillator, input to OSCIN and leave OSC
67 I This is an input pin for the 2-Hz external clock. I nternally, it is divided by
half to generate a 1-Hz signal that i s used as the synchronization signal
OUT
unconnected.
for the blink function.
µµµµ
PD16681
6
Data Sheet S13104EJ5V0DS00
3.3 Driver System Pins
Pin Symbol Pin Name Pad No. I/O Description
SEG1 - SEG96Segment 115-210 O Segment output pins
COM1 -
51
COM
Common 85-105
109-112
211-216
220-239
PCOM1,
PCOM
IN(+)
AMP
IN(−)
AMP
OUT
AMP
2
Pictograph common 240
114
Op amp inputs 10-13 I These are input pins f or the op amp that regulates the LCD driver
Op amp outputs 8,9 O These are output pins for the op amp that regulates t he LCD dri ver
DUMMY DUMMY pins 1,81-84,
106-108,
113,
217-219,
241
O Common output pins
1/52 duty : Use COM
1/39 duty : Use COM
leave COM
1
to COM51.
1
to COM19, COM27 to COM45,
20
to COM26, COM46 to COM51 open.
O Common output pins for pict ographs
The same signal is out put from PCOM
voltage.
Leave the AMP
IN(+)
pin unconnected when using the on-chip D/A
converter. When not using the D/A converter, a reference volt age must
be input.
Connect the AMP
IN(−)
pin to a resistor used to regulate the LCD voltage.
(See diagram below.)
voltage. Normally, they are c onnected to resistors that are us ed to
regulate the LCD voltage. (See diagram below.)
Since the AMP
OUT
pins are used to stabilize the on-chip amp’s output, we
recommend connect i ng them to a capacitor that is rated between 0.1 and
1.0
F.
µ
DUMMY pins are not connected to the int ernal circuit. Leave open if they
−
are not used.
1
and PCOM2.
µµµµ
PD16681
DA
AMP
CHA
IN(+)
AMP
R
IN(−)
1
D/A
converter
+
−
AMP
R
2
OUT
Figure 3-1. Voltage Control Circuit
Reference power supply circuit
V
V
LC1
V
LC2
V
C
1
Data Sheet S13104EJ5V0DS00
LC3
LCBS1
V
LCBS2
V
LCBS3
V
EXT
V
V
LC4
V
LC5
SS
7
µµµµ
PD16681
4. POWER SUPPLY CIRCUIT
A switchable (3x or 4x) boost circuit is included to generate a current for driving the LCD. A connection to a boostrelated capacitor is used to switch the boost circuit’s setting.
EXT
The V
on-chip boost circuit.
4.1 Boost Circuit
When using the internal power supply, connect the boost-related capacitor between C
+
3
C
potential between V
Since the boost circuit uses signals from the internal oscillation circuit, the oscillation circuit must be operating. The
relation between the boosted voltage and the potential is described below.
The C
minimized.
pin (H: external, L: internal) is used to switch between using an external LCD driver power supply or the
and C
1
−
3
. Also, connect the capacitor for level stabilization between V
DD
and VSS from 3 to 4 times.
+
−
+
−
+
, C
1
2
2
, C
, C
, C
−
3
3
, C
and VDD pins all relate to the boost circuit, so the wire impedance should be
1
LCD
and VSS, and set V
+
and C
1
EXT
−
, C
Figure 4-1. 3x and 4x Boost Mode
+
2
and C
−
2
, and
low to boost the
V
LCD = 4VDD = 12 V
(During 4x boost mode)
V
LCD = 3VDD = 9 V
(During 3x boost mode )
Note
VDD = 3 V
SS = 0 V
V
Note
When set for 3x boost, connect boost-related capacitors between C
−
2
and C
+
3
and C
+
1
and C
−
1
.
8
Data Sheet S13104EJ5V0DS00
4.2 Regulation of LCD Driver Voltage
µµµµ
PD16681
4.2.1 When not using internal power supply select or D/A converter (V
EXT
= L, DA
CHA
= L)
When using the internal power supply, the boosted voltage is used as the power supply for the op amp incorporated
in the IC for the LCD driver’s voltage. A common mode amplifier circuit can be configured by connecting external
resistors R1 and R2 and inputting the reference voltage V
LC1
regulate the potential of the LCD driver voltage V
. If using a thermistor to regulate the LCD driver voltage to suit
REF
to AMP
IN(+)
, and this configuration can be used to
the liquid crystals’ temperature characteristics, we recommend connecting in parallel to R2.
LC1
The LCD driver voltage V
LC1
V
R2′ =
= AMP
R2 ‚ Rth
R2 + Rth
OUT
R2
= 1+ V
R1
can be determined using the following formula.
′
REF
Figure 4-2. When Not Using Internal Power Supply Select or D/A Converter
DA
CHA
D/A
converter
V
AMP
REF
+
IN
(+)
−
To internal drive circuit
IN(−)
AMP
R
1
4.2.2 When using internal power supply select and D/A converter (V
Using the D/A converter enables commands to be entered to control the reference voltage V
R
R
AMP
th
2
OUT
V
LC1
C
1
EXT
= L, DA
CHA
= H)
REF
that is input to the +
input of the op amp for the LCD driver voltage.
The D/A converter function sets 6-bit data to the D/A converter set register to set one of the 64 modes for the
REF
reference voltage V
The formula for V
(V
EXT
= L, DA
CHA
between VDD and 1/2 VDD.
LC1
is the same as in
= L) above.
4.2.1 When not using internal power supply select or D/A converter
Data Sheet S13104EJ5V0DS00
9
Figure 4-3. Using Internal Power Supply Select and D/A Converter
V
V
DD
DD
µµµµ
PD16681
D/A
converter
V
REF
+
To internal drive circuit
AMP
OPEN
DA
CHA
IN(+)
−
AMP
IN(−)
R
1
4.2.3 When using an external power supply (V
When an external power supply is used for the LCD driver voltage, the op amp incorporate in the
EXT
AMP
R
th
R
2
= H)
OUT
V
LC1
C
1
PD16681 (used
µ
for the LCD driver voltage) is in OFF mode. Consequently, the LCD driver’s op amp and D/A converter function
cannot be used when using an external power supply. Instead, regulate the LCD driver voltage by inputting directly
to the V
LCD
and V
LC1
pins.
Cautions 1. Maintain the following relation for the voltage input to the V
2. Since the DA
CHA
, AMP
IN(+)
, and AMP
IN(
)
pins are CMOS inputs, they should be fixed either high or
−−−−
LCD
and V
LC1
pins : V
LCD
> V
LC1
low.
OUT
3. The AMP
pin should be left unconnected.
4.3 Reference Voltage
4.3.1 When using internal power supply (V
When using the internal power supply, the
LC1
LC2
LC3
LC4
potential (V
, V
, V
, V
LC5
, V
, and VSS) required for the LCD driver.
4.3.2 When using an external power supply (V
When use of an external power supply has been selected, the op amp incorporated in the
driver level power supply is in OFF mode, so a reference potential must be directly input to V
LC5
.
V
EXT
= L)
PD16681’s on-chip divider resistor is used to create the six-level
µ
EXT
= H)
PD16681 for the LCD
µ
LC1
LC2
, V
LC3
, V
, V
LC4
, and
Ordinarily, these levels are generated by dividing the resistance. Since large resistance values result in poorer LCD
display quality, be sure to select a resistance value that suits the type of LCD panel to be used.
The display quality can be improved by connecting capacitors between the level pins and ground pins. As with the
resistance values described above, the capacitance values of the capacitors should be selected to suit the divided
resistance values and the type of LCD panel to be used.
10
Data Sheet S13104EJ5V0DS00
4.4 Control of Op Amp for Level Power Supply
µµµµ
PD16681
Input to the AMP
High power mode (AMP
•
CHA
pin is used to control the op amp for the LCD driver level power supply.
CHA
= L)
This mode maximizes the LCD drive current supply capacity in the op amp for the LCD driver level power supply.
CHA
Normal mode (AMP
•
= H)
This mode uses a lower LCD drive current supply capacity in the op amp for the LCD driver level power supply,
which is suitable for charging the capacitor used to stabilize the external level.
Caution For either mode, be sure to connect a level stabilization capacitor (rated from about 0.1 to 1.0
for the V
LC1
to V
LC5
pins. Poorer display quality results when these capacitors are not connected.
Figure 4-4. Reference Voltage Circuit
AMP
OUT
V
LC1
V
LC2
+
−
R
+
−
R
Output to SEG and COM
Output to SEG and COM
F)
µµµµ
V
V
V
V
LCBS1
LCBS2
LCBS3
V
V
V
LC3
LC4
LC5
SS
2R
+
−
R
R
+
−
R
+
−
R
Output to SEG and COM
Op amp for level driver
Output to SEG and COM
Output to SEG and COM
Output to SEG and COM
Data Sheet S13104EJ5V0DS00
11
4.5 Bias Value Settings
The bias value can be set as 1/6 bias, 1/7 bias, or 1/8 bias by selecting an internal bias for the (
connecting externally from the IC among V
Bias Value Connected Pin
LCBS1
LCBS3
, V
LCBS2
LCBS1
LCBS1
1/8 bias V
1/7 bias Between V
V
1/6 bias Between V
LCBS1
, and V
and V
and V
LCBS2
, V
LCBS3
leave open
LCBS2
LCBS3
LCBS3
, and V
or between V
LCBS2
and V
leave open
pins.
LCBS2
and
4.6 Power Supply Circuit Use Example
Figure 4-5. Using Internal Power Supply and Normal Mode
µµµµ
PD16681
PD16681 and by
µ
A) 4x boost (D/A converter is not used.)
V
DD
V
LCD
+
C
2
+
C
1
+
C
1
−
C
1
+
C
2
+
C
1
−
C
2
+
C
3
+
C
1
−
C
3
AMP
AMP
AMP
B) 3x boost
To V
DD
V
DD
(+)
R2Rth (thermistor)
(−)
1
R
OUT
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
+
+
+
+
+
+
C
2
+
C
1
open
+
C
1
+
open
V
LCD
+
C
1
−
C
1
+
C
2
−
C
2
+
C
3
−
C
3
Remarks 1.
12
V
V
1
C
= 1.0 µF,C2 = 1.0 µF
+
2.
Leave C
3.
Leave AMP
2
AMP
EXT
SS
−
3
and C
pins open during 3x boost.
(+)
open when using the D/A converter.
CHA
Data Sheet S13104EJ5V0DS00
V
DD
CHA
V
V
EXT
V
SS
Figure 4-6. Using External Power Supply Circuit
A) Use 1/8 bias
V
DD
AMP
AMP
(+)
(−)
µµµµ
PD16681
open
AMP
OUT
V
LCD
+
C
1
V
open
LC1
To external drive supply
R
−
C
1
+
C
2
V
LC2
R
V
LC3
−
C
2
+
C
3
V
LC4
−
C
3
4R
R
Remark
V
DD
V
EXT
V
SS
Fix all open input pins high or low.
V
LC5
Data Sheet S13104EJ5V0DS00
R
13
µµµµ
5. LCD DISPLAY DRIVER
Either a 1/52 duty driver or a 1/39 duty driver can be selected for the µPD16681. Both drivers output a drive
waveform using the two-frame AC drive method.
5.1 1/52 Duty Driver
When the 1/52 duty driver is selected for the
1
block’s common outputs (COM
1
V
V
V
1
V
V
V
and PCOM2).
1234567
LC1
LC2
LC3
LC4
LC5
SS
from PCOM
SEG
to COM51) and from the pictograph block’s common outputs (same signal output
PD16681, a select signal is output once per frame from the dot
µ
Figure 5-1. 1/52 Duty Driver
1Frame
8
5051521234567 50 51 52
8
PD16681
COM
COM
PCOM
PCOM
V
LC1
V
LC2
V
LC3
1
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
2
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
1
2
V
LC4
V
LC5
V
SS
14
Data Sheet S13104EJ5V0DS00
5.2 1/39 Duty Driver
When the 1/39 duty driver is selected for the
1
block’s common outputs (COM
signal output from PCOM
to COM19, COM27 to COM45) and from the pictograph block’s common outputs (same
1
and PCOM2).
Figure 5-2 1/39 Duty Driver
1Frame
1234567
V
LC1
V
LC2
V
SEG
COM
LC3
1
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
1
V
LC4
V
LC5
V
SS
µµµµ
PD16681, a select signal is output once per frame from the dot
µ
8
3738391234567 37 38 39
8
PD16681
COM
PCOM
PCOM
V
LC1
V
LC2
V
LC3
2
V
LC4
V
LC5
V
SS
V
LC1
V
LC2
V
LC3
1
2
V
LC4
V
LC5
V
SS
Data Sheet S13104EJ5V0DS00
15
µµµµ
PD16681
6. DESCRIPTION OF BLOCKS
6.1 Display Data RAM (DDRAM)
DDRAM is RAM that contains display data consisting of a 16-bit character code plus a character attribute code. The
RAM capacity is 16 x 72 bits, which means that up to 72 characters can be stored in RAM.
The following table shows correspondences between DDRAM addresses and LCD display positions. For further
description of these correspondences, see the section
123456789101112131415161718
1st line 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H
2nd line 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H
3rd line 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H
4th line 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H
6.2 Full Width (11x12 dots) Character Generator ROM (FCGROM)
FCGROM generates a total of 7,064 full width character patterns, of which 6,355 are JIS Level 1 + Level 2 kanji, 453
are non-kanji characters and 256 other symbols. These character patterns are displayed in 11 x12 dot font patterns
based on 12-bit character codes. The section entitled
Examples
Also, see the section entitled
and the character code set to DDRAM.
describes the correspondence between the character codes set to DDRAM and this full width font pattern.
7.2 Character Codes
7.1 LCD display and DDRAM addresses.
7.2.2 Full Width(11 x 12 dots) Character Code Setting
for a description of the correspondence between the JIS code
6.3 Half Width(5 x 12 dots) Character Generator ROM (HCGROM)
FCGROM generates a total of 192 half width (5 x 12 dots) character patterns, displayed in 5 x 12 dot font patterns.
The section entitled
and the half width font patterns.
7.2 Character Codes
describes the correspondence between the character code set to DDRAM
16
Data Sheet S13104EJ5V0DS00
µµµµ
PD16681
6.4 Character Generator RAM (CGRAM)
CGRAM is RAM to which the user can freely set character patterns. Eight types of 12 x 13 dot character patterns
can be defined. To display a character pattern that has been stored in CGRAM, the user specifies a value ranging
from “000H” to “007H”.
The relation between character codes and CGRAM addresses used to access CGRAM is shown below.
Figure 6-1. The Relation between Character Codes and CGRAM Addresses
C12
0
0
0
Character code
CGRAM Data
A0 ="0" A0 ="1"CGRAM Address
D
D
D
D
D
D
D
D
D
D
D
D
D
D
to
0
0
0
0
0
0
0
0
0
0
·
·
·
0
0
0
0
0
C3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
·
·
·
·
·
·
·
·
·
·
·
·
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
D
7
6
5
4
3
2
1
0
7
6
5
4
A
A
0
0
0
0
0
0
A
A
0
0
0
0
A
A
0
1
1
1
1
1
0
0
A
A
0
0
1
0
A
1
1
0
A
0
0
1
A
1
0
1
A
0
1
1
A
1
1
1
A
0
0
0
A
1
0
0
A
0
1
0
A
1
1
0
A
0
0
1
A
0
0
0
A
1
0
0
A
0
1
0
A
1
1
0
A
0
0
1
A
1
0
1
A
0
1
1
A
1
1
1
A
0
0
0
A
1
0
0
A
0
1
0
A
1
1
0
A
0
0
1
·
·
·
A
0
0
0
A
1
0
0
A
0
1
0
A
1
1
0
A
0
0
1
A
1
0
1
A
0
1
1
A
1
1
1
A
0
0
0
A
1
0
0
A
0
1
0
A
1
1
0
A
0
0
1
1
A
0
1
A
0
1
A
0
1
A
0
1
A
0
1
A
0
1
A
0
1
A
0
1
A
0
1
A
0
0
A
0
0
A
0
0
A
1
1
A
0
0
A
0
0
A
0
0
A
0
0
A
0
0
A
0
1
A
0
1
A
1
0
A
0
0
A
0
0
·
·
·
A
A
A
A
A
A
A
A
A
A
A
A
A
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
·
·
·
0
A
A
1
1
A
A
0
0
A
A
0
0
A
A
0
0
A
A
0
0
A
A
1
1
A
A
0
0
A
A
0
0
A
A
0
0
A
A
0
0
A
A
1
1
A
A
0
0
A
A
0
0
A
A
0
0
A
A
1
1
A
A
1
0
A
A
0
1
A
A
0
1
A
A
0
0
A
A
0
0
A
A
0
0
A
A
1
1
A
A
0
0
A
A
0
0
A
A
0
0
·
·
·
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A1
A2
A3
A4
A5
A6
A7
C0
C1
C2
D
3
2
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
·
·
·
Data Sheet S13104EJ5V0DS00
17
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