NEC UPD16680P, UPD16680W Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD16680

1/53, 1/40 DUTY, LCD CONTROLLER/DRIVER WITH BUILT-IN RAM

DESCRIPTION

The µPD16680 is a driver which contains a RAM capable of full - dot LCD display. The single µPD16680 IC chip can
operate a full - dot (up to 100 by 51 dots) LCD and pictographs (100 pictographs).

PD16680 can operate on single 3 V-power supply, is suitable for graphic pagers and cellular.

The

µ

FEATURES

LCD driver with a built-in display RAM

•

Can operate on single 3 V-power supply

•

Booster circuit incorporated : Switchable 3 or 4 folds

•

Dot display RAM : 100 x 51 bits

•

Pictographic display RAM : 100 bits

•

Pictographic display's duty changeable : 1/53 or 1/40 duty

•

Output for full-dot : 100 segments and 52 commons

•

Data input based on serial & 4-bit / 8-bit parallel switch over

•

String resister to output bias level incorporated

•

Selectable LCD driving bias level (select from 1/8 bias, 1/7 bias, 1/6 bias)

•

Oscillation circuit incorporated

•

D/A converter incorporated (for LCD driving voltage adjustment)

•

ORDERING INFORMATION

Part number Package
PD16680W/P Wafer/Chip(Matched COG mounting)

µ

Remark

Document No. S12694EJ2V0DS00(2nd edition)
Date Published July 1999 NS CP(K)
Printed in Japan

Purchasing the above products in term of chips per requires an exchange of other documents as well,
including a memorandum on the product quality. Therefore those who are interested in this regard are
advised to contact an NEC salesperson for further details.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

The mark

••••

shows major revised points.

©

1997, 1999

1. BLOCK DIAGRAM

100

µµµµ

PD16680

SEG

1

SEG

PCOM

51

COM

0

COM

LC5

V

LC4

100

Segment Driver

100

100-bit latch

100 bits

100 x 51 bits

Pictograph Data RAM

Display Data RAM

100 bits

Blink Data RAM

LCD Voltage Generator

Common Driver

53-bit Register

V

LCBS3

V

LCBS2

V

LCBS1

V

LC3

V

LC2

V

LC1

V

CHA

AMP

Blink Controller

OUT

AMP

Remark

2

DD

SS

V

V

/xxx indicates act ive low signals.

Address Decoder

Data

Register

I/O

Buffer

6

D
to

(NS)

(DATA)

1

7

WS

0

STB

E(SCK)

D

D

D

Data Sheet S12694EJ2V0DS00

Command Decoder

OUT

/RESET

TEST

Timing Generator

Oscillator

circuit

OUT

BRI

OSC

OSCINOSC

D/A Converter

CHA

DA

IN(-)

OP Amp

AMP

IN(+)

AMP

LCD

V

DC/DC

Converter

−

−

−

3

1

2

, C

, C

, C

+

+

+

1

3

2

EXT

V

C

C

C

2. PIN CONFIGURATION (Top view)

Chip Size : 12.5 mm x 1.89 mm

µµµµ

PD16680

250

264

249

115

Y

X

1

114

100

99

Data Sheet S12694EJ2V0DS00

3

Table 2-1. Pad Layout (1/2)

µµµµ

PD16680

Pin No. Pin Name

X(

m) Y(µm)

µ

1 Dummy –5883.2 –811.0 67 C
2 Dummy –5763.2 –811.0 68 C
3 Dummy –5643.2 –811.0 69 C
4V
5V

LCBS1
LCBS1

–5523.2 –811.0 70 C

–5403.2 –811.0 71 C
6 Dummy –5283.2 –811.0 72 C
7V
8V

LCBS2
LCBS2

–5163.2 –811.0 73 V

–5043.2 –811.0 74 V
9 Dummy –4923.2 –811.0 75 V

10 V
11 V

LCBS3
LCBS3

–4803.2 –811.0 76 Dummy 3116.8 –811.0

–4683.2 –811.0 77 V

12 Dummy –4563.2 –811.0 78 DA
13 AMP
14 AMP

OUT
OUT

–4443.2 –811.0 79 AMP

–4323.2 –811.0 80 OSC

15 Dummy –4203.2 –811.0 81 OSC
16 AMP
17 AMP

IN(-)
IN(-)

–4083.2 –811.0 82 V

–3963.2 –811.0 83 OSC

Pin No. Pin Name

3
3
3
3
3
3
DD
DD
DD

EXT

DD

+
+
+
–
–
–

CHA

CHA
IN
OUT

BRI

X(µm) Y(µm)

2036.8 –811.0

2156.8 –811.0

2276.8 –811.0

2396.8 –811.0

2516.8 –811.0

2636.8 –811.0

2756.8 –811.0

2876.8 –811.0

2996.8 –811.0

3236.8 –811.0

3356.8 –811.0

3476.8 –811.0

3596.8 –811.0

3716.8 –811.0

3836.8 –811.0

3956.8 –811.0
18 Dummy –3843.2 –811.0 84 D0(DATA) 4076.8 –811.0
19 AMP
20 AMP

IN(+)
IN(+)

–3723.2 –811.0 85 D

–3603.2 –811.0 86 D
21 Dummy –3483.2 –811.0 87 D
22 V
23 V

DD
DD

–3363.2 –811.0 88 D

–3243.2 –811.0 89 D
24 Dummy –3123.2 –811.0 90 D
25 V
26 V
27 V

LC5
LC5
LC5

–3003.2 –811.0 91 D7(NS) 4916.8 –811.0

–2883.2 –811.0 92 WS 5036.8 –811.0

–2763.2 –811.0 93 STB 5156.8 –811.0

1
2
3
4
5
6

4196.8 –811.0

4316.8 –811.0

4436.8 –811.0

4556.8 –811.0

4676.8 –811.0

4796.8 –811.0

28 Dummy –2643.2 –811.0 94 E(SCK) 5276.8 –811.0
29 V
30 V
31 V

LC4
LC4
LC4

–2523.2 –811.0 95 /RESET 5396.8 –811.0

–2403.2 –811.0 96 V

–2283.2 –811.0 97 TEST

DD

5516.8 –811.0

OUT

5636.8 –811.0
32 Dummy –2163.2 –811.0 98 Dummy 5756.8 –811.0
33 V
34 V
35 V
36 Dummy –1683.2 –811.0 102 COM
37 V
38 V
39 V
40 Dummy –1203.2 –811.0 106 COM
41 V
42 V
43 V
44 Dummy –723.2 –811.0 110 COM
45 V
46 V
47 V
48 V
49 V
50 V
51 V
52 V
53 V
54 Dummy 476.8 –811.0 120 COM
55 C
56 C
57 C
58 C
59 C
60 C
61 C
62 C
63 C
64 C
65 C
66 C

LC3
LC3
LC3

LC2
LC2
LC2

LC1
LC1
LC1

LCD
LCD
LCD
DD
DD
DD
SS
SS
SS

1
1
1
1
1
1
2
2
2
2
2
2

–2043.2 –811.0 99 Dummy 5876.8 –811.0
–1923.2 –811.0 100 Dummy 6112.0 –682.2
–1803.2 –811.0 101 Dummy 6112.0 –592.2

–1563.2 –811.0 103 COM
–1443.2 –811.0 104 COM
–1323.2 –811.0 105 COM

–1083.2 –811.0 107 COM
–963.2 –811.0 108 COM
–843.2 –811.0 109 COM

–603.2 –811.0 111 COM
–483.2 –811.0 112 COM

27
28
29
30
31
32
33
34
35
36
37

6112.0 –502.2

6112.0 –412.2

6112.0 –322.2

6112.0 –232.2

6112.0 –142.2

6112.0 –52.2

6112.0 37.8

6112.0 127.8

6112.0 217.8

6112.0 307.8

6112.0 397.8

–363.2 –811.0 113 Dummy 6112.0 487.8
–243.2 –811.0 114 Dummy 6112.0 577.8
–123.2 –811.0 115 Dummy 6030.0 817.8
–3.2 –811.0 116 Dummy 5940.0 817.8

100

38
39
40
41
42
43
44
45
46
47
48
49
50
51

5850.0 817.8

5760.0 817.8

5670.0 817.8

5580.0 817.8

5490.0 817.8

5400.0 817.8

5310.0 817.8

5220.0 817.8

5130.0 817.8

5040.0 817.8

4950.0 817.8

4860.0 817.8

4770.0 817.8

4680.0 817.8

4500.0 817.8

116.8 –811.0 117 COM

236.8 –811.0 118 COM

356.8 –811.0 119 COM

+
+
+
–
–
–
+
+
+
–
–
–

596.8 –811.0 121 COM

716.8 –811.0 122 COM

836.8 –811.0 123 COM

956.8 –811.0 124 COM

1076.8 –811.0 125 COM

1196.8 –811.0 126 COM

1316.8 –811.0 127 COM

1436.8 –811.0 128 COM

1556.8 –811.0 129 COM

1676.8 –811.0 130 COM

1796.8 –811.0 131 PCOM 4590.0 817.8

1916.8 –811.0 132 SEG

4

Data Sheet S12694EJ2V0DS00

Table 2-1. Pad Layout (2/2)

µµµµ

PD16680

Pin No. Pin Name

133 SEG
134 SEG
135 SEG
136 SEG
137 SEG
138 SEG
139 SEG
140 SEG
141 SEG
142 SEG
143 SEG
144 SEG
145 SEG
146 SEG
147 SEG
148 SEG
149 SEG
150 SEG
151 SEG
152 SEG
153 SEG
154 SEG
155 SEG
156 SEG
157 SEG
158 SEG
159 SEG
160 SEG
161 SEG
162 SEG
163 SEG
164 SEG
165 SEG
166 SEG
167 SEG
168 SEG
169 SEG
170 SEG
171 SEG
172 SEG
173 SEG
174 SEG
175 SEG
176 SEG
177 SEG
178 SEG
179 SEG
180 SEG
181 SEG
182 SEG
183 SEG
184 SEG
185 SEG
186 SEG
187 SEG
188 SEG
189 SEG
190 SEG
191 SEG
192 SEG
193 SEG
194 SEG
195 SEG
196 SEG
197 SEG
198 SEG

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

X(

m) Y(µm)

µ

4410.0 817.8 199 SEG

4320.0 817.8 200 SEG

4230.0 817.8 201 SEG

4140.0 817.8 202 SEG

4050.0 817.8 203 SEG

3960.0 817.8 204 SEG

3870.0 817.8 205 SEG

3780.0 817.8 206 SEG

3690.0 817.8 207 SEG

3600.0 817.8 208 SEG

3510.0 817.8 209 SEG

3420.0 817.8 210 SEG

3330.0 817.8 211 SEG

3240.0 817.8 212 SEG

3150.0 817.8 213 SEG

3060.0 817.8 214 SEG

2970.0 817.8 215 SEG

2880.0 817.8 216 SEG

2790.0 817.8 217 SEG

2700.0 817.8 218 SEG

2610.0 817.8 219 SEG

2520.0 817.8 220 SEG

2430.0 817.8 221 SEG

2340.0 817.8 222 SEG

2250.0 817.8 223 SEG

2160.0 817.8 224 SEG

2070.0 817.8 225 SEG

1980.0 817.8 226 SEG

1890.0 817.8 227 SEG

1800.0 817.8 228 SEG

1710.0 817.8 229 SEG

1620.0 817.8 230 SEG

1530.0 817.8 231 SEG

1440.0 817.8 232 COM

1350.0 817.8 233 COM

1260.0 817.8 234 COM

1170.0 817.8 235 COM

1080.0 817.8 236 COM

990.0 817.8 237 COM

900.0 817.8 238 COM

810.0 817.8 239 COM

720.0 817.8 240 COM

630.0 817.8 241 COM

540.0 817.8 242 COM

450.0 817.8 243 COM

360.0 817.8 244 COM

270.0 817.8 245 COM

180.0 817.8 246 COM

90.0 817.8 247 COM

Pin No. Pin Name

33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11

X(µm) Y(µm)
–1530.0 817.8
–1620.0 817.8
–1710.0 817.8
–1800.0 817.8
–1890.0 817.8
–1980.0 817.8
–2070.0 817.8
–2160.0 817.8
–2250.0 817.8
–2340.0 817.8
–2430.0 817.8
–2520.0 817.8
–2610.0 817.8
–2700.0 817.8
–2790.0 817.8
–2880.0 817.8
–2970.0 817.8
–3060.0 817.8
–3150.0 817.8
–3240.0 817.8
–3330.0 817.8
–3420.0 817.8
–3510.0 817.8
–3600.0 817.8
–3690.0 817.8
–3780.0 817.8
–3870.0 817.8
–3960.0 817.8
–4050.0 817.8
–4140.0 817.8
–4230.0 817.8
–4320.0 817.8
–4410.0 817.8
–4500.0 817.8
–4590.0 817.8
–4680.0 817.8
–4770.0 817.8
–4860.0 817.8
–4950.0 817.8
–5040.0 817.8
–5130.0 817.8
–5220.0 817.8
–5310.0 817.8
–5400.0 817.8
–5490.0 817.8
–5580.0 817.8
–5670.0 817.8
–5760.0 817.8
–5850.0 817.8

0.0 817.8 248 Dummy –5940.0 817.8
–90.0 817.8 249 Dummy –6030.0 817.8
–180.0 817.8 250 Dummy –6112.0 577.8
–270.0 817.8 251 Dummy –6112.0 487.8
–360.0 817.8 252 COM
–450.0 817.8 253 COM
–540.0 817.8 254 COM
–630.0 817.8 255 COM
–720.0 817.8 256 COM
–810.0 817.8 257 COM
–900.0 817.8 258 COM
–990.0 817.8 259 COM
–1080.0 817.8 260 COM
–1170.0 817.8 261 COM

10
9
8
7
6
5
4
3
2
1

–6112.0 397.8
–6112.0 307.8
–6112.0 217.8
–6112.0 127.8
–6112.0 37.8
–6112.0 -52.2
–6112.0 -142.2
–6112.0 -232.2
–6112.0 -322.2
–6112.0 -412.2

–1260.0 817.8 262 PCOM –6112.0 -502.2
–1350.0 817.8 263 Dummy –6112.0 -592.2
–1440.0 817.8 264 Dummy –6112.0 -682.2

Data Sheet S12694EJ2V0DS00

5

3. PIN DESCRIPTIONS

3.1 Power System Pins

Pin Symbol Pin Name Pin No. I/O Function Description

DD

V

SS

V

LCD

V

★

V

V
V
C
C
C

LC1

to V

LCBS1

LCBS3

+

, C

1

+

, C

2

+

, C

3

LC5

to

–

1

–

2

–

3

µµµµ

PD16680

Logic and booster power
supply pin

22, 23,

48 to 50,

- Power supply pin for logic and booster ci rcuit.

73 to 75,

82, 96

Logic and driver ground

51 to 53 - Ground pin for logic and driver circuit .
pin
Driver power supply pin 45 to 47 - Driver power supply pin. Output pin of i nternal booster circuit.

Please connect with a 1

F booster capacitor to ground.

µ

When not using the i nternal booster circuit, the driver power

can be turned on directly.
Driver reference power
supply

25 to 27,
29 to 31,
33 to 35,
37 to 39,

- Reference power supply pin for LCD drive.
When the internal bi as i s selected, be sure to leave it open.
When display contrast is bad, connect a capacitor between
these pins and ground.

41 to 43

Bias level select pin 4, 5, 7,

8, 10, 11

- When the internal bias is selected, Connecting these pins
outside the IC, the bias l evel can be changed.

Capacitor connection pins 55 to 72 - Capacitor connection pins for booster circuit. When using

internal booster circuit, connect a 1

F capacitor between

µ

these pins.

6

Data Sheet S12694EJ2V0DS00

µµµµ

PD16680

3.2 Logic System Pins (1/2)

Pin Symbol Pin Name Pin No. I/O Function Description

WS Word length select pin

(Word Select )

CHA

DA

D/A converter select pi n 78 I This pin sel ec ts whether to use the internal D/A c onverter for

STB Strobe 93 I This pin is select signal of device, strobe signal for data

E(SCK) Enable(shift clock) 94 I When using paral l el i nt erface mode, this pin becomes the

D0(DATA) Data-bus(data) 84 I/ O When using parallel interface m ode, this pin becomes t he D

3

D1 to D

D4 to D

6

Data-bus 85 to 87 I/O W hen using parallel interface mode, these pin becom es the

Data-bus 88 to 90 I /O When using parallel interfac e mode, thes e pin become t he D

D7(NS) Data-bus(nibble select) 91 I/ O When word select (WS) is High level, this pin becomes the D

OUT

TEST

TEST signal output 97 O When to do test , this pin is output for test signal.

/RESET Reset 95 I

92 I This pin selects the word length.

At High level, it become an 8-bit parallel interface.
At Low level, when D

7

(NS) is High level, it become a serial
interface.
When the word length is 4 bits, data is transferred in the
upper-to-low sequence by mean of data buss es D
The word length cannot be changed after power-on.

LCD driving voltage adjustment or not .
At High level, D/A c onverter is used. At Low level, unused.

transfer. Data transfer is initialized at falling/rising edge of
STB.
Data can be input/output at Low level either in parallel
interface or serial interf ace mode.
When STB is Hi gh l evel , Enable/shift clock is bypassed.

data enable input. In reading-in, dat a i s fetched into the
interface buffer at ris i ng edge. In reading-out, data is fetched
from interface buff er at falling edge.
When using serial i nterface mode, this pin becom es the data
shit clock.
In reading-in, data is fetc hed into the interfac e buffer at rising
edge.
In reading-out, data is fetched from interface buffer at falling
edge.

bit of data-bus.
When using serial interface mode, this pin becomes the
input/output pin of the c ommand and display data (3 states).

1

D

to D3 bits of data-bus. W hen using serial interface m ode,

keep them H or L.

to D6 bits of data-bus. When using serial interf ace mode, keep
them H or L.

bit of data-bus.
When word select (WS) is Low level, This pin becomes nibble
select pin. At High l evel , selected 4-bit parallel interface.
At Low level, selected serial i nterface.

When using in normal operation, this pin leave open.
At Low level, the

PD16680 is initialized.

µ

0

to D3.

0

4

7

Data Sheet S12694EJ2V0DS00

7

3.2 Logic System Pins (2/2)

Pin Symbol Pin Name Pin No. I/O Function Description

CHA

AMP

EXT

V

OSC

OSC

OSC

IN

OUT

BRI

Amp mode select pin 79 I Select operational amplifier mode.

At High level, “Level capac i tor mode”.
At Low level, “LCD driving mode”.

LCD reference supply
switching

77 I Select the m ethod for supplying LCD power circuit. At High

level, LCD driving voltage is suppli ed external circuit. At Low
level, it is supplied internal circuit.

Oscillation pin

80 I

These pins are connected with the 1 MΩ resistor. W hen us ing
external oscillation, input into the OSC

OUT

OSC

81 O

open.

Blinking Clock 83 I This pin is oscillation input for Blink ing. To input 2 Hz external

clock, when to use Blink i ng by external c l ock mode.
When not to use t hi s pin, keep it H or L.

µµµµ

PD16680

IN

, and leaving the

8

Data Sheet S12694EJ2V0DS00

3.3 Driver System Pins

Pin Symbol Pin Name Pin No. I/O Function Description

SEG1 to

100

SEG
COM1 to

51

COM

PCOM Pictographic common 131, 262 O Common output pins for pictograph.

AMPIN(+) 19, 20

AMPIN(-)

OUT

AMP

Dummy Dummy pad 1, 2, 3, 9, 12,

Segment 132 to 231 O Segment output pins.

Common 102 to 112,

O Common output pins
117 to 130,
232 to 247,
252 to 261

(Same waveform output from these pins.)

Operational amplifier input

I These pins are the input pins of operat ional amplif ier for LCD

driving voltage adjustment .
When using the int ernal D/A converter, leave AMP
When not using the i nternal D/A converter, it is necessary to

16,17

input the reference voltage.

IN(–)

AMP

is connected to the resist er for LCD driving voltage
adjustment.
See

4. LCD DRIVING VOLTAGE CONTROL CIRCUIT

Operational amplifier
output

13,14 O This is the input pin of operati onal amplifier for LCD driving

voltage adjustment. Normally it is connected to the res i ster for
LCD driving voltage adjustment . See

VOLTAGE CONTROL CIRCUIT

this pin a 0.1 to 1

µ

internal operational amplif i er be stable.

- Dumm y pins are not connected to the internal circuit. Leave

15, 18, 21,

open if they are not used.

24, 28, 32,
33, 40, 44,
54, 76,
98 to 101,
113 to 116,
248 to 251,
263, 264

. It recomm ends to connect to

F capacitor to make the output of the

µµµµ

IN(+)

4. LCD DRIVING

PD16680

open.

.

4. LCD DRIVING VOLTAGE CONTROL CIRCUIT

CHA

AMP

DA

IN(+)

AMP

IN(−)

R

1

D/A
Converter

+

−

AMP

R

2

outVLC1

C

1

V

LC2VLC3

Data Sheet S12694EJ2V0DS00

Reference power circuit

V

LCBS1

V

LCBS3

V

LCBS2

V

LC4VLC5

V

EXT

V

SS

9

µµµµ

PD16680

5. POWER CIRCUIT

The

PD16680 incorporate the booster circuit is switchable between 3 and 4 folds. The boosting magnitude of

µ

internal booster circuit is selected by the capacitor connection.

The reference power circuit is switchable between internal driving circuit and external driving circuit. The method

EXT

for supplying the reference circuit selected by V

5.1 Booster circuit

pin (H : External, L : Internal ).

Using Internal driving circuit, to connect condenser for boosting between C

LCD

connect condenser between V
booster circuit boost voltage between V

and VDD to be stable boosting voltage. And to set V

DD

and VSS to 3 or 4 folds.

+

and C

1

–

+

, C

1

2

EXT

pin to low level, internal

and C

–

+

, C

2

3

and C

The booster circuit is using clock made by internal oscillation circuit. It is necessary that oscillation to be operated.

+

–

+

–

+

–

, C

,C

,C

C

1

1

,C

2

2

3

,C

DD

, V

are pins for booster circuit. To use the wire that have low register value to connect

3

these pins.

Figure 5-1 3x and 4x Booster Circuits

V

LCD = 4VDD = 12 V

(4-fold boost)

V

LCD = 3VDD = 9 V

(3-fold boost)

VDD = 3 V

SS = 0 V

V

Remarks 1.

When to use 3-fold booster circuit, not to connect condenser between C
open C

2.

When to use external power supply circuit, booster circuit is not operating.

+

2

and C

–

.

3

+

3

and C

–

+

, C

2

1

and C

–

, leave

1

3

–

, to

10

Data Sheet S12694EJ2V0DS00

5.2 LCD driving circuit

µµµµ

PD16680

5.2.1 To use internal driving circuit, not to use D/A converter ( V

EXT

= L , DA

CHA

= L )

When to internal driving circuit is chosen, boosted voltage be used for power of internal operational amplifier

adjusting LCD driving voltage. To connect external resister R

LC1

possible to adjust LCD driving voltage of V

. If using thermistor to adjust LCD driving voltage according to the

1

, R2, and input reference voltage to AMP

temperature characteristic of LCD panel, we recommend connecting it with R

LC1

The value of V

can be computed by the following formula.

2

in parallel.

(+)

IN

Equation 5-1

R

2

V

= AMPIN(+) = (1+ ) V

LC1

Remark

2

R

R2 x R

=

′

R2 + R

′

R

th

th

REF

1

Figure 5-2 When not using Internal power supply select or D/A converter

DA

CHA

D/A
Converter

V

REF

to Internal driving circuit

pin. It is

AMP

AMP

IN(+)

R

IN(-)

1

+

−

R

R

AMP

th

2

out

V

LC1

1

C

Data Sheet S12694EJ2V0DS00

11

µµµµ

PD16680

5.2.2 To use internal driving circuit and D/A converter ( V

To use D/A converter, it is possible to adjust reference voltage V
command.
To set 6-bit data to D/A converter register, reference voltage V
The formula of V

LC1

is as same written in

Equation 5-1

.

Figure 5-3 Using internal power supply select and D/A converter

V

DD

D/A
Converter

V

REF

+

−

AMP

out

AMP

Open

DA

IN(+)

AMP

CHA

IN(-)

= L , DA

EXT

REF

inputted to AMP

REF

is choose one level from 64 level in 1/2 VDD to VDD.

V

DD

CHA

= H )

(+)

pin for LCD driving by

IN

to Internal driving circuit

V

LC1

R

th

R

2

R

1

C

1

.

5.2.3 To use external driving circuit ( V

EXT

= H )

When external voltage supply circuit for LCD driving is chosen, operational amplifier incorporated IC is off.
Therefore, it is impossible to use operational amplifier for LCD driving and D/A converter function. LCD driving
voltage is adjust by the voltage inputted to V

LCD

Remarks 1.

Set V

2.

DA

3.

Set AMP

CHA ,

LC1.

V

≥

IN

AMP

pin "open".

OUT

(+)

, AMP

(-)

IN

are CMOS input. Set H level or L level.

LCD

and V

LC1

pins directly.

12

Data Sheet S12694EJ2V0DS00

5.3 REFERENCE VOLTAGE CIRCUIT

µµµµ

PD16680

5.3.1 To use internal reference voltage circuit ( V

When internal driving circuit is chosen, 6 levels for LCD reference voltage (V

EXT

= L )

LC1

, V

LC2

, V

LC3

, V

LC4

, V

, VSS) is

LC5

generate by internal breeder resister.

5.3.2 To use external driving circuit ( V

EXT

= H )

When external driving circuit is chosen, operational amplifier incorporated IC is Off. It is necessary to input voltage
to V

, V

, V

, V

LC1

LC2

LC3

LC4

and V

directly.

LC5

Generally, These levels are made by external breeder resister. The display dignity of LCD declines when these
resistance values are big, it is necessary to choose the resistance value which corresponds with the LCD panel.

There is an effect that improves display dignity when connecting a capacitor with each level pins and the ground. It is
necessary to choose the condenser value which corresponds with the LCD panel.

★

Figure 5-3. Reference voltage circuit

AMP

OUT

V

LC1

V

LC2

+

−

R

+

−

R

to SEG, COM Outputs

to COM Output

V

V

V

V

LC3

LCBS1

LCBS2

LCBS3

V

LC4

V

LC5

V

SS

+

−

R

R

R

+

−

R

+

−

R

to SEG Output

Voltage follower for level voltage

to SEG Output

to COM Output

to SEG, COM Output

Data Sheet S12694EJ2V0DS00

13

5.4 Setting BIAS value

When internal driving circuit chosen, by connecting the interval of the pin V
bias value can be set from the 1/6 bias, the 1/7 bias, the 1/8 bias.

Bias value Pin connection

LCBS1

LCBS2

1/8 bias V

, V
1/7 bias To connect V
1/6 bias To connect V

, V

LCBS3

LCBS1

LCBS1

All open
and V
and V

LCBS2

LCBS3

, or V

LCBS2

, V

LCBS2

and V

is open.

LCBS3

5.5 Voltage followers for level power supply

LCBS1

, V

LCBS2

LCBS3

, V

outside the IC, the

µµµµ

PD16680

By the input of AMP

• LCD driving mode ( AMP
When this mode is chosen, The voltage follower maximizes electric current supply ability for LCD drive. It
doesn't need to connect the external capacitor for the level stability.

CHA

pin, it controls voltage follower for the LCD drive level power supply.

CHA

= L )

• Level capacitor mode ( AMP
When this mode is chosen, The voltage follower maximizes electric current supply ability for the external
condenser charging. In this mode, it needs to connect the external capacitor ( 0.1 to 1.0 µF ) for the level stability.

CHA

= H )

Caution When using this mode without connecting capacitor, the display dignity will be bad.

14

Data Sheet S12694EJ2V0DS00