NEC UPD16432BGC-001-9EU Datasheet
DATA SHEET
MOS INTEGRATED CIRCUIT
µµµµ
PD16432B
1/8, 1/15 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
The µPD16432B is a controller/driver with 1/8 and 1/15 duty dot matrix LCD display capability. It has 60 segment
outputs, 10 common outputs, and 5 dual segment/common outputs, giving a maximum display capability of 12
columns × 2 lines (at 1/15 duty).
LED drive outputs, key scanning key source outputs, and key data inputs are also provided, making it ideal for use
in a car stereo front panel, etc.
FEATURES
• Dot matrix LCD controller/driver
• Pictograph display segment drive capability (max. 64)
• LCD driver unit power supply V
• On-chip key scan circuit (8 × 4 matrix)
• Alphanumeric character and symbol display capability provided by on-chip ROM (5 × 7 dots)
240 characters + 16 user-defined characters
• Display contents
1/8 duty: 13 columns × 1 line, 64 pictograph displays, 4 LEDs
1/15 duty: 12 columns × 2 lines, 60 pictograph displays, 4 LEDs
• Serial data input/output (SCK, STB, DATA)
• On-chip oscillator
• Reduced power consumption possible using standby mode
LCD
independently settable (Max. 10 V)
ORDERING INFORMATION
Part Number Package
µ
PD16432BGC-001-9EU 100-pin plastic QFP (0.5 pit ch, 14 × 14), Standard ROM code
Document No. S11092EJ5V0DS00 (5th edition)
Date Published April 1998 N CP(K)
Printed in Japan
1998©
BLOCK DIAGRAM
4
LED1LED
1
/KS
1
SEG
8
/KS
8
9
SEG
SEG
14
/COM
61
SEG60SEG
10
/COM
65
SEG
9
COM
µµµµ
PD16432B
0
COM
4
LED
Driver
4
4-Bit LED
Output Latch
4
Segment Driver
65-Bit Output Latch
65-Bit Shift Register
Parallel/Serial Conversion
5
CG
RAM
5 × 7
5
CG ROM
5 × 7 × 240
× 16
65
65
5
5
5
Common Driver
15
15-Bit Shift Register
2
Timing Generator
8
OSC
IN
8
Display
Data RAM
8 × 25
Character
Display
RAM
OSC
OSC
OUT
64 Bits
2
STB
SCK
DATA
RESET
LCD OFF
SYNC
Serial I/F
Command
Decoder
5
KEY REQ
8
KEY
Key Data
1
RAM
4 × 8
SS
DD
V
LC1VLC2VLC3VLC4VLC5
LCD
V
V
V
KEY
4
PIN CONFIGURATION
µµµµ
PD16432B
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61/COM14
SEG62/COM13
SEG63/COM12
SEG64/COM11
SEG65/COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
75 51
76
100
125
50
26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8/KS8
SEG7/KS7
SEG6/KS6
SEG5/KS5
SEG4/KS4
SEG3/KS3
SEG2/KS2
SEG1/KS1
VSS
VLC5
VLC4
VLC3
LED1
LED2
LED3
LED4
VLC2
VLC1
VLCD
VDD
SYNC
LCD OFF
SCK
RESET
KEY REQ
STB
DATA
IN
OSC
OSCOUT
KEY1
KEY2
KEY3
KEY4
3
PIN DESCRIPTIONS
Pin Symbol Pin Name Pin No. Function
µµµµ
PD16432B
SEG1/KS1 to
8
8
/KS
SEG
SEG9 to SEG
SEG61/COM14 to
85
/COM
SEG
Segment output/key source
output dual-function pins
60
Segment outputs 34 to 85 Dot matrix LCD segment outputs
Segment output/common
10
output dual-function pins
26 to 33 Pins with dual function as dot matrix LCD segment outputs and
key scanning key source outputs
86 to 90 Switchable to either dot matrix LCD segment outputs or com-
mon outputs
COM0 to COM9Common outputs 91 to 100 Dot matrix LCD common outputs
LED1 to LED
4
LED output pins 1 to 4 LED outputs are Nch open-drain.
SCK Shift clock input 17 Data shift clock
Data is read on rising edge, and output on falling edge.
DATA Data input/output 18 Performs input of commands, key data, etc., and key data
output. Input is performed from the MSB on the rise of the shift
clock, and the first 8 bits are recognized as a command. Output
is performed from the MSB on the fall of the shift clock.
Output is Nch open-drain.
STB Strobe input 19 Data input is enabled when “H”. Command processing is
performed on a fall.
KEY REQ Key request output 16 “H” if there is key data, “L” if the r e is none. Key data can be read
irrespective of the state of this pin. Output is CMOS output.
RESET Reset input 15 Initial state is set when “L”.
LCD OFF LCD off input 14 When “L”, a forced LCD off operation is performed, and SEG
n
& COMn output the unselected waveform.
SYNC Synchro 13 Synchronization signal input/output pin. When 2 or more chips
are used, wired-OR connection is made to each chip. A pull-up
resistor is also required when one chip is used.
IN
OSC
OUT
OSC
KEY1 to KEY
DD
V
SS
V
LCD
V
LC1
to V
LC5
V
Oscillation pins
4
Key data inputs 22 to 25 Key scanning key data inputs.
Logic power supply pin 12 Internal logic power supply pin
GND pin 5 GND pin
LCD drive voltage pin 11 LCD drive power supply pin
LCD drive power supply 10 to 6 Dot matrix LCD drive power supply
20
21
Connect oscillator resistor.
4
µµµµ
PD16432B
LCD DISPLAY
In the µPD16432B LCD display, a 5 × 7-segment display and pictograph display segments can be driven. The
0
pictograph display segment common output is allocated to COM
(1) Example of 1/8 duty connections
1
SEG
2345
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM0
, and up to 64 can be driven.
616263 64 65678910
(2) Example of 1/15 duty connections
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM0
1SEG
2345
64 Pictograph Segments
565758 59 60678910
60 Pictograph Segments
5
µµµµ
PD16432B
CHARACTER CODES AND CHARACTER PATTERNS
The relation between character codes and character patterns is shown below. Character codes 00H to 0FH are
allocated to CGRAM.
Character codes 10H to 1FH and E0H to FFH are undefined.
Higher
Lower
Bits
Bits
0XH
1XH 2XH 3XH
4XH 5XH 6XH
7XH 8XH 9XH AXH BXH CXH DXH EXH FXH
X0HRAM
X1HRAM
X2HRAM
X3HRAM
X4HRAM
X5HRAM
X6HRAM
X7HRAM
X8HRAM
CG
(1)
CG
(2)
CG
(3)
CG
(4)
CG
(5)
CG
(6)
CG
(7)
CG
(8)
CG
(9)
X9HRAM
XAHRAM
XBHRAM
XCHRAM
XDHRAM
XEHRAM
XFHRAM
CG
(10)
CG
(11)
CG
(12)
CG
(13)
CG
(14)
CG
(15)
CG
(16)
6
DISPLAY RAM ADDRESSES
Display RAM addresses are allocated as shown below irrespective of the display mode.
Column No.12345678910111213
Line 1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH
Line 2 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H
PICTOGRAPH DISPLAY RAM ADDRESSES
Pictograph display RAM addresses are allocated as shown below.
µµµµ
PD16432B
Address
00H 12345678
01H 9 10111213141516
02H 17 18 19 20 21 22 23 24
03H 25 26 27 28 29 30 31 32
04H 33 34 35 36 37 38 39 40
05H 41 42 43 44 45 46 47 48
06H 49 50 51 52 53 54 55 56
07H 57 58 59 60 61 62 63 64
Note
b7 b6 b5 b4 b3 b2 b1 b0
When 1/15 duty is used (12 columns × 2 lines), 61 to 64 are disabled.
Segment Output No.
7
µµµµ
PD16432B
CGRAM COLUMN ADDRESSES
A maximum of any sixteen 5 × 7-dot characters can be written in CGRAM. The row address within one character is
allocated as shown below, and is specified by bits b7 to b5.
The character code for which a write is to be performed must be specified beforehand with an address setting
command.
Row
Address
00H 0 0 0
01H 0 0 1
02H 0 1 0
03H 0 1 1
04H 1 0 0
05H 1 0 1
06H 1 1 0
Font data (1: on, 0: off)
*
b7 b6 b5 b4 b3 b2 b1 b0
Row Address Font Data
Dot Data
*****
*****
*****
*****
*****
*****
*****
(5 × 7 Dots)
8
KEY MATRIX AND KEY DATA RAM CONFIGURATION
The key matrix has an 8 × 4 configuration, as shown below.
KEY1
µµµµ
PD16432B
KEY2
=
KEY3
KEY4
KS1 KS2 KS3 KS4 KS5 KS6 KS7 KS8
Key data is stored as shown below, and is read in MSB-first order by a read command.
b7 b4 b3
KS
8
KS
6
KS
4
KS
2
KEY
KEY
3
4
KEY
KS
KS
KS
KS
2
7
5
3
1
KEY
b0
Key data is as follows:
1: On
0: Off
Read Order
1
Key Input Equivalent Circuit
VDD
Pull-Up
Control Signal
R
To Key
Data RAM
In the event of key source output, the pull-up control signal
becomes “H”, and the pull-up transistor is turned on.
KEYn
9
KEY REQUEST (KEY REQ)
A key request is output as shown below according to the state.
µµµµ
PD16432B
State
In key scan operation High level is output while any key
data is “1”.
In standby mode or when SEG
& COMn are fixed at V
When key scanning is stopped Fixed at low level Always OFF
KEY REQ does not become low until the key data is all “0”.
Note
LC5
n
High level is output in case of key
input only.
KEY REQ
Note
Note
Key Scan Internal Pull-Up Resistor
During key scan : ON
During display : OFF
Always ON
(It is not synchronized with the key data reads.)
LED OUTPUT LATCH CONFIGURATION
The low-order 4 bits of the LED output latch are enabled, and the high-order 4 bits disabled, as shown below.
LSBMSB
b3 b2 b1 b0
××××
Latch data is as follows:
1: On
0: Off
×
: Don’t Care
LED1
LED2
LED3
LED4
10
µµµµ
PD16432B
COMMANDS
Commands set the display mode and status.
The first byte after a rise edge on the STB pin is regarded as a command.
If STB is driven low during command/data transfer, serial communication is initialized and the command/data being
transferred is invalidated. (However, a command or data that has already been transferred is valid.)
(1) Display Setting Command
This command initializes the
slave operation, and the drive voltage supply method.
The state set when this command is executed is: LCD off, LED on, key scanning stopped. To restart the display,
it is necessary to execute “status command” normal operation. However, nothing is done if the same mode is
selected.
×
00
After powering on
Note
××
×
××
When multiple chips are used, only the chip that sent the command is enabled. If initialization is
performed during display, the display may be affected (especially when multiple chips are used).
PD16432B
µ
b2 b1 b0
000
Note
, and sets the duty, number of segments, number of commons, master/
LSBMSB
×
: Don’t Care
Duty setting
0: 1/8 duty (SEG61/COM14 to SEG65/COM10 → segment outputs)
1: 1/15 duty (SEG61/COM14 to SEG65/COM10 → common outputs)
Master/slave setting
0: Master
1: Slave
Drive voltage supply method selection
0: External
1: Internal
11
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