The µPC2533 is an IC developed as an AM tuner for car stereos and car radios.
It employs an up-conversion type double super-heterodyne configuration (IF1 = 10.71 MHz, IF2 = 450 kHz).
The internal configuration consists of the MIX1 block (MIX1, OSC1, Buff1), MIX2 block (MIX2, OSC2, Buff2), IF
amplifier, detection circuit, AGC circuit, signal meter circuit, SD (station detector) circuit, and Lo/DX (short range/long
range) circuit.
Features
• Possible to select stations using only one varactor diode with narrow variable capacitance range
• Tracking adjustment unnecessary
• Coil switching between LW (long wave) and MW (middle wave) unnecessary
• Less sensitivity deviation due to tracking error
• High S/N: 60 dB
• Signal meter output with good linearity
• Signal meter output voltage inclination setting possible by external resistor.
• Can be used with IF (intermediate frequency) counter turning system or high/low tuning system.
Type Number
µ
PC2533GS-01Set by pin No. 7Set by pin No. 9Depends on SDSD sensitivity of IF counter
µ
PC2533GS-02Set by pin No. 7Set by pin No. 9Tilt of the signal meter
•LO/DX function on-chip
• Since IFT (intermediate frequency transformer) turn ratio is free from limitation for matching of ceramic filter
impedance, it is easy to design MIX gain with IFT.
IF Counter OutputHigh/Low Output
SD Sensitivity Setting
Signal Meter Voltage
Inclination Setting
sensitivity settingsystem and high/low system
can be set independently.
voltage can be set without
regard to SD sensitivity.
Remarks
The information in this document is subject to change without notice.
Document No. S11989EJ4V0DS00 (4th edition)
Date Published August 1998 N CP(K)
Printed in Japan
28GNDGroundGND (high frequency)
29Buff1IN1st IF buffer input
V
ref
29
Z
IN = 15 kΩ ±20 %
30MIX1BYPMIX1 bypass
3330
µ
PC2533
(6/7)
31MIX1OUTMIX1 output
32MIX1OUTMIX1 output
33MIX1INMIX1 input
34RF AGC T.C.RF AGC smoothing
ZIN = 1.2 kΩ ±20 %
3132
V
ref
9
Pin No.SymbolNameEquivalent Circuit
35RF AGC2RF AGC output (cascade base)
Vref
O = 11 kΩ ±20 %
Z
35
36RF AGC1RF AGC output (PIN diode)
µ
PC2533
(7/7)
36
O
= 22 kΩ ±20 %
Z
10
2. Operation of Each Block
2.1 FR Amplifier Circuit Block
VCC
R1
L3
R2
L1
Q1
Q2
L2
C1
+
C9
C8
Fig. 2-1 RF Ampliier Circuit
LPF
L4L5
C3C4C5
C6
33
30
C7
35
36
MIX1
From MIX2
RF AGCL
O/DX
µ
PC2533
Note
C2
34
+
4
Note LO : 3 V or higher
DX : 1 V or lower
In the AM band, the capacitance of a car radio antenna depends on its length, diameter, cable length, etc. Therefore,
µ
J-FET is used in the
PC2533 to raise RF input impedance.
Since the µPC2533 raises the first IF (intermediate frequency) to 10.71 MHz, there is no need for a tuning circuit
between the RF amplifier circuit and MIX1. Instead, it employs an LPF (about 6 MHz) consisting of L4, L5 and C3
to C5 between the RF amplifier circuit and MIX1 in order to cut image frequency (21.4 MHz or higher). Because this
allows a wide-band RF amplifier circuit to be configured without using a tuning circuit, frequency sensitivity deviation
can be minimized to a high degree.
The AGC circuit consists of RF AGC1 by the PIN diode connected to the FET gate and RF AGC2 by the cascade
transistor Q1. Use a low-noise transistor even with low current for the cascade transistor Q1 (if a high-noise one is
used, the S/N ratio deteriorates).
Remark Set bias voltage for cascade transistor Q1 to V
C > VB.
11
2.2 MIX1 Block
Fig. 2-2 MIX1 Block
µ
PC2533
From
LPF
V
T
+
2332
Q101
R11
OSC1
Q105
Q109
1
R107
28
33
30
T1
31
Q106 Q107
To 10.7 MHz
CC
V
17
Q104
Q103Q102
Q108
R109
R110
R108
To RF AGC circuit (Fig. 2-4)
2927
Bias circuit
BPF
R112
Buff1
Note
R111
Note Output impedance and input impedance of Buff1 are 330 Ω and 15 kΩ, respectively.
MIX1 (Q101 to Q108) is a DBM (double balanced mixer).
MIX1 output is supplied to 10.7 MHz ceramic filter via Buff1 (output impedance: 330 Ω) for impedance matching.
The local oscillation signal is applied to the bases of Q101 to Q104, and the RF signal to the base of Q105. MIX1
(Q101 to 108) multiplies the local oscillation signal by RF signal, and converts to the resonance frequency of IFT T1
for output.
µ
The local oscillation signal is output from pin 1 via Q109 (OSC Buff). It has an amplitude of 110 dB
V and can
be directly input to CMOS LSI for use by the PLL synthesizer.
The RF signal applied to the base of Q105 is also input to the detector of the RF AGC circuit.
12
2.3 MIX2 Block
From 10.7 MHz BPF
µ
PC2533
Fig. 2-3 MIX2 Block
V
CC
2823 172425141312 112221
Note
+
Xtal
To IF amplifier
R211
Bias
circuit
R210
R209
To RF AGC circuit (Fig. 2-4)
Current control
circuit
Q201
Q202Q203
Q205
Q206
R207R208
Q204
Q207
R212
Buff2
Note
Q203
OSC2
Q208
From IF AGC (Fig. 2-6)
Note Output impedance and input impedance of Buff2 are 2 kΩ and 30 kΩ, respectively.
MIX2 (Q201 to Q208) is a DBM with a configuration similar to that of MIX1.
The major difference from the MIX1 is that MIX2 is equipped with a current control circuit for output and is controlled
by the AGC.
Input impedance of MIX2 is 330 Ω to match the 10.7 MHz ceramic filter. Output impedance of Buff2 is 2 kΩ to
match the 450 kHz ceramic filter.
IF signal input from pin 23 is also input to the detector of the RF AGC. The RF AGC is detected by both MIX1 and
MIX2 blocks.
The Buff1 and Buff2 ensure impedance matching between MIX1 and MIX2 outputs and each ceramic filter. As
a result, IFT design is not restricted by the need to match ceramic filter impedance. For turn ratio, etc., only conversion
gain need be taken input account, so it is easy to design.
13
2.4 RF AGC Block
Fig. 2-4 RF AGC Block
R412
µ
PC2533
Bias circuit
R402
To RF amplifier
circuit (Fig. 2-1)
Q402
Q401
Q403
R403
R405
Q405
Time
constant
switchover
Q404
R404
R406
353634
Q406
D401
Q407Q408
Detection
and
addition
R409
R410
R408
+
circuit
AMP.
AMP.
+
–
+
–
From MIX2
(Fig. 2-3)
From MIX1
(Fig. 2-2)
The configuration of the RF AGC is shown in Fig. 2-4. After being detected by the RF AGC detector and added,
the input signal from MIX1 and MIX2 is smoothed by external capacitor of pin 34, and its DC voltage controls the RF
AGC.
RF AGC output controls the PIN diode from pin 36 and controls base voltage of cascade transistor which determines
DS from pin 35. In addition, by detecting sudden fluctuation of pin 34 voltage and switching over time constants,
FET V
RF AGC response convergence when the electric field suddenly changes is improved.
Operation start time of the RF AGC can be delayed slightly by connecting a resistor parallel to the external capacitor
of pin 34.
14
2.5 IF Amplifier Block and Detection Block
Fig. 2-5 IF Amplifier and Detection Block
µ
PC2533
From 450kHz BPFTo SD circuit
R19
+
C19
1918
IF amp
T3
17
–
R303
Q301
Q302
15
R304
Bias circuit
R301R302
+
V
CC
Audio
output
From IF AGC circuit
(Fig. 2-6)
To IF AGC circuit
(Fig. 2-6)
In the IF amplifier block, DC feedback is carried to pin 19 via an external low pass filter (composed of T3 and C19)
from pin 18, an output pin. The DC electric potential of pin 18 is designed to be fixed approximately equal to the (+)
side input of the IF amplifier. The value of R19 is the input impedance, so impedance matching to 450 kHz ceramic
filter is possible.
The output signal current of the IF amplifier is converted to signal voltage by being resonated by T3 and input to
the detection circuit after frequency selection.
Emitter follower detection by Q302 is adopted for the detection circuit block.
15
2.6 IF AGC Block
Fig. 2-6 IF AGC Block (for µPC2533GS-01)
µ
PC2533
V
CC
Bias circuit
To SD circuit
(Fig. 2-7)
From SD circuit
(Fig. 2-7)
To MIX2 (Fig. 2-3)To IF amp. (Fig. 2-5)
Signal meter circuit
Note
R501
R502
5 kΩ
5 kΩ
7209
Q503
Q501
D501
Q502
Q504
D502
From detection circuit
(Fig. 2-5)
Time
constant
switchover
Note In the case of PC2533GS-02,
+
the part enclosed by the
dotted line is illustrated as
shown below.
R501
5 kΩ
µ
Voltage
limiter
R502
5 kΩ
IF AGC block configuration is shown in Fig. 2-6. The signal detected from pin 15 is smoothed by the capacitor
of pin 20, and its DC voltage controls the IF AGC.
The IF AGC controls the IF amplifier and MIX2. In the operation sequence, it first controls the gain of the IF amplifier,
then controls the gain of MIX2.
The signal meter circuit output (current output) is in proportion to the DC voltage smoothed by pin 20, and converted
to voltage by the external resistor of pin 7 or 9. Therefore, output voltage value and gain can be set by the value of
the external resistor.
Note
Note For relation between the external resistor and the signal meter, refer to Signal meter output voltage
(adjustment by resistor between pin 9 and GND) in section 4. Characteristic Curves.
16
2.7 Station Detector Circuit Block
(
)
Fig. 2-7 Station Detector Circuit Block
µ
PC2533
ON/OFF
SD AC output
450kHz IF input
(from T3)
Bias circuit
From signal meter
circuit (Fig. 2-6)
+
1.0 V
+
Detection comparator 2
–
–
SD output
Active high
Detection comparator 1
1.0 V
10568
–
+
To time constant
switchover circuit
(Fig. 2-6)
From DTS (request)
The configration station detector (SD) circuit block is shown in Fig. 2-7.
The SD circuit stops scanning or seeking when a broadcast wave is received when auto scanning or seek tuning.
µ
Since the
PC2533 has two outputs (DC high/low signal (open collector) and AC IF signal (f = 450 kHz)), it can be
used according to DTS (digital tuning system) type. Input the SD request signal from DTS to pin 5.
µ
The SD sensitivity setting methods of the
PC2533GS-01 and µPC2533GS-02 differ.
With the µPC2533GS-01, SD sensitivities in the IF counter output system and in the high/low output system are
set by external resistor between pin 7 and GND and by external resistor between pin 9 and GND.
µ
With the
PC2533GS-02, SD sensitivities in both the IF counter output system and high/low output system are set
by external resistor between pin 7 and GND (refer to Fig. 2-6).
Bias circuit
Table 2-1 SD Sensitivity Setting Examples
Value of Resistor between Pin 9 or Pin 7 and GNDSD Sensitivity (AC, DC)
51 kΩ27 dBµV
24 kΩ29 dBµV
10 kΩ33 dBµV
17
µ
PC2533
The reference voltage of the µPC2533-01 and µPC2533-02 detection comparator has been internally fixed at
1.0 V.
Under the influence of R501 (5 kΩ) and R502 (5 kΩ) of the siganl meter circuit (Fig. 2-6), signal meter output voltage
and detection comparator input voltage do not perfectly coincide. For SD sensitivity setting, refer to the following
formula.
Detection comparator input voltage =
Signal meter output voltage × (1 +
Value of resistor between pin 7 and GND
Remark Because DC output is open-collector type (Active high), connect pull-up resistor to pin 10 to use.
R501
)
18
µ
PC2533
3. Electical Characteristics
Absolute Maximum Ratings (TA = 25 °C)
ItemSymbolRatingUnit
Power supply voltageVCC10V
Power dissipationPD600mW
Operating ambient temperatureTA–40 to +85°C
Storage temperatureTstg–55 to +125°C
Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
The device should be operated within the limits specified under DC and AC Characteristics.
Recommended Operating Conditions (T
ItemSymbolConditionsMIN.TYP.MAX.Unit
Power supply voltageVCC7.58.08.5V
Input voltageVIN132dBµV
A = 25 ˚C)
Electrical Characteristics
(Unless specified, TA = 25 °C, VCC = 8 V, fIN = 999 kHz, fMOD = 400 Hz, AMMOD = 30 %, RSD1 (resistor between pin
7 and GND) = R
Circuit currentICCNo input (excluding FET)–4555mA
Detection outputVOVIN = 74 dBµV150180210mVrms
Signal-to-noise ratioS/NVIN = 74 dBµV5360–dB
Total harmonic distortion 1THD1VIN = 74 dBµV–0.31.0%
Total harmonic distortion 2THD2VIN = 74 dBµV, AMMOD = 80 %–0.71.0%
Total harmonic distortion 3THD3VIN = 130 dBµV, AMMOD = 80 %–0.71.5%
Signal meter output voltage 1VS1No input–00.2V
Signal meter output voltage 2VS2VIN = 30 dBµV0.51.52.5V
Signal meter output voltage 3
Local buffer output 1VOSC1-pin load: 20 pF or less106110114dBµV
SD2 (resistor between pin 9 and GND) = 24 kΩ, 15-pin measurement load = 100 kΩ)
ItemSymbolConditionsMIN.TYP.MAX.Unit
Note
VS3VIN = 74 dBµV4.85.56.7V
(4.3)(5.0)(5.5)
Note Specifications in parentheses for signal meter output voltage 3 are for µPC2533GS-02. Values of other items
µ
are the same for
PC2533GS-01 and µPC2533GS-02.
19
µ
Reference Characteristics
ItemSymbolConditionsMIN.TYP.MAX.Unit
Maximum sensitivityMSVIN making VO –10 dB, where–13–dBµV
VO = 0 dB at VIN = 74 dBµV
S/D sensitivity (AC)SS(AC)V IN making SEEK, SD AC–29–dBµV
OUT level 101 dBµV or more
S/D sensitivity (DC)SS(DC)VIN making SEEK, SD AC–29–dBµV
OUT voltage 4.8 V or more
S/D output timeT-SDDelay time from the time when0525ms
changing SEEK VIN = 0 → 40
dBµV to the time when pin 10
voltage becomes 4.8 V or more
Vo stabilization timeT-VOVIN = 60 → 100 dBµV,60160260ms
VO = ±3 dB
TweetTWVIN = 74 dBµV, 2IF–60–dB
2nd local buffer negativeZOSC2Maximum value of a series400––Ω
impedanceresistor with which the crystal
can oscillate
Usable sensitivityUSVIN making S/N = 20 dB–25–dBµV
PC2533
20
4. Characteristic Curves
Input/Output Characteristics (1)
µ
PC2533
MS (VO =
–10 dB)
0
7
–10
6
US (at S/N=20 dB)
–20
5
(dB), Noise (dB)
–30
O
4
–40
3
–50
2
–60
1
Total harmonic level V
–70
0
Total harmonic distortion THD (%), Signal meter voltage (V)
0102030405060708090100 110120130
MS = 14 dB VµUS = 25 dB V
THD 80 %
Input/Output Characteristics (2)
( PC2533GS-01)
µ
Signal meter voltage
( PC2533GS-02)
µ
THD 30 %
µ
Signal input level (dB V)
Noise
µ
V
O
CC
V
f
IN
= 999 kHz
f
MOD
MOD
AM
R
SD1
=8 V
= 400 Hz
= 30 %
= R
SD2
= 24 kΩ
0
7
6
5
MS (VO =
–10 dB)
–10
–20
(dB), Noise (dB)
O
–30
US (at S/N=20 dB)
( PC2533GS-01)
µ
Signal meter voltage
( PC2533GS-02)
µ
4
–40
3
–50
2
–60
1
Detection output level V
–70
0
Total harmonic distortion THD (%), Signal meter voltage (V)
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
S
L
S
K
N
ITEM MILLIMETERS
A15.3±0.24
B0.97 MAX.
C0.8 (T.P.)
D0.37
E0.125±0.075
F1.675
G1.55
H7.7±0.3
I5.6±0.15
J1.05±0.2
K0.22
L0.6±0.2
M0.10
N0.10
R5°±5°
+0.08
−0.07
+0.125
−0.175
+0.08
−0.07
P36GM-80-300B-4
32
µ
PC2533
7. Recommended Soldering Conditions
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering
processes are used, or if the soldering is performed under different conditions, please make sure to consult with our
sales offices.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
Infrared ray reflowPeak temperature: 235 °C or below (Package surface temperature),IR35-00-2
Reflow time: 30 seconds or less (at 210 °C or higher),
Maximum number of reflow processes: 2 times.
VPSPeak temperature: 215 °C or below (Package surface temperature),VP15-00-2
Reflow time: 40 seconds or less (at 200 °C or higher),
Maximum number of reflow processes: 2 times.
Wave solderingSolder temperature: 260 °C or below, Flow time: 10 seconds or less,WS60-00-1
Maximum number of flow processes: 1 time,
Pre-heating temperature: 120 °C or below (Package surface temperature).
Partial heating methodPin temperature: 300 °C or below, –
Heat time: 3 seconds or less (Per each side of the device).
Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or
the device will be damaged by heat stress.
33
[MEMO]
µ
PC2533
34
[MEMO]
µ
PC2533
35
µ
PC2533
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
34
M4 96.5
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