NEC UPA573T Datasheet
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
P-CHANNEL MOS FET (5-PIN 2 CIRCUITS)
FOR SWITCHING
PA573T
The µPA573T is a super-mini-mold device provided with
two MOS FET circuits. It achieves high-density mounting
and saves mounting costs.
FEATURES
• Two source common MOS FET circuits in package the
same size as SC-70
• Directly driven by ICs having a 3 V power supply
• Automatic mounting supported
PACKAGE DIMENSIONS (in millimeters)
2.1 ±0.1
1.25 ±0.1
+0.1
0.2
–0
0.65 0.65
1.3
2.0 ±0.2
0.15
0.9 ±0.1
+0.1
–0.05
0.7
0 to 0.1
EQUIVALENT CIRCUIT
5 4
PIN CONNECTION
(G1)
Gate 1
1 2 3
1. G
2.
3.
4.
5.
Marking: CB
Source
Gate 2
Drain 2
Drain 1
(common)
(G2)
(D2)
(D1)
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
PARAMETER SYMBOL TEST CONDITIONS RATINGS UNIT
Drain to Source Voltage VDSS VGS = 0 –30 V
Gate to Source Voltage VGSS VDS = 0 +7 V
Drain Current (DC) ID(DC) +100 mA
Drain Current (pulse) ID(pulse) PW ≤ 10 ms, Duty Cycle ≤ 50 % +200 mA
Total Power Dissipation PT 200 (Total) mW
Channel Temperature Tch 150 ˚C
Operating Temperature Topt –55 to +80 ˚C
Storage Temperature Tstg –55 to +150 ˚C
Document No. G11245EJ1V0DS00 (1st edition)
Date Published June 1996 P
Printed in Japan
©
1996
µ
PA573T
ELECTRICAL CHARACTERISTICS (TA = 25 ˚C)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Drain Cut-off Current IDSS VDS = –30 V, VGS = 0 –1.0
Gate Leakage Current IGSS VGS = +5 V, VDS = 0 +3.0
Gate Cut-off Voltage VGS(off) VDS = –3 V, ID = –10 µA –1.6 –1.9 –2.3 V
Forward Transfer Admittance |yfs|VDS = –3 V, ID = –10 mA 20 30 S
Drain to Source On-State Resistance
Drain to Source On-State Resistance
RDS(on)1 VGS = –2.5 V, ID = –1 mA 55 100 Ω
RDS(on)2 VGS = –4.0 V, ID = –10 mA 20 25 Ω
Input Capacitance Ciss VDS = –5.0 V, VGS = 0, f = 1 MHz 16 pF
Output Capacitance Coss 13 pF
Reverse Transfer Capacitance Crss 2pF
Turn-On Delay Time td(on) VDD = – 5 V, ID = –10 mA, VGS(on) = –5 V, 10 ns
Rise Time tr
RG = 10 Ω, RL = 500 Ω
40 ns
Turn-Off Delay Time td(off) 130 ns
Fall Time tf 80 ns
µ
A
µ
A
SWITCHING TIME MEASUREMENT CIRCUIT AND CONDITIONS
V
GS
R
PG.
0
V
GS
τ
τ = 1 s
µ
Duty Cycle ≤ 1 %
DUT
L
V
G
R
Gate
voltage
waveform
DD
I
D
Drain
current
waveform
10 %
V
GS(on)
90 %
d(on)
t
0
10 % 10 %
trt
I
D
d(off)
90 %
90 %
t
f
2
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