NEC PD78F0500, PD78F0501, PD78F0502, PD78F0503, PD78F0503D User Manual
...
µ
User’s Manual
78K0/Kx2
8-Bit Single-Chip Microcontrollers
Flash Memory Self Programming
µ
PD78F0500
µ
PD78F0501
µ
PD78F0502
µ
PD78F0503
µ
PD78F0503D
µ
PD78F0511
µ
PD78F0512
µ
PD78F0513
µ
PD78F0513D
µ
PD78F0514
µ
PD78F0515
µ
PD78F0515D
µ
PD78F0521
µ
PD78F0522
µ
PD78F0523
µ
PD78F0524
µ
PD78F0525
µ
PD78F0526
µ
PD78F0527
µ
PD78F0527D
µ
PD78F0531
µ
PD78F0532
µ
PD78F0533
µ
PD78F0534
µ
PD78F0535
µ
PD78F0536
µ
PD78F0537
µ
PD78F0544
µ
PD78F0545
µ
PD78F0546
µ
PD78F0547
µ
PD78F0547D
PD78F0537D
Document No. U17516EJ1V0UM00 (1st edition)
Date Published August 2005 N CP(K)
2005
Printed in Japan
[MEMO]
2 User’s Manual U17516EJ1V0UM
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distor tion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
IL
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
User’s Manual U17516EJ1V0UM 3
•
The information in this document is current as of July, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
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•
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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M8E 02. 11-1
4 User’s Manual U17516EJ1V0UM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
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Device availability
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Ordering information
•
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•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
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J05.6
User’s Manual U17516EJ1V0UM 5
INTRODUCTION
Readers This manual is intended for users who wish to understand the functions of the flash
memory versions of the 78K0/Kx2 and design application systems using these
microcontrollers.
Purpose This manual is intended to give users an understanding of the usage of the flash
memory self programming sample library which is used when rewriting the 78K0/Kx2
flash memory.
Organization This manual can be generally divided into the following sections.
• Description of flash environment
• Description of flash memory self programming sample library
How to Read This Manual It is assumed that the readers of this manual have general knowled ge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To check the hardware functions of the 78K0/Kx2
→ Refer to the user’s manual of each 78k0/Kx2 product.
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary … xxxx or xxxxB
Decimal … xxxx
Hexadecimal … xxxxH
6 User’s Manual U17516EJ1V0UM
Terminology The following describes the meanings of certain terms used in this manual.
• Self programming
Self programming operations are flash memory write operations th at are performed
by user programs.
• Flash memory self programming sample library
This is the library that is provided by the 78K0/Kx2 for flash memory manipulation.
• Flash environment
This is the environment that supports flash memory manipulations. It has
restrictions that differ from those applied to ordinary program execution.
• Block number
Block numbers indicate blocks in flash memory. They are used as units during
manipulations such as erasures and blank checks.
• Boot cluster
This is the area that is used for boot swapping. Boot cluster 0 and boot cluster 1
are provided and the cluster to be booted can be selected.
• Entry RAM
This is the area in RAM that is used by the flash memory self programmi ng sample
library. The user program reserves this area and specifies the start address of the
specific area to be used when the library is called.
• Internal verification
After writing to flash memory, signal levels are checked internally to confirm correct
reading of data. When an internal verification error occurs, the corresponding
device is judged as faulty.
User’s Manual U17516EJ1V0UM 7
CONTENTS
CHAPTER 1 GENERAL........................................................................................................................... 11
1.1 Overview..................................................................................................................................... 11
1.2 Calling Self Programming Sample Library ............................................................................. 11
1.3 Bank Number and Block Number ............................................................................................14
1.4 Processing Time and Acknowledging Interrupt.....................................................................17
CHAPTER 2 PROGRAMMING ENVIRONMENT .................................................................................... 20
2.1 Hardware Environment.............................................................................................................. 20
2.2 Software Environment...............................................................................................................21
2.2.1 Entry RAM........................................................................................................................................... 22
2.2.2 Stack and data buffer...........................................................................................................................23
CHAPTER 3 INTERRUPT SERVICING DURING SELF PROGRAMMING............................................ 24
3.1 Overview..................................................................................................................................... 24
3.2 Interrupt Response Time........................................................................................................... 27
3.3 Description Example................................................................................................................. 29
3.4 Cautions ..................................................................................................................................... 31
CHAPTER 4 BOOT SWAP FUNCTION...................................................................................................32
CHAPTER 5 SELF PROGRAMMING SAMPLE LIBRARY..................................................................... 39
5.1 Type of Self Programming Sample Library............................................................................. 39
5.2 Explanation of Self Programming Sample Library.................................................................40
self programming start library .....................................................................................................................41
initialize library ............................................................................................................................................43
mode check library...................................................................................................................................... 45
block blank check library .............................................................................................................................47
block erase library....................................................................................................................................... 51
word write library......................................................................................................................................... 55
block verify library....................................................................................................................................... 60
self programming end library ......................................................................................................................64
get information library .................................................................................................................................66
set information library.................................................................................................................................. 72
EEPROM write library.................................................................................................................................76
CHAPTER 6 DETAILS OF SELF PROGRAMMING CONTROL.............................................................81
6.1 Registers That Control Self Programming.............................................................................. 81
6.1.1 Flash programming mode control register (FLPMC)............................................................................ 81
6.1.2 Flash protect command register (PFCMD)..........................................................................................83
6.1.3 Flash status register (PFS)..................................................................................................................84
6.1.4 Self programming control parameters..................................................................................................85
APPENDIX A SAMPLE PROGRAM........................................................................................................90
A.1 User Program.............................................................................................................................90
A.2 Self Programming Library (Normal Model)...........................................................................103
A.3 Self Programming Library (Static Model)..............................................................................118
A.4 Boot Swap ................................................................................................................................132
A.5 Compiling the Flash Self Programming Sample Library and Sample Program................137
APPENDIX B INDEX..............................................................................................................................138
8
User’s Manual U17516EJ1V0UM
LIST OF FIGURES
Figure 1-1 Flow of Self Programming (rewriting contents of flash memory).......................................................12
Figure 1-2 Block Numbers and Boot Clusters (flash memory of up to 60 KB) ...................................................15
Figure 1-3 Block Numbers and Boot Clusters (flash memory of 96 KB or more)...............................................16
Figure 2-1 FLMD0 Voltage Generator................................................................................................................20
Figure 2-2 Allocation Range of Entry RAM........................................................................................................22
Figure 2-3 Allocatable Range for Stack Pointer and Data Buffer .......................................................................23
Figure 3-1 Flow of Processing in Case of Interrupt............................................................................................ 25
Figure 4-1 Flow of Boot Swapping.....................................................................................................................33
Figure 5-1 Flow of Self Programming Start Library............................................................................................ 42
Figure 5-2 Flow of Initialize Library....................................................................................................................44
Figure 5-3 Flow of Mode Check Library.............................................................................................................46
Figure 5-4 Flow of Block Blank Check Library................................................................................................... 50
Figure 5-5 Flow of Block Erase Library..............................................................................................................54
Figure 5-6 Flow of Word Write Library ...............................................................................................................59
Figure 5-7 Flow of Block V e rify Library............................................................................................................... 63
Figure 5-8 Flow of Self Programming End Library.............................................................................................65
Figure 5-9 Flow of Get Information Library ........................................................................................................71
Figure 5-10 Flow of Set Information Library.........................................................................................................75
Figure 5-11 Flow of EEPROM Write Library........................................................................................................ 80
Figure 6-1 Self Programming Operation Mode and Memory Map (µPD78F0545).............................................82
Figure 6-2 Write Protection................................................................................................................................83
User’s Manual U17516EJ1V0UM
9
LIST OF TABLES
Table 1-1 Processing Time and Acknowledging Interrupt (with internal high-speed oscillator).........................18
Table 1-2 Processing Time and Acknowledging Interrupt (with external system clock used) ...........................19
Table 2-1 Software Resources .........................................................................................................................21
Table 3-1 Resume Processing Stopped by Interrupt ........................................................................................26
Table 3-2 Interrupt Response Time (with Internal High-Speed Oscillator)........................................................27
Table 3-3 Interrupt Response Time (with External System Clock)....................................................................28
Table 5-1 Self programming sample library List................................................................................................39
Table 6-1 Register Bank 3 Parameter List........................................................................................................86
Table 6-2 Entry RAM Parameter List................................................................................................................87
Table 6-3 Data Buffer Parameter List................................................................................................................88
Table 6-4 Detailed Flash Information for Get Information Function...................................................................89
10
User’s Manual U17516EJ1V0UM
CHAPTER 1 GENERAL
1.1 Overview
The self programming sample library is firmware provided on the 78K0/Kx2, and is software which is used to rewrite
data in the flash memory.
By calling the self programming sample library from a user program, the contents of the flash memor y can be
rewritten and, consequently, the period for software development can be substantially shortened.
Cautions 1. Because the self programming sample library rewrites the contents of the flash memory by
using the CPU, registers, and RAM of the 78K0/Kx2, a user program cannot be executed while
processing of the self programming sample library is being executed.
2. The self programming sample library uses the CPU (register bank 3) and a work area (100
bytes of entry RAM). Therefore, the user must save the data necessary for the user program
in that area immediately before calling the self programming sample library.
1.2 Calling Self Programming Sample Library
The self programming sample library can be called by a user program in C or an assembly language.
If the -SM option (that uses an object as a static model) is specified when a file written in C is complie d, use (link)
the library for static models. If the -SM option is not specified, link the library for normal models.
If the file is written in an assembly language, use (link) the library for static models.
User’s Manual U17516EJ1V0UM
11
CHAPTER 1 GENERAL
k
The following flowchart illustrates how to rewrite the contents of the flash memory by using the self programming
sample library.
Figure 1-1. Flow of Self Programming (rewriting contents of flash memory)
Starting self programming
<1>
<2>
<3>
<4>
<5>
<6>
<8>
FLMD0 pin: Low → High
FlashStart
Setting operating environment
FlashEnv
CheckFLMD
Normal
completion?
Yes
FlashBlockBlankChec
Erased?
Yes
<7>
FlashWordWrite
No
No
FlashBlockErase
Normal
completion?
Yes
No
No
No
<9>
<10>
<11>
Normal
completion?
Yes
FlashBlockVerify
Normal
completion?
Yes
FlashEnd
FLMD0 pin: High → Low
End of self programming
12
User’s Manual U17516EJ1V0UM
CHAPTER 1 GENERAL
<1> Preprocessing (setting of hardware environment)
As preprocessing, make the FLMD0 pin high (refer to 2.1 Hardware Environment).
<2> Preprocessing (declaring start of self programming)
As preprocessing, call the self programming start library FlashStart to declare the start of self programming.
<3> Preprocessing (setting of software environment)
As preprocessing, save register bank 3 and specify a work area (refer to 2.2 Software Environment).
<4> Preprocessing (initializing entry RAM)
As preprocessing, call the initialize library FlashEnv to initialize the entry RAM.
<5> Preprocessing (checking voltage level)
As preprocessing, call the mode check library CheckFLMD and check the voltage level.
<6> Checking erasing of specified block (1 KB)
Call the block blank check library FlashBlockBlankCheck to check if the specified block (1 KB) has been erased.
<7> Erasing specified block (1 KB)
Call the block erase library FlashBlockErase to erase a specified block (1 KB).
<8> Writing data of 1 to 64 words to specified addresses
Call the word write library FlashWordWrite to write data of 1 to 64 words to specified addresses.
<9> Verifying specified block (1 KB) (internal verification)
Call the block verify library FlashBlockVerify to verify a specified block (1 KB) (internal verification).
<10> Post-processing (declaring end of self programming)
As post-processing, call the self programming end library FlashEnd to declare the end of self programming.
<11> Post-processing (setting of hardware environment)
As post-processing, return the level of the FLMD0 pin to the low level.
User’s Manual U17516EJ1V0UM
13
CHAPTER 1 GENERAL
1.3 Bank Number and Block Number
Products in the 78K0/Kx2 Series having flash memor y of up to 60 KB have their flash memory divided into 1 KB
blocks. Erasing, blank checking, and verification (internal verification) for self programming are performed in these
block units. To call the self programming sample library, a block number is specified.
Addresses 0000H to 0FFFH and 1000H to 1FFFH of the 78K0/Kx2 are allocated for boot clusters. A boot cluster is
an area that is used to prevent the vector table data and basic functions of the program from being destroyed, and to
prevent the user program from being unable to start due to a power failure or because the device was reset while an
area including a vector area was being rewritten. For details on the boot cluster, refer to CHAPTER 4 BOOT SWAP
FUNCTION.
Figure 1-2 shows the block numbers and boot clusters of a flash memory of up to 60 KB.
78K0/Kx2 products having flash memory of more than 96 KB have banks in an area that is larger than 32 KB. For
these products, not only a block number but also a bank number must be specified to call the self programming sample
library when performing erasing, blank checking, or verification (internal verification) in the are a that is larger than 32
KB during self programming.
Figure 1-3 shows the block numbers and boot clusters of a flash memory of more than 96 KB.
14
User’s Manual U17516EJ1V0UM
CHAPTER 1 GENERAL
000
Figure 1-2. Block Numbers and Boot Clusters (flash memory of up to 60 KB)
8000H
7C00H
7800H
7400H
7000H
6C00H
6800H
6400H
6000H
5C00H
5800H
5400H
5000H
4C00H
4800H
4400H
4000H
3C00H
3800H
3400H
3000H
2C00H
2800H
2400H
2000H
1C00H
1800H
1400H
1000H
0C00H
0800H
0400H
0000H
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
F800H
Internal expansion RAM
H
F
EC00H
E800H
E400H
E000H
DC00H
D800H
D400H
D000H
CC00H
C800H
C400H
C000H
BC00H
B800H
B400H
B000H
AC00H
A800H
A400H
A000H
9C00H
9800H
9400H
9000H
8C00H
8800H
8400H
8000H
2000H
1FFFH
0FFFH
0000H
User’s Manual U17516EJ1V0UM
Block 59
Block 58
Block 57
Block 56
Block 55
Block 54
Block 53
Block 52
Block 51
Block 50
Block 49
Block 48
Block 47
Block 46
Block 45
Block 44
Block 43
Block 42
Block 41
Block 40
Block 40
Block 39
Block 38
Block 37
Block 36
Block 35
Block 34
Block 33
Block 32
Boot cluster 1
Boot cluster 0
1FFFH
17FFH
1081H
1080H
107FH
0FFFH
0800H
07FFH
0081H
0080H
007FH
003FH
0000H
CALLF entry
2048 bytes
Program area
1919 bytes
Option byte
CALLT table 64 bytes
Vector table 64 bytes
CALLF entry
2048 bytes
Program area
1919 bytes
Option byte
CALLT table 64 bytes
Vector table 64 bytes
Area subject to boot
swapping
15
CHAPTER 1 GENERAL
Figure 1-3. Block Numbers and Boot Clusters (flash memory of 96 KB or more)
8000H
7C00H
7800H
7400H
7000H
6C00H
6800H
6400H
6000H
5C00H
5800H
5400H
5000H
4C00H
4800H
4400H
4000H
3C00H
3800H
3400H
3000H
2C00H
2800H
2400H
2000H
1C00H
1800H
1400H
1000H
0C00H
0800H
0400H
0000H
16
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
F800H
Internal expansion RAM
E000H
DFFFH
Use prohibited
C000H
BC00H
B800H
B400H
B000H
AC00H
A800H
A400H
A000H
9C00H
9400H
9000H
8C00H
8800H
8400H
8000H
2000H
1FFFH
0FFFH
0000H
Boot cluster 1
Boot cluster 0
Block 47
Block 46
Block 45
Block 44
Block 43
Block 42
Block 41
Block 40
Block 40
Block 39
Block 38
Block 37
Block 36
Block 35
Block 34
Bank 1
Bank 3
Bank 2
1FFFH
Block 33
Block 32
17FFH
Bank0
1081H
1080H
107FH
User’s Manual U17516EJ1V0UM
0FFFH
0800H
07FFH
0081H
0080H
007FH
003FH
0000H
Bank 5
Bank 4
CALLF entry
2048 bytes
Program area
1919 bytes
Option byte
CALLT table 64 bytes
Vector table 64 bytes
CALLF entry
2048 bytes
Program area
1919 bytes
Option byte
Vector table 64 bytes
Area subject to boot
swapping
CHAPTER 1 GENERAL
1.4 Processing Time and Acknowledging Interrupt
Table 1-1 and Table 1-2 show the processing time of the self programming sample library and whether interrupts can
be acknowledged. Table 1-1 shows a case where an inter nal high-speed oscillator is us ed for the main system clock
and Table 1-2 shows a case where an external system clock is used for the main system clock.
The self programming sample library that can acknowledge interrupts has a function to check if an interrupt is
generated while processing of the self programming sample library is under execution, and a function to perform
post-processing if an interrupt has been generated.
For details on interrupts, refer to CHAPTER 3 INTERRUPT SERVICING DURING SELF PROGRAMMING.
User’s Manual U17516EJ1V0UM
17
18
User’s Manual U17516EJ1V0UM
Table 1-1. Processing Time and Acknowledging Interrupt (with internal high-speed oscillator)
Library Name
self programming start library 4.25 Not acknowledged
initialize library 977.75 443.5 Not acknowledged
mode check library 753.875 753.125 219.625 218.875 Not acknowledged
block blank check library 12770.875 12765.875 12236.625 12231.625 Acknowledged
block erase library 36909.5 356318 36904.5 356296.25 36363.25 355771.75 36358.25 355750 Acknowledged
word write library
block verify library 25618.875 25613.875 25072.625 25067.625 Acknowledged
self programming end library 4.25 Not acknowledged
get information library
(option value: 03H)
get information library
(option value: 04H)
get information library
(option value: 05H)
set information library 105524.75 790809.375 105523.75 790808.375 104978.5 541143.125 104977.5 541142.125 Acknowledged
EEPROM write library
1214
(1214.375)
1496.5
(1496.875)
Remark Values in parentheses are when the write start address structure is placed outside of internal high-speed RAM.
Processing Time (unit: microseconds)
Outside short direct addressing range In short direct addressing range
Normal model Static model Normal model Static model
Min Max Min Max Min Max Min Max
2409
(2409.375)
871.25
(871.375)
863.375
(863.5)
1042.75
(1043.625)
2691.5
(2691.875)
1207
(1207.375)
(866.125)
(1038.375)
1489.5
(1489.875)
(2402.375)
866
858.125
(858.25)
1037.5
(2684.875)
2402
2684.5
679.75
(680.125)
(337.125)
(503.125)
962.25
(962.625)
337
329.125
(239.25)
502.25
1874.75
(1875.125)
2157.25
(2157.625)
672.75
(673.125)
(331.875)
(497.875)
955.25
(955.625)
1867.75
(1868.125)
331.75
323.875
(324)
497
2150.25
(2150.625)
Acknowledging
Acknowledged
Not acknowledged
Not acknowledged
Not acknowledged
Acknowledged
Interrupt
CHAPTER 1 GENERAL
Table 1-2. Processing Time and Acknowledging Interrupt (with external system clock used)
User’s Manual U17516EJ1V0UM
Library Name
self programming start library 34/fX
initialize library 49X
mode check library 35/fX
block blank check library 174/fX
block erase library
174/f
+ 31093.875
word write library
318(321)/f
+ 644.125
block verify library 174/fX
self programming end library 34X
get information library
171(172)/f
(option value: 03H)
get information library
181(182)/f
(option value: 04H)
get information library
404(411)/f
(option value: 05H)
set information library
75/f
+ 79157.6875
EEPROM write library
318(321)/f
+ 799.875
Note fX: Operating frequency of external system clock
Remark Values in parentheses are when the write start address structure is placed outside of internal high-speed RAM.
Processing Time (unit: microseconds)
Outside short direct addressing range In short direct addressing range
Acknowledging
Normal model Static model Normal model Static model
Min Max Min Max Min Max Min Max
Note
Not acknowledged
Note
+ 485.8125 49/fX
Note
+ 374.75 29/fX
Note
+ 6382.0625 134/fX
Note
X
174/f
Note
X
+
298948.125
Note
X
318(321)/f
Note
X
+ 1491.625
Note
+ 13448.5625 134/fX
Note
X
+ 432.4375 129(130)/fX
Note
X
+ 427.875 139(140)/fX
Note
X
+ 496.125 362(369)/fX
Note
X
75/f
Note
X
+ 652400
Note
X
318(321)/f
Note
X
+ 1647.375
Note
Note
Note
134/fX
+ 31093.875
262(265)/f
Note
X
+ 644.125
Note
Note
67/f
X
+ 79157.6875
262(265)/f
Note
X
+ 799.875
+ 374.75 35/fX
+ 6382.0625 174/fX
Note
134/f
X
+ 298948.125
262(265)/f
+ 1491.625
Note
X
174/f
+ 30820.75
318(321)/f
+ 383
+ 13448.5625 174/fX
Note
Not acknowledged
Note
+ 432.4375 171(172)/fX
Note
+ 427.875 181(182)/fX
Note
+ 496.125 404(411)/fX
Note
67/f
X
+ 652400
262(265)/f
+ 1647.375
X
+ 78884.5625
Note
318(321)/f
+ 538.75
75/f
X
Note
+ 113.625 29/fX
Note
+ 6120.9375 134/fX
Note
X
Note
318(321)/f
X
Note
+ 13175.4375 134/fX
Note
+ 171.3125 129(130)/fX
Note
+ 166.75 139(140)/fX
Note
+ 231.875 362(369)/fX
Note
+ 527566.875
Note
318(321)/f
X
Note
Note
174/f
X
+ 298675
+ 1230.5
Note
75/f
X
+ 1386.25
+ 224.6875 Not acknowledged
Note
+ 113.625 Not acknowledged
Note
+ 6120.9375 Acknowledged
Note
262(265)/f
X
+ 78884.5625
Note
262(265)/f
X
Note
134/f
X
+ 30820.75
X
+ 383
Note
Note
67/f
X
X
+ 538.75
Note
262(265)/f
+ 13175.4375 Acknowledged
Note
+ 171.3125 Not acknowledged
Note
Note
+ 527566.875
Note
262(265)/f
Note
134/f
X
Acknowledged
+ 298675
Note
X
Acknowledged
+ 1230.5
+ 166.75 Not acknowledged
+ 231.875 Not acknowledged
Note
67/f
X
Acknowledged
Note
X
Acknowledged
+ 1386.25
Interrupt
CHAPTER 1 GENERAL
19
k
Ω
CHAPTER 2 PROGRAMMING ENVIRONMENT
This chapter explains the hardware environment and software environment necessary for the user to rewrite flash
memory by using the self programming sample library.
2.1 Hardware Environment
To execute self programming, a circuit that controls the voltage on the FLMD0 pin of the 78K0/Kx2 is necessary.
The voltage on the FLMD0 pin must be low while an ordinary user program is being executed (in normal operation
mode) and high while self programming is being executed (in flash rewriting mode).
While the FLMD0 pin is low, the firmware and software for rewriting run, but the circuit for rewriting flash memory
does not operate. Therefore, the flash memory is not actually rewritten.
A self programming sample library that makes the FLMD0 pin high is not provided. Therefore, to rewrite the flash
memory, the voltage level of the FLMD0 pin must be made high by manipulating a port throu gh user program, before
calling the self programming start library.
Here is an example of the circuit that changes the voltage on the FLMD0 pin by manipulating a port.
Figure 2-1. FLMD0 Voltage Generator
78K0/Kx2
FLMD0
Output port
10
(recommended)
20
User’s Manual U17516EJ1V0UM
CHAPTER 2 PROGRAMMING ENVIRONMENT
2.2 Software Environment
The self programming sample library allocates its program to a user area and consumes about 500 bytes of the
program area. The self programming sample librar y itself uses the CPU (register bank 3), work area (entry RAM),
stack, and data buffer.
The following table lists the necessary software resources.
Table 2-1. Software Reso urces
Item Description Restriction
CPU Register bank 3
Work area Entry RAM: 100 bytes
Stack 39 bytes max.
Remark Use the same stack as for the
user program.
Data buffer 1 to 256 bytes
Remark The size of this buffer varies
depending on the writing unit
specified by the user program.
Program area
Normal model: 525 bytes
Static model: 432 bytes
Remark Supplied as an
assembly-language source.
Internal high-speed RAM outside short addressing range or
internal high-speed RAM in short direct addressing range with
first address as FE20H (Refer to 2.2.1 Entry RAM.)
Internal high-speed RAM other than FE20H to FE83H (Refer to
2.2.2 Stack and data buffer.)
Internal high-speed RAM other than FE20H to FE83H (Refer to
2.2.2 Stack and data buffer.)
Within 0000H to 7FFFH (32 KB)
Caution The self programming sample library and the
user program that calls the self programming
sample library must always be located within the
above range, because the firmware built into the
product is allocated to addresses starting from
8000H.
Cautions 1. The self programming operation is not guaranteed if the user manipulates the above
resources. Do not manipulate these resources during a self programming operation.
2. The user must release the above resources used by the self programming sample library
before calling the self programming sample library.
−
User’s Manual U17516EJ1V0UM
21
CHAPTER 2 PROGRAMMING ENVIRONMENT
2.2.1 Entry RAM
The self programming sample library uses a work area of 100 bytes. This area is called entry RAM.
As the entry RAM, 100 bytes are automatically allocated, star ting from the first address that is specified when th e
initialize library is called. Therefore, the first address of the entry RAM can be specified in the range from FB00H to
FE20H.
In addition, a data buffer used by the initialize library to actually write data to the flash memory must be allocated to
an area that is within the range from 1 to 256 bytes and is other than the work area. For details on the data buffer,
refer to 2.2.2 Stack and data buffer.
The range in which the entry RAM can be allocated is shown below.
Figure 2-2. Allocation Range of Entry RAM
FFFFH
FF20H
FF00H
FEFFH
Special function registers (SFRs)
256 bytes
General-purpose registers
32 bytes
Short direct addressing
FE83H
FE20H
FB00H
FAFFH
FA20H
FA00H
F9FFH
F800H
F7FFH
Internal high-speed RAM
1024 bytes
Use prohibited
Buffer RAM 32 bytes
Use prohibited
Entry RAM allocation range
Internal expansion high-speed RAM
1024 bytes
Caution The size of the internal expansion high-speed RAM varies depending on the product.
For the size of the internal expansion high-speed RAM, refer to the user’s manual of each
product.
22
User’s Manual U17516EJ1V0UM
CHAPTER 2 PROGRAMMING ENVIRONMENT
2.2.2 Stack and data buffer
The self programming sample library writes data to flash memory by using the CPU. Therefore, a self
programming operation is performed by using the stack specified by the user program.
The stack must be allocated by stack processing of the self programming operation so that the entry RAM and the
RAM used by the user are not cleared. Therefore, the stack can be allocated in the internal high-speed RAM at
addresses other than FE20H to FE83H.
A data buffer is automatically allocated from the first address and by the number of data specified when the word
write library is called. Therefore , the first address of the data b uffer can be specified in the internal high-speed RAM at
an address other than FE20H to FE83H, just as for the stack pointer.
Note that data to be written to the flash memory must be appropri ately set and processed before the word write
library is called.
The following figure shows the range in which the stack pointer and data buffer can be allocated.
Figure 2-3. Allocatable Range for Stack Pointer and Data Buffer
FFFFH
FF20H
FF00H
FEFFH
Special function registers (SFRs)
256 bytes
General-purpose registers
32 bytes
Short direct addressing
FE83H
FE20H
Use prohibited
FB00H
FAFFH
FA20H
FA00H
F9FFH
F800H
F7FFH
Internal high-speed RAM
1024 bytes
Use prohibited
Buffer RAM 32 bytes
Use prohibited
Range where stack and data buffer can be
allocated (except FE20H to FE83H)
Internal expansion high-speed RAM
1024 bytes
Caution The size of the internal expansion high-speed RAM varies depending on the product.
For the size of the internal expansion high-speed RAM, refer to the user’s manual of each
product.
User’s Manual U17516EJ1V0UM
23
CHAPTER 3 INTERRUPT SERVICING DURING SELF
PROGRAMMING
3.1 Overview
An interrupt can be generated, even while self programming is executed, in some self progr amming sample libraries
of the 78K0/Kx2.
However, unlike the case for an ordinary interrupt, the user must decide whether the processing that has been
interrupted should be resumed, by checking the return value from the self programming sample library.
24
User’s Manual U17516EJ1V0UM
CHAPTER 3 INTERRUPT SERVICING DURING SELF PROGRAMMING
The following figure illustrates the flow of processing if an interrupt is generated while processing of the self
programming sample library is being executed.
Figure 3-1. Flow of Processing in Case of Interrupt
User program Library Interrupt handler
Self programming starts.
FLMD0 pin: Low → High
Interrupt
FlashStart
Setting of operating environment
occurs.
Servicing starts.
Servicing ends.
DI
Calling library
EI
Return value
End
FlashEnd
FLMD0 pin: High → Low
1
Stopped (= 1FH)
Retry?
No
Servicing starts.
Processing is stopped.
Yes
1
End of self programming
User’s Manual U17516EJ1V0UM
25
CHAPTER 3 INTERRUPT SERVICING DURING SELF PROGRAMMING
The following table shows how the processing of the self programming sample libraries that acknowledge interrupts
is resumed after the processing has been stopped by the occurrence of an interrupt.
Table 3-1. Resume Processing Stopped by Interrupt
Library Name Resuming Method
block blank check library
block erase library
word write library
block verify library
set information library
EEPROM write library
Call the block blank check library FlashBlockBlankCheck to resume processing to check
block erasure that has been stopped by the occurrence of an interrupt.
To resume processing to erase blocks that was stopped by the occurrence of an
interrupt, call the block blank check library FlashBlockBlankCheck and check whether
blocks that should be erased have been erased. Then, call the block erase library
FlashBlockErase.
Call the word write library FlashWordWrite to resume data write processing that was
stopped by the occurrence of an interrupt.
Call the block verify library FlashBlockVerify to resume block verify processing that was
stopped by the occurrence of an interrupt.
Call the set information library FlashSetInfo to resume flash information setting
processing that was stopped by the occurrence of an interrupt.
Call the EEPROM write library FlashEEPROMWrite to resume processing to write data
during EEPROM emulation that was stopped by the occurrence of an interrupt.
Remark An interrupt is not acknowledged until all of the processing of the above self programming sample
libraries has been completed, because these libraries execute their processing with interrupts disabled.
26
User’s Manual U17516EJ1V0UM
CHAPTER 3 INTERRUPT SERVICING DURING SELF PROGRAMMING
3.2 Interrupt Response Time
Unlike the case for an ordinary interrupt, generation of an interrupt during execution of self programming is
accomplished via post-interrupt serv icing in the self programming sample library (such as setting 0x 1F as the return
value from the self programming sample library). Consequently, the response time is longer than that for an ordinary
interrupt.
When an interrupt occurs during self programming execution, both the interrupt response time of the self
programming sample library, as well as the interrupt response time of the device used, are necessary.
Remark For the response time of each device, refer to the user’s manual of each device.
Table 3-2 and Table 3-3 show the interrupt response time of the self programming sample library. Table 3-2 is a
case where the internal high-speed oscillator is used to generate the main system clock, and Table 3-3 is a case where
an external system clock is used as the main system clock.
Table 3-2. Interrupt Response Time (with Internal High-Speed Oscillator)
Interrupt Response Time (Unit: Microseconds)
Library Name
block blank check library 391.25 1300.5 81.25 727.5
block erase library 389.25 1393.5 79.25 820.5
word write library 394.75 1289.5 84.75 716.5
block verify library 390.25 1324.5 80.25 751.5
set information library 387 852.5 77 279.5
EEPROM write library 399.75 1395.5 89.75 822.5
Entry RAM outside short direct addressing
range
Min Max Min Max
Remark An interrupt is not acknowledged until all of the processing of the above self programming sample
libraries has been completed, because these libraries execute their processing with interrupts disabled.
Entry RAM inside short direct addressing
range (from FE20H)
User’s Manual U17516EJ1V0UM
27
CHAPTER 3 INTERRUPT SERVICING DURING SELF PROGRAMMING
Table 3-3. Interrupt Response Time (with External System Clock)
Interrupt Response Time (Unit: Microseconds)
Library Name
Entry RAM outside short direct addressing
range
Entry RAM inside short direct addressing
range (from FE20H)
Min Max Min Max
block blank check library 18/fx
block erase library 18/fx
word write library 22/fx
block verify library 18/fx
set information library 16/fx
EEPROM write library 22/fx
Note
+ 192 28/fx
Note
+ 186 28/fx
Note
+ 189 28/fx
Note
+ 192 28/fx
Note
+ 190 28/fx
Note
+ 191 28/fx
Note
+ 698 18/fx
Note
+ 745 18/fx
Note
+ 693 22/fx
Note
+ 709 18/fx
Note
+ 454 16/fx
Note
+ 783 22/fx
Note
+ 55 28/fx
Note
+ 49 28/fx
Note
+ 52 28/fx
Note
+ 55 28/fx
Note
+ 53 28/fx
Note
+ 54 28/fx
Note
+ 462
Note
+ 509
Note
+ 457
Note
+ 473
Note
+ 218
Note
+ 547
Note fX: Operating frequency of external system clock
Remark An interrupt is not acknowledged until all of the processing of the above self programming sample
libraries has been completed, because these libraries execute their processing with interrupts disabled.
28
User’s Manual U17516EJ1V0UM
CHAPTER 3 INTERRUPT SERVICING DURING SELF PROGRAMMING
3.3 Description Example
This section shows an example of writing a user program that resumes erase processing that was stopped by the
occurrence of an interrupt during execution of a self programming sample library (block erase library).
User’s Manual U17516EJ1V0UM
29
CHAPTER 3 INTERRUPT SERVICING DURING SELF PROGRAMMING
ERS_RTRY:
; Main processing
MOV A, #0 ; Sets 0 as the bank number of the block to be erased.
MOV B, #10 ; Sets 10 as the block number of the block to be erased.
DI ; Disables interrupts.
CALL !_FlashBlockErase ; Calls the block erase library.
EI ; Enables interrupts.
CMP A, #1FH ; Checks whether a stop status is set.
BZ $BLN_RTRY ; If the stop status is set,
; jumps to resume processing BLN_RTRY.
CMP A, #00H ; Checks whether execution has been correctly
completed.
BNZ $ERS_FALSE_END ; Jumps to abnormal termination ERS_FALSE_END if
execution has not been correctly completed.
BR ERS_TRUE_END
BLN_RTRY:
; Resume processing
MOV A, #0 ; Sets 0 as the bank number of the block to be
blank-checked.
MOV B, #10 ; Sets 10 as the block number of the block to be
blank-checked.
DI ; Disables interrupts.
; Calls the block blank check library.
CALL !_FlashBlockBlankCheck
EI ; Enables interrupts.
CMP A, #1FH ; Checks whether a stop status is set.
BZ $BLN_RTRY ; If the stop status is set,
; retries the resume processing.
CMP A, #00H ; Checks whether execution has been correctly
completed.
BNZ $ERS_RTRY ; Retries the main processing if execution has not been
correctly completed.
; Clears the internal status of the stop processing
MOVW AX, #EntryRAM ; Sets the first address of entry RAM.
CALL !_FlashEnv ; Calls the initialize library.
ERS_TRUE_END:
; Normal completion
ERS_FALSE_END:
; Abnormal termination
Caution It is assumed that the entry RAM has already been set.
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User’s Manual U17516EJ1V0UM
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