NEC PD784927, PD784928, PD784927Y, PD784928Y DATA SHEET

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PD784927, 784928, 784927Y, 784928Y

DESCRIPTION

The µPD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a high-

speed, high-performance 16-bit CPU for VCR software servo control.

PD784927Y and 784928Y are based on the µPD784928 with the addition of an I2C bus interface compatible

The

with multi-master.

They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer

unit) for software servo control and VCR analog circuits.

Flash memory models, the

DATA SHEET

MOS INTEGRATED CIRCUIT

16-BIT SINGLE-CHIP MICROCONTROLLER

PD78F4928 and µPD78F4928Y, are under development.

The functions of the

manual before designing your system.

PD784928, 784928Y Subseries User’s Manual - Hardware : U12648E

78K/IV Series User’s Manual - Instruction : U10905E

FEATURES

High instruction execution speed realized by 16-bit CPU core

•

• Minimum instruction execution time: 250 ns (with 8 MHz internal clock) High internal memory capacity

•

Item Internal ROM capacity 96K bytes 128K bytes

Internal RAM capacity 2048 bytes 3584 bytes

VCR analog circuits conforming to VHS Standard

•

• CTL amplifier • DFG amplifier • Reel FG comparator (2 channels)

• RECCTL driver (rewritable) • DPG amplifier • CSYNC comparator

• CFG amplifier • DPFG separation circuit (ternary separation circuit) Timer unit (super timer unit) for servo control

•

Serial interface : 3 channels

•

3-wire serial I/O : 2 channels

•

I2C bus interface : 1 channel

•

A/D converter: 12 channels (conversion time: 10 µs)

•

Low-frequency oscillation mode: main system clock frequency = internal clock frequency

•

Low-power consumption mode: CPU can operate with a subsystem clock.

•

Supply voltage range: VDD = +2.7 to 5.5 V

•

Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current consumption

•

PD784927 is described in detail in the following User’s Manual. Be sure to read this

Part Number

PD784927, 784927YµPD784928, 784928Y

Unless otherwise specified, the

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U12255EJ2V0DS00 (2nd edition) Date Published December 1999 N CP(K) Printed in Japan

PD784927 is treated as the representative model throughout this document.

The mark shows major revised points.

1997,1999

APPLICATION FIELDS

Stationary VCR, video camera, In-TV VCR

ORDERING INFORMATION

(1)µPD784928 subseries

Part Number Package

PD784927GC-×××-8EU

PD784927GF-×××-3BA 100-pin plastic QFP (14 × 20 mm)

PD784928GC-×××-8EU

PD784928GF-×××-3BA 100-pin plastic QFP (14 × 20 mm)

PD784928Y subseries

(2)

Part Number Package

PD784927YGC-×××-8EU

PD784927YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)

PD784928YGC-×××-8EU

PD784928YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)

Note

PD784927, 784928, 784927Y, 784928Y

100-pin plastic LQFP (fine pitch) (14 × 14 mm)

Note Under development

Remark ××× indicates ROM code suffix.

PRODUCT DEVELOPMENT OF VCR-SERVO MICROCONTROLLERS

The product development of VCR-servo microcontrollers is shown below. Enclosed in a frame are subseries

names.

The Y subseries is a collection of products supporting the I

Products under mass production

Products under development

78K/IV series

78K/I series

PD784928

PD784915

PD78148

PD784928Y

C bus.

100-pin QFP. With flash memory. Expanded internal memory capacity. More powerful analog amplifier. Improved VCR functions. Increased I/O. High-current port added.

C function added (Y model only).

I 100-pin QFP.

Expanded internal memory capacity. Internal analog amplifier. Reinforced super timer. Low-power consumption mode added.

100-pin QFP Expanded internal RAM capacity. Operational amplifier, watch function, multiplier added.

PD78138

Data Sheet U12255EJ2V0DS00

80-pin QFP

FUNCTION LIST (1/2)

Part Number

Item Internal ROM capacity Internal RAM capacity Operating clock

Minimum instruction execution time

I/O port

Real-time output port

Timer/counter

Capture register

Super timer unit

VCR special circuit

General-purpose timer

PWM output

Serial interface

A/D converter

PD784927, 784928, 784927Y, 784928Y

PD784927, 784927Y

96K bytes 128K bytes 2048 bytes 3584 bytes 16 MHz (internal clock: 8 MHz)

Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz) Low power consumption mode : 32.768 kHz (subsystem clock)

250 ns (with 8 MHz internal clock)

input : 20

I/O : 54 (including 8 ports for LED direct drive)

11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation)

Timer/counter Compare register Capture register Remark

TM0 (16 bits) 3 — TM1 (16 bits) 3 1 FRC (22 bits) — 6 TM3 (16 bits) 2 1

UDC (5 bits) 1 —

EC (8 bits) 4 — For HSW signal generation

EDV (8 bits) 1 — For CFG signal division

Input signal Number of bits Measurable cycle Operating edge

CFG 22 125 ns to 524 ms ↑↓

DFG 22 125 ns to 524 ms ↑ HSW 16 1 µs to 65.5 ms ↑↓ VSYNC 22 125 ns to 524 ms ↑

CTL 16 1 µs to 65.5 ms ↑↓ TREEL 22 125 ns to 524 ms ↑↓ SREEL 22 125 ns to 524 ms ↑↓

•VSYNC separation circuit, HSYNC separation circuit

• VISS detection, wide aspect detection circuits

• Field identification circuit

• Head amplifier switch/chrominance rotation output circuit

Timer Compare register Capture register TM2 (16 bits) 1 — TM4 (16 bits) 1 (capture/compare) 1 TM5 (16 bits) 1 —

• 16-bit resolution : 3 channels (carrier frequency: 62.5 kHz)

• 8-bit resolution : 3 channels (carrier frequency: 62.5 kHz)

3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel)

• I2C bus interface: 1 channel (µPD784928Y subseries only) 8-bit resolution × 12 channels, conversion time: 10 µs

PD784928, 784928Y

Data Sheet U12255EJ2V0DS00

FUNCTION LIST (2/2)

PD784927, 784928, 784927Y, 784928Y

Part Number

Item Analog circuit

Interrupt sources

External Internal

Standby function

Watch function Buzzer output function

Supply voltage Package

Note Under development

PD784927, 784927Y

• CTL amplifier

• RECCTL driver (rewritable)

• DFG amplifier, DPG amplifier, CFG amplifier

• DPFG separation circuit (ternary separation circuit)

• Reel FG comparator (2 channels)

• CSYNC comparator

4 levels (programmable), vectored interrupt, macro service, context switching 9 (including NMI) 22 (including software interrupt) 23 (including software interrupt) HALT mode/STOP mode/low power consumption mode/low power consumption HALT mode STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/

INTP2/KEY0-KEY4 pins

0.5-second measurement, low-voltage operation (VDD = 2.7 V)

1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (Internal clock: 8 MHz)

2.048 kHz, 4.096 kHz, 32.768 kHz (Subsystem clock: 32.768 kHz) VDD = +2.7 to 5.5 V

• 100-pin plastic LQFP (fine pitch)(14 × 14 mm)

• 100-pin plastic QFP (14 × 20 mm)

Note

PD784928, 784928Y

Data Sheet U12255EJ2V0DS00

PIN CONFIGURATION (Top View)

• 100-pin plastic LQFP (fine pitch)(14 × 14 mm)

PD784927GC-×××-8EU

PD784928YGC-×××-8EU, 784928YGC-×××-8EU

P84/PWM2/SDA

P83/ROTC

P82/HASW

Note 2

P80 P57 P56 P55 P54 P53 P52 P51 P50

V P47 P46 P45 P44 P43 P42 P41 P40 P07 P06 P05

1 2 3 4 5 6 7 8 9 10 11 12

SS DD

13 14 15 16 17 18 19 20 21 22 23 24 25

Note 1

, 784928GC-×××-8EU

Note 2

P85/PWM3/SCL

P86/PTO10

P87/PTO11

P30/PTO00

P31/PTO01

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

P32/PTO02ICRESETX1X2

PD784927, 784928, 784927Y, 784928Y

Note 1

VSSXT2

XT1

VDDP33/SI2/BUSY

P34/SO2

P35/SCK2

P36/PWM1

P37/PWM0

P63/SI1

P62/SO1

P61/SCK1/BUZ

P60/STRB/CLO

P67/PWM5/CTLMON

P66/PWM4/CFGMON

80 79 78 77 76

46 47 48 49 50

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P65/HWIN/DPGMON P64/BUZ/DFGMON P103/CSYNCIN P102/REEL0IN/INTP3 P101/REEL1IN DFGIN P100/DPGIN CFGCPIN CFGAMP0 CFGIN AV

DD1

SS1

VREFC CTLOUT2 CTLOUT1 CTLIN RECCTL− RECCTL+ CTLDLY AV

SS2

P113/ANI11 P112/ANI10 P111/ANI9 P110/ANI8 P77/ANI7

DD2AVREF

P04

P03

P02

P01

P00

P23/INTP2

P20/NMI

P22/INTP1

P21/INTP0

P90/ENV

P91/KEY0

P92/KEY1

P93/KEY2

P96

P94/KEY3

P95/KEY4

Notes 1. Under development

2. Pins SCL and SDA are provided for the µPD784928Y subseries only.

Caution Directly connect the IC (Internally Connected) pins to V

Data Sheet U12255EJ2V0DS00

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

SS in the normal operation mode.

• 100-pin plastic QFP (14 × 20 mm)

PD784927GF-×××-3BA, 784928GF-×××-3BA,

PD784927YGF-×××-3BA, 784928YGF-×××-3BA

CSYNCIN/P103

REEL0IN/INTP3/P102

REEL1IN/P101

100

DFGMON/P64/BUZ

DPGMON/P65/HWIN

CFGMON/P66/PWM4

CTLMON/P67/PWM5

P60/STRB/CLO

P61/SCK1/BUZ

P62/SO1

P63/SI1 P37/PWM0 P36/PWM1

P35/SCK2

P34/SO2

P33/SI2/BUSY

XT1 XT2

RESET

P32/PTO02 P31/PTO01 P30/PTO00 P87/PTO11 P86/PTO10

Note

/P85/PWM3

SCL

Note

/P84/PWM2

SDA

P83/ROTC

P82/HASW

1 2 3 4 5 6 7 8 9 10 11 12 13

15 16

19 20

21 22 23 24 25 26 27 28 29 30

3132333435363738 39 40 41 42 43 44 45 46 47 48 49 50

DFGIN96DPGIN/P100

CFGCPIN

CFGAMPO

PD784927, 784928, 784927Y, 784928Y

DD1

CFGIN92AV

SS1

VREFC89CTLOUT2

CTLOUT1

CTLIN86RECCTL

RECCTL+

CTLDLY83AV

SS2

ANI11/P113

ANI10/P112

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

ANI9/P111 ANI8/P110 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0

REF

AV AV

DD2

P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI/P20 INTP0/P21 INTP1/P22 INTP2/23 P00 P01 P02 P03 P04 P05 P06

P80

P57

P56

P55

Note Pins SCL and SDA are provided for the

P54

P53

P52

PD784928Y subseries only.

P51

P50

P47

Caution Directly connect the IC (Internally Connected) pins to V

Data Sheet U12255EJ2V0DS00

P46

P45

P44

P43

SS.

P42

P41

P40

P07

PD784927, 784928, 784927Y, 784928Y

ANI0-ANI11 : Analog Input AVDD1, AVDD2 : Analog Power Supply AV

SS1, AVSS2 : Analog Ground

AVREF : Analog Reference Voltage BUSY : Serial Busy BUZ : Buzzer Output CFGAMPO : Capstan FG Amplifier Output CFGCPIN : Capstan FG Capacitor Input CFGIN : Analog Unit Input CFGMON : Capstan FG Monitor CLO : Clock Output CSYNCIN : Analog Unit Input CTLDLY : Control Delay Input CTLIN : CTL Amplifier Input Capacitor CTLMON : CTL Amplifier Monitor CTLOUT1, CTLOUT2 : CTL Amplifier Output DFGIN : Analog Unit Input DFGMON : DFG Monitor DPGIN : Analog Unit Input DPGMON : DPG Monitor ENV : Envelope Input HASW : Head Amplifier Switch Output HWIN : Hardware Timer External Input IC : Internally Connected INTP0-INTP3 : Interrupt From Peripherals KEY0-KEY4 : Key Return NMI : Nonmaskable Interrupt P00-P07 : Port0

P20-P23 : Port2 P30-P37 : Port3 P40-P47 : Port4 P50-P57 : Port5 P60-P67 : Port6 P70-P77 : Port7 P80, P82-P87 : Port8 P90-P96 : Port9 P100-P103 : Port10 P110-P113 : Port11 PTO00-PTO02, PTO10, PTO11 : Programmable Timer Output PWM0-PWM5 : Pulse Width Modulation Output RECCTL+, RECCTL– : RECCTL Output/PBCLT Input REEL0IN, REEL1IN : Analog Unit Input RESET : Reset ROTC : Chrominance Rotate Output SCK1, SCK2 : Serial Clock

Note

SCL SDA

Note

: Serial Clock

: Serial Data SI1, SI2 : Serial Input SO1, SO2 : Serial Output STRB : Serial Strobe V

DD : Power Supply

VREFC : Reference Amplifier Capacitor V

SS : Ground

X1, X2 : Crystal (Main System Clock) XT1, XT2 : Crystal (Subsystem Clock)

Note Pins SCL and SDA are provided for the

Data Sheet U12255EJ2V0DS00

PD784928Y subseries only.

INTERNAL BLOCK DIAGRAM

PD784927, 784928, 784927Y, 784928Y

NMI

INTP0-INTP3

PWM0-PWM5

PTO00-PTO02

PTO10, PTO11

VREFC REEL0IN REEL1IN

CSYNCIN

DFGIN DPGIN CFGIN

CFGAMPO

CFGCPIN CTLOUT1 CTLOUT2

CTLIN

RECCTL+

RECCTL

CTLDLY

DFGMON

DPGMON

CFGMON

CTLMON

DD1

, AV

DD2

SS1

, AV

REF

AN10-AN11

SI1

SO1

SCK1

SI2/BUSY

SO2

SCK2

STRB

SUPER TIMER

ANALOG UNIT

A/D CONVERTER

SS2

INTERFACE 1

INTERFACE 2

INTERRUPT

CONTROL

UNIT

SERIAL

78K/IV

16-BIT CPU CORE

(RAM: 512 bytes)

RAM

ROM

SYSTEM

CONTROL

CLOCK OUTPUT

BUZZER OUTPUT

KEY INPUT

REAL-TIME

OUTPUT PORT

PORT0 P00-P07

PORT2 P20-P23

PORT3 P30-P37

PORT4 P40-P47

PORT5 P50-P57

PORT6 P60-P67

PORT7 P70-P77

PORT8 P80, P82-P87

PORT9 P90-P96

X1 X2 XT1 XT2 RESET

CLO

BUZ

KEY0-KEY4

P00-P07

P80, P82, P83

SDA

SCL

SERIAL

INTERFACE 3

Note

Note Only the µPD784928 subseries supports I2C bus interface.

Remark Internal ROM and RAM capacities differ depending on the product.

Data Sheet U12255EJ2V0DS00

PORT10 P100-P103

PORT11 P110-P113

SYSTEM CONFIGURATION EXAMPLE

• Video camera

DFG

DPG

Drum motor M

Capstan motor M

CTL head

Loading motor M

Driver

CFG

Driver

PD784927, 784928, 784927Y, 784928Y

PD784927

DFGIN DPGIN

PWM0

CFGIN

PWM1

RECCTL+

RECCTL

PWM2

PORT

SCK1

SI1

SO1

INTP0

PORT

SCK2

SO2

BUSY

Key matrix

INTP0

Camera-

SCK

controlling

microcontroller

PD784038

PORT

Camera block

CS CLK

DATA BUSY

LCD C/D PD7225

Audio/video

signal

processing

circuit

Remote controller signal

Composite sync signal Video head switch Audio head switch Pseudo vertical sync signal

Remote controller reception signal

PC2800A

PORT CSYNCIN

PTO00 PTO01 P80

INTP2

XT1 XT2X1 X2

16 MHz 32.768 kHz

PORT

STRB

PORT

SDA

SCL

Note

+VDD

CS CLK DATA BUSY STB

SDA SCL

LCD display panel

OSD

PD6461

Mechanical block

EEPROM

Other ICs

Note Pins SCL and SDA are provided for the

Data Sheet U12255EJ2V0DS00

PD784928Y subseries only.

• Stationary VCR

Drum motor M

Capstan motor M

CTL head

Loading motor M

Reel motor

PD784927, 784928, 784927Y, 784928Y

PD784927

DFG

DFGIN DPGIN

DPG

Driver

Reel FG0

Driver

Reel FG1

CFG

PWM0

CFGIN

PWM1

RECCTL+

RECCTL

PWM2

REEL0IN

PWM3

PWM4

REEL1IN

PORT

SCK1

SI1

SO1

PORT

SCK2

SO2

PORT

CSYNCIN

PTO00 PTO01

P80

PWM5

PORT

INTP2

Note

SDA

Note

SCL

STB CLK DOUT DIN

FIP

CS CLK

DATA

Composite sync signal Video head switch Audio head switch Pseudo vertical sync signal

Remote controller reception signal

EEPROM

SDA SCL

C/D

FIP

PD16311

Key matrix

OSD PD6464A

Audio/video signal

processing circuit

Tuner

Mechanical block

PC2800A

Remote controller signal

Low frequency oscillation mode

Note Pins SCL and SDA are provided for the

XT1 XT2X1 X2

8 MHz 32.768 kHz

PD784928Y subseries only.

Data Sheet U12255EJ2V0DS00

Other ICs

SDA SCL

PD784927, 784928, 784927Y, 784928Y

CONTENTS

1. DIFFERENCE BETWEEN µPD784928 SUBSERIES AND 784928Y SUBSERIES .................... 12

2. PIN FUNCTION ............................................................................................................................... 13

2.1 Port Pins................................................................................................................................................ 13

2.2 Pins Other Than Port Pins .................................................................................................................. 14

2.3 I/O Circuits of Pins and Processing of Unused Pins...................................................................... 1 6

3. INTERNAL BLOCK FUNCTION ..................................................................................................... 19

3.1 CPU Registers ...................................................................................................................................... 19

3.1.1 General-purpose registers ......................................................................................................... 19

3.1.2 Other CPU registers................................................................................................................... 20

3.2 Memory Space ...................................................................................................................................... 2 1

3.3 Special Function Registers (SFRs) ................................................................................................... 2 4

3.4 Ports....................................................................................................................................................... 3 0

3.5 Real-Time Output Port......................................................................................................................... 31

3.6 Super Timer Unit .................................................................................................................................. 35

3.7 Serial Interface ..................................................................................................................................... 4 1

3.8 A/D Converter ....................................................................................................................................... 44

3.9 VCR Analog Circuits............................................................................................................................ 45

3.10 Watch Function .................................................................................................................................... 50

3.11 Clock Output Function ........................................................................................................................ 51

3.12 Buzzer Output Function ...................................................................................................................... 5 2

4. INTERNAL/EXTERNAL CONTROL FUNCTION ........................................................................... 53

4.1 Interrupt Function ................................................................................................................................53

4.1.1 Vectored interrupt....................................................................................................................... 56

4.1.2 Context switching ....................................................................................................................... 56

4.1.3 Macro service ............................................................................................................................. 57

4.1.4 Application example of macro service ...................................................................................... 59

4.2 Standby Function................................................................................................................................. 62

4.3 Clock Generation Circuit ..................................................................................................................... 64

4.4 Reset Function ..................................................................................................................................... 65

5. INSTRUCTION SET ........................................................................................................................ 66

6. ELECTRICAL SPECIFICATIONS .................................................................................................. 70

7. PACKAGE DRAWING .................................................................................................................... 85

8. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 87

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 88

APPENDIX B. RELATED DOCUMENTS ............................................................................................ 91

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

1. DIFFERENCE BETWEEN µPD784928 SUBSERIES AND 784928Y SUBSERIES

The µPD78F4928 and 78F4928Y are based on the µPD784927 and 784927Y and are provided with a 128K-byte

flash memory instead of a mask ROM.

Table 1-1 shows the differences between the products in the µPD784928 subseries and 784928Y subseries.

Table 1-1. Differences between

PD784928 Subseries and 784928Y Subseries

Part Number

Item Internal ROM Mask ROM Flash memory

Internal RAM 2048 bytes 3584 bytes Internal memory capacity Not provided Provided

select register (IMS) IC pin Provided Not provided VPP pin Not provided Provided Electrical characteristics Refer to the Data Sheet of each product.

PD784927,

PD784927Y

96K bytes 128K bytes

PD784928,

PD784928Y

PD78F4928,

PD78F4928Y

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

2. PIN FUNCTION

2.1 Port Pins

Pin Name I/O Shared with: Function

P00-P07 I/O Real-time 8-bit I/O port (port 0).

output port • Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors. P20 Input NMI 4-bit I/O port (port 2). P21-P23 INTP0-INTP2 • Can be connected with software pull-up resistors (P22 and P23 only). P30-P32 I/O PTO00-PTO02 8-bit I/O port (port 3). P33 SI2/BUSY • Can be set in input or output mode in 1-bit units. P34 SO2 • Can be connected with software pull-up resistors. P35 SCK2 P36, P37 PWM1, PWM0 P40-P47 I/O — 8-bit I/O port (port 4).

• Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors.

• Can directly drive LED.

P50-P57 I/O — 8-bit I/O port (port 5).

• Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors.

P60 I/O STRB/CLO 8-bit I/O port (port 6). P61 SCK1/BUZ • Can be set in input or output mode in 1-bit units. P62 SO1 • Can be connected with software pull-up resistors. P63 SI1 P64 DFGMON/BUZ P65 DPGMON/HWIN P66 CFGMON/PWM4 P67 CTLMON/PWM5 P70-P77 Input ANI0-ANI7 8-bit input port (port 7) P80 I/O Real-time Pseudo VSYNC output 7-bit I/O port (port 8). P82 output port HASW output • Can be set in input or output mode P83 ROTC output in 1-bit units. P84 PWM2/SDA P85 PWM3/SCL P86 PTO10 P87 PTO11 P90 I/O ENV 7-bit I/O port (port 9). P91-P95 KEY0-KEY4 • Can be set in input or output mode in 1-bit units. P96 — • Can be connected with software pull-up resistors. P100 Input DPGIN 4-bit input port (port 10). P101 REEL1IN P102 REEL0IN/INTP3 P103 CSYNCIN P110-P113 Input ANI8-ANI11 4-bit input port (port 11).

Note

• Can be connected with software pull-up resistors.

Note Pins SCL and SDA are provided for the µPD784928Y subseries only.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

2.2 Pins Other Than Port Pins (1/2)

Pin Name I/O Shared with: Function REEL0IN Input P102/INTP3 Reel FG input REEL1IN P101 DFGIN — Drum FG, PFG input (ternary) DPGIN P100 Drum PG input CFGIN — Capstan FG input CSYNCIN P103 Composite SYNC input CFGCPIN — CFG comparator input CFGAMPO Output — CFG amplifier output PTO00 Output P30 Programmable timer output of super timer unit PTO01 P31 PTO02 P32 PTO10 P86 PTO11 P87 PWM0 Output P37 PWM output of super timer unit PWM1 P36 PWM2 P84/SDA PWM3 P85/SCL PWM4 P66/CFGMON PWM5 P67/CTLMON HASW Output P82 Head amplifier switch signal output ROTC Output P83 Chrominance rotation signal output ENV Input P90 Envelope signal input SI1 Input P63 Serial data input (serial interface channel 1) SO1 Output P62 Serial data output (serial interface channel 1) SCK1 I/O P61/BUZ Serial clock I/O (serial interface channel 1) SI2 Input P33/BUSY Serial data input (serial interface channel 2) SO2 Output P34 Serial data output (serial interface channel 2) SCK2 I/O P35 Serial clock I/O (serial interface channel 2) BUSY Input P33/SI2 Serial busy signal input (serial interface channel 2) STRB Output P60/CLO Serial strobe signal output (serial interface channel 2) SDA I/O P84/PWM2 I2C bus data I/O SCL I/O P85/PWM3 I2C bus clock I/O ANI0-ANI7 Analog input P70-P77 Analog signal input of A/D converter ANI8-ANI11 P110-P113 CTLIN — — CTL amplifier input capacitor connection CTLOUT1 Output — CTL amplifier output CTLOUT2 I/O — Logic signal input/CTL amplifier output RECCTL+, RECCTL– I/O — RECCTL signal output/PBCTL signal input CTLDLY — — External time constant connection (for RECCTL rewriting)

Note

Note Pins SCL and SDA are provided for the µPD784928Y subseries only.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

2.2 Pins Other Than Port Pins (2/2)

Pin Name I/O Shared with: Function VREFC — — VREF amplifier AC connection DFGMON Output P64/BUZ Drum FG signal output DPGMON P65/HWIN Drum PG signal output CFGMON P66/PWM4 CFG signal output CTLMON P67/PWM5 CTL signal output NMI Input P20 Non-maskable interrupt request input INTP0-INTP2 Input P21-P23 External interrupt request input INTP3 Input P102/REEL0IN KEY0-KEY4 Input P91-P95 Key input signal input CLO Output P60/STRB Clock output BUZ Output P61/SCK1 Buzzer output

P64/DFGMON HWIN Input P65/DPGMON External input of hardware watch counter RESET Input — Reset input X1 Input — Crystal connection for main system clock oscillation X2 — XT1 Input — Crystal connection for subsystem clock oscillation. XT2 — Crystal connection for watch clock oscillation AVDD1 — — Positive power supply to analog amplifier circuit AVDD2 — — Positive power supply to A/D converter and analog circuits input buffer AVSS1 — — GND of analog amplifier circuit AVSS2 — — GND of A/D converter and analog circuits input buffer AVREF — — Reference voltage input to A/D converter VDD — — Positive power supply to digital circuits VSS — — GND of digital circuits IC — — Internally connected. Directly connect this pin to VSS.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

2.3 I/O Circuits of Pins and Processing of Unused Pins

Table 2-1 shows the types of the I/O circuits of the respective pins and processing of the unused pins. Figure

2-1 shows the circuits of the respective types.

Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (1/2)

Pin I/O Circuit Type I/O Recommended Connection of Unused Pins

P00-P07 5-A I/O Input: Connect to VDD.

Output: Leave unconnected. P20/NMI 2 Input Connect to VDD. P21/INTP0 Connect to VDD or VSS. P22/INTP1, P23/INTP2 2-A Connect to VDD. P30/PTO00-P32/PTO02 5-A I/O Input: Connect to VDD. P33/SI2/BUSY 8-A Output: Leave unconnected. P34/SO2 5-A P35/SCK2 8-A P36/PWM1, P37/PWM0 5-A P40-P47 P50-P57 P60/STRB/CLO P61/SCK1/BUZ 8-A P62/SO1 5-A P63/SI1 8-A P64/DFGMON/BUZ 5-A P65/HWIN/DPGMON 8-A P66/PWM4/CFGMON 5-A P67/PWM5/CTLMON P70/ANI0-P77/ANI7 9 Input Connect to VSS. P80 5-A I/O Input: Connect to VDD. P82/HASW Output: Leave unconnected. P83/ROTC P84/PWM2/SDA P85/PWM3/SCL P86/PTO10 5-A P87/PTO11 P90/ENV P91/KEY0-P95/KEY4 8-A P96 5-A

Note

10-A

Note Pins SCL and SDA are provided for the µPD784928Y subseries only.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (2/2)

Pin I/O Circuit Type I/O Recommended Connection of Unused Pins

P100/DPGIN — Input When ENDRUM = 0 or ENDRUM = 1 and

SELPGSEPA = 0: Connect to VSS. P101/REEL1IN When ENREEL = 0: Connect to VSS. P102/REEL0IN/INTP3 P103/CSYNCIN When ENCSYN = 0: Connect to VSS. P110/ANI8-P113/ANI11 9 Input Connect to VSS. RECCTL+, RECCTL– — I/O When ENCTL = 0 and ENREC = 0: Connect to VSS. DFGIN — Input When ENDRUM = 0: Connect to VSS. CFGIN, CFGCPIN When ENCAP = 0: Connect to VSS. CTLOUT1 — Output Leave unconnected. CTLOUT2 — I/O When ENCTL = 0 and ENCOMP = 0: Connect to VSS.

When ENCTL = 1: Leave unconnected. CFGAMPO — Output Leave unconnected. CTLIN — — When ENCTL = 0: Leave unconnected. VREFC CTLDLY Leave unconnected. AVDD1, AVDD2 — — Connect to VDD. AVREF, AVSS1, AVSS2 Connect to VSS. RESET 2 — — XT1 — — Connect to VSS. XT2 Leave unconnected.

When ENCTL = 0 and ENCAP = 0 and ENCOMP = 0: Leave unconnected.

IC Directly connect to VSS.

Remark ENCTL : bit 1 of amplifier control register (AMPC)

ENREC : bit 7 of amplifier mode register 0 (AMPM0) ENDRUM : bit 2 of amplifier control register (AMPC) SELPGSEPA: bit 2 of amplifier mode register 0 (AMPM0) ENCAP : bit 3 of amplifier control register (AMPC) ENCSYN : bit 5 of amplifier control register (AMPC) ENREEL : bit 6 of amplifier control register (AMPC) ENCOMP : bit 4 of amplifier control register (AMPC)

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Figure 2-1. I/O Circuits of Respective Pins

Type 2

Schmitt trigger input with hysteresis characteristics

Type 2-A

P-ch

Pull-up enable

Schmitt trigger input with hysteresis characteristics

Type 5-A

Pull-up

enable

Data

Output

disable

P-ch

N-ch

P-ch

IN/ OUT

Type 8-A

Pull-up

enable

Data

Output

disable

Type 9

Type 10-A

Pull-up Enable

P-ch N-ch

P-ch

N-ch

Comparator

REF

(Threshold voltage)

Input enable

P-ch

IN/ OUT

P-ch

Input

enable

Data

Open drain

Output disable

P-ch

IN/OUT

N-ch

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3. INTERNAL BLOCK FUNCTION

3.1 CPU Registers

3.1.1 General-purpose registers

PD784927 has eight banks of general-purpose registers. One bank consists of sixteen 8-bit general-purpose

The registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. Four of the 16-bit general-purpose registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register.

These eight banks of general-purpose registers can be selected by software or context switching function.

The general-purpose registers, except for the address expansion registers V, U, T, and W, are mapped to the internal RAM.

Figure 3-1. Configuration of General-Purpose Register

A (R1) X (R0)

AX (RP0)

B (R3) C (R2)

BC (RP1)

R5 R4

RP2

R7 R6

RP3

R9 R8V

VP (RP4)

VVP (RG4)

R11 R10U

UP (RP5)

UUP (RG5)

D (R13) E (R12)T

DE (RP6)

TDE (RG6)

H (R15) L (R14)W

HL (RP7)

WHL (RG7)

( ): absolute name

8 banks

Caution Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the RSS bit is planned to be deleted from the future models in the 78K/IV Series.

Data Sheet U12255EJ2V0DS00

3.1.2 Other CPU registers

(1) Program counter

The program counter of the updated as the program is executed.

(2) Program status word

This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the program is executed.

PD784927, 784928, 784927Y, 784928Y

PD784927 is 20 bits wide. The value of the program counter is automatically

19 0

12 11 10 9 8

PSWH UF15RBS214RBS113RBS0

PSW

PSWL S7Z

RSS

5AC4IE3

Note

P/V201CY

Note The RSS flag is provided to maintain compatibility with the microcomputers in the 78K/III Series.

Always clear this flag to 0 except when the software of the 78K/III Series is used.

(3) Stack pointer

This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the high-order 4 bits.

23 0

000200SP

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.2 Memory Space

A memory space of 1M bytes can be accessed. The mapping of the internal data area (special function registers and internal RAM) can be selected by using the LOCATION instruction. The LOCATION instruction must be always executed after reset has been cleared, and cannot be used more than once.

(1) When LOCATION 0H instruction is executed

Part Number Internal Data Area Internal ROM Area

PD784927, 784927Y 0F700H-0FFFFH 00000H-0F6FFH

10000H-17FFFH

PD784928, 784928Y 0F100H-0FFFFH 00000H-0F0FFH

10000H-1FFFFH

Remark The area of the internal ROM overlapping the internal data area cannot be used when the

LOCATION 0 instruction is executed.

Part Number Unusable Area

PD784927, 784927Y 0F700H-0FFFFH (2304 bytes)

PD784928, 784928Y 0F100H-0FFFFH (3840 bytes)

(2) When LOCATION 0FH instruction is executed

Part Number Internal Data Area Internal ROM Area

PD784927, 784927Y FF700H-FFFFFH 00000H-17FFFH

PD784928, 784928Y FF100H-FFFFFH 00000H-1FFFFH

Data Sheet U12255EJ2V0DS00

(256 bytes)

Special function registers (SFRs)

Internal ROM

(63232

bytes)

Internal RAM

(2048 bytes)

Cannot be used

General-purpose registers

(128 bytes)

Macro service control

word area (54 bytes)

Data area (512 bytes)

Program/data area

(1536 bytes)

Note 2

CALLF entry area

(2K bytes)

Program/data area

Note 3

CALLT table area

(64 bytes)

Vector table area

(64 bytes)

Internal RAM

(2048 bytes)

Cannot be used

Internal ROM

(96K bytes)

Note 4

When LOCATION 0H instruction is executed

Note 1

When LOCATION 0FH instruction is executed

Internal ROM

(32768 bytes)

FFFFFH

18000H

17FFFH

10000H

0FFFFH

0FFDFH

0FFD0H

0FF00H

0FEFFH

0F700H

0F6FFH

00000H

0FEFFH

0FE80H

0FE7FH

0FE3BH

0FE06H

0FD00H

0FCFFH

0F700H

17FFFH

10000H

0F6FFH

01000H

00800H

007FFH

00080H

0007FH

00040H

0003FH

00000H 00000H

17FFFH

18000H

FFFFFH

FFFDFH

FFFD0H

FFF00H

FFEFFH

FF6FFH

FF700H

FFEFFH

FFE80H

FFE7FH

FFE3BH

FFE06H

FFD00H

FFCFFH

FF700H

17FFFH

Special function registers (SFRs)

(256 bytes)

Note 4

Note 1

00FFFH

PD784927, 784928, 784927Y, 784928Y

PD784927, 784927Y

Figure 3-2. Memory Map of

2. The 2304 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. When LOCATION 0H instruction is executed: 96000 bytes, when LOCATION 0FH instruction is executed: 98304 bytes

4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.

Notes 1. Accessed in external memory expansion mode

Data Sheet U12255EJ2V0DS00

(256 bytes)

Special function registers (SFRs)

Internal ROM

(61696

bytes)

Internal RAM

(3584 bytes)

Cannot be used

General-purpose registers

(128 bytes)

Macro service control

word area (54 bytes)

Data area (512 bytes)

Program/data area

(3072 bytes)

Note 2

CALLF entry area

(2K bytes)

Program/data area

Note 3

CALLT table area

(64 bytes)

Vector table area

(64 bytes)

Internal RAM

(3584 bytes)

Cannot be used

Internal ROM

(128K bytes)

Note 4

When LOCATION 0H instruction is executed

Note 1

When LOCATION 0FH instruction is executed

Internal ROM

(65536 bytes)

FFFFFH

20000H

1FFFFH

10000H

0FFFFH

0FFDFH

0FFD0H

0FF00H

0FEFFH

0F100H

0F0FFH

00000H

0FEFFH

0FE80H

0FE7FH

0FE3BH

0FE06H

0FD00H

0FCFFH

0F100H

1FFFFH

10000H

0F0FFH

01000H

00800H

007FFH

00080H

0007FH

00040H

0003FH

00000H 00000H

1FFFFH

20000H

FFFFFH

FFFDFH

FFFD0H

FFF00H

FFEFFH

FF0FFH

FF100H

FFEFFH

FFE80H

FFE7FH

FFE3BH

FFE06H

FFD00H

FFCFFH

FF100H

1FFFFH

Special function registers (SFRs)

(256 bytes)

Note 4

Note 1

00FFFH

PD784927, 784928, 784927Y, 784928Y

PD784928, 784928Y

Figure 3-3. Memory Map of

2. The 3840 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. When LOCATION 0H instruction is executed: 127232 bytes, when LOCATION 0FH instruction is executed: 131072 bytes

4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.

Notes 1. Accessed in external memory expansion mode

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.3 Special Function Registers (SFRs)

Special function registers are assigned special functions and mapped to a 256-byte space of addresses FF00H through FFFFH. These registers include mode registers and control registers that control the internal peripheral hardware units.

Caution Do not access an address to which no SFR is assigned. If such an address is accessed by

mistake, the

Table 3-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

• Symbol .................................... Abbreviation of an SFR. This abbreviation is reserved for NEC’s assembler

• R/ W ......................................... Indicates whether the SFR in question can be read or written.

PD784927 may be deadlocked. This deadlock can be cleared only by reset input.

(RA78K4). With a C compiler (CC78K4), the abbreviation can be used as sfr variable by the #pragma sfr instruction.

R/W : Read/write R : Read only W : Write only

• Bit length................................. Indicates the bit length (word length) of the SFR.

• Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that

can be manipulated in 16-bit units can be used as the operand sfrp of an instruction. Specify an even address to manipulate this SFR. An SFR that can be manipulated in 1-bit units can be used for a bit manipulation instruction.

• After clearing reset ................. Indicates the status of each register immediately after clearing reset.

Caution The addresses shown in Table 3-1 are used when the LOCATION 0H instruction is executed. Add

“F0000H” to the address values shown in the table when the LOCATION 0FH instruction is executed.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (1/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FF00H Port 0 P0 R/W 8 — Undefined FF02H Port 2 P2 R 8 — FF03H Port 3 P3 R/W 8 — FF04H Port 4 P4 8 — FF05H Port 5 P5 8 — FF06H Port 6 P6 8 — FF07H Port 7 P7 R 8 — FF08H Port 8 P8 R/W 8 — FF09H Port 9 P9 8 —

FF0AH Port 10 P10 R 8 — FF0BH Port 11 P11 8 — FF0EH Port 0 buffer register L P0L R/W 8 —

FF0FH Port 0 buffer register H P0H 8 — FF10H Timer 0 compare register 0 CR00 16 — — Cleared to 0 FF11H Event counter compare register 0 ECC0 W 8 — — FF12H Timer 0 compare register 1 CR01 R/W 16 — — FF13H Event counter compare register 1 ECC1 W 8 — — FF14H Timer 0 compare register 2 CR02 R/W 16 — — FF15H Event counter compare register 2 ECC2 W 8 — — FF16H Timer 1 compare register 0 CR10 R/W 16 — — FF17H Event counter compare register 3 ECC3 W 8 — — FF18H Timer 1 compare register 1 CR11 R/W 16 — —

FF1AH Timer 1 compare register 2 CR12 R 16 — — FF1CH Timer 1 compare register 3 CR13 R/W 16 — — FF1EH Timer 2 compare register 0 CR20 16 — —

FF20H Port 0 mode register PM0 8 — FFH FF23H Port 3 mode register PM3 8 — FF24H Port 4 mode register PM4 8 — FF25H Port 5 mode register PM5 8 — FF26H Port 6 mode register PM6 8 — FF28H Port 8 mode register PM8 8 — FDH FF29H Port 9 mode register PM9 8 — 7FH

FF2EH Real-time output port 0 control register RTPC 8 — 00H

FF30H Timer counter 0 TM0 R 16 — — Cleared to 0 FF31H Event counter EC R/W 8 — — FF32H Timer counter 1 TM1 R 16 — — FF34H Free running counter (bits 0-15) FRCL 16 — — 0000H FF35H Free running counter (bits 16-21) FRCH 8 — — 00H FF36H Timer counter 2 TM2 16 — — Cleared to 0

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (2/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FF38H Timer control register 0 TMC0 R/W 8 — 00H FF39H Timer control register 1 TMC1 8 — FF3AH Timer control register 2 TMC2 8 — FF3BH Timer control register 3 TMC3 8 —00×00000 FF3CH Timer counter 3 TM3 R 16 — — Cleared to 0 FF3DH Timer control register 4 TMC4 R/W 8 — ××000000 FF3EH Timer counter 4 TM4 R 16 — — Cleared to 0 FF43H Port 3 mode control register PMC3 R/W 8 — 00H FF48H Port 8 mode control register PMC8 8 — FF4BH Control mode select register CMS 8 — FF4DH Trigger source select register 0 TRGS0 8 — FF4EH Pull-up resistor option register L PUOL 8 — FF4FH Pull-up resistor option register H PUOH 8 — FF50H Input control register ICR 8 — 10H FF51H Up/down counter count register UDC 8 — — Undefined FF52H Event divider counter EDV R 8 — — Cleared to 0 FF53H Capture mode register CPTM R/W 8 — 00H FF54H Timer counter 5 TM5 R 16 — — Cleared to 0 FF56H Timer 3 capture register 0 CPT30 16 — — FF58H Timer 0 output mode register TOM0 W 8 — — ××000000 FF59H Timer 0 output control register TOC0 8 — — 00H

ADML

Note 1

R/W 8 — — 80H

Note 2

8 —

FF5AH Timer 1 output mode register TOM1 FF5BH Timer 1 output control register TOC1 W 8 — — 00H FF5CH Timer 3 compare register 0 CR30 R/W 16 — — Cleared to 0 FF5EH Timer 3 compare register 1 CR31 16 — — FF60H Port 8 buffer register L P8L 8 — 000×0×0× FF63H Up/down counter compare register UDCC W 8 — — Undefined FF65H Trigger source select register 1 TRGS1 R/W 8 — 00H FF66H Port 6 mode control register PMC6 8 — FF68H A/D converter mode register ADM 16 — — 0000H

FF6AH A/D conversion result register ADCR R 8 — — Undefined FF6CH Hardware watch counter 0 HW0 R/W 16 — — Not affected FF6EH Hardware watch counter 1 HW1 R 16 — — by reset FF6FH Watch mode register WM R/W 8 —00××0×00 FF70H PWM control register 0 PWMC0 8 — 05H

Notes 1. When the TOM1 is read, the write sequence of the REC driver is read (bits 0 and 1).

2. ADML is the low-order 8 bits of ADM and can be manipulated in 1- or 8-bit units.

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (3/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FF71H PWM control register 1 PWMC1 R/W 8 — 15H FF72H PWM0 modulo register PWM0 16 — — 0000H FF73H PWM2 modulo register PWM2 8 — — 00H FF74H PWM1 modulo register PWM1 16 — — 0000H FF75H PWM3 modulo register PWM3 8 — — 00H FF76H PWM5 modulo register PWM5 16 — — 0000H FF77H PWM4 modulo register PWM4 8 — — 00H FF78H Event divider control register EDVC W 8 — — Cleared to 0 FF79H Clock output mode register CLOM R/W 8 — 00H

FF7AH Timer 4 capture/compare register 0 CR40 16 — — Cleared to 0 FF7BH Clock control register CC 8 — 00H FF7CH Timer 4 capture register 1 CR41 R 16 — — Cleared to 0 FF7DH Capture/compare control register CRC W 8 — — 00H FF7EH Timer 5 compare register CR50 R/W 16 — — Cleared to 0

FF80H I2C control register IICC 8 — 00H FF82H I2C clock select register IICCL 8 — FF84H Serial mode register 1 CSIM1 8 — FF85H Serial shift register 1 SIO1 8 — — Undefined FF86H Slave address register SVA 8 — 00H FF88H Serial mode register 2 CSIM2 8 — FF89H Serial shift register 2 SIO2 8 — — Undefined

FF8AH Serial control register 2 CSIC2 8 — — 00H

Note

IICS R 8 —

IIC R/W 8 —

FF8CH I2C bus status register FF8EH I2C bus shift register

FF90H Amplifier mode register 2 AMPM2 8 —

FF91H Head amplifier switch output control register HAPC 8 — FF94H Amplifier control register AMPC 8 — FF95H Amplifier mode register 0 AMPM0 8 — FF96H Amplifier mode register 1 AMPM1 8 — FF97H Gain control register CTLM 8 — FF98H VISS detection circuit shift register 0 VSFT0 16 — — 0000H FF99H

FF9AH VISS detection circuit shift register 1 VSFT1 16 — — FF9BH FFA0H External interrupt mode register INTM0 8 — 000000×0 FFA1H External capture mode register 1 INTM1 8 — 00H FFA2H External capture mode register 2 INTM2 8 — FFA3H VISS detection circuit control register VDC 8 —

Note These registers are provided for the µPD784928Y subseries only.

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (4/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FFA4H VISS detection circuit up/down counter register VUDC R/W 8 — — 00H FFA5H VUDC value setting register VUDST 8 — — FFA6H Key interrupt control register KEYC 8 — 70H FFA7H VISS pulse pattern setting register VPS 8 — — 00H FFA8H In-service priority register ISPR R 8 — FFAAH Interrupt mode control register IMC R/W 8 — 80H FFACH Interrupt mask flag register MK0L FFADH MK0H 8 FFAEH MK1L FFAFH MK1H 8 FFB0H FRC capture register 0L CPT0L R 16 — — Cleared to 0 FFB1H FRC capture register 0H CPT0H 8 — — FFB2H FRC capture register 1L CPT1L 16 — — FFB3H FRC capture register 1H CPT1H 8 — — FFB4H FRC capture register 2L CPT2L 16 — — FFB5H FRC capture register 2H CPT2H 8 — — FFB6H FRC capture register 3L CPT3L 16 — — FFB7H FRC capture register 3H CPT3H 8 — — FFB8H FRC capture register 4L CPT4L 16 — — FFB9H FRC capture register 4H CPT4H 8 — — FFBAH FRC capture register 5L CPT5L 16 — — FFBBH FRC capture register 5H CPT5H 8 — — FFBDH VSYNC separation circuit control register VSC R/W 8 — 00H FFBEH FFBFH VSYNC separation circuit compare register VSCMP 8 — — FFH FFC0H Standby control register STBC 8 — — 0011×000 FFC4H Execution speed select register MM W 8 — — 20H FFCEH CPU clock status register PCS R 8 — 00H FFCFH FFE0H Interrupt control register (INTP0) PIC0 R/W 8 — 43H FFE1H Interrupt control register (INTCPT3) CPTIC3 8 — FFE2H Interrupt control register (INTCPT2) CPTIC2 8 — FFE3H Interrupt control register (INTCR12) CRIC12 8 — FFE4H Interrupt control register (INTCR00) CRIC00 8 — FFE5H Interrupt control register (INTCLR1) CLRIC1 8 — FFE6H Interrupt control register (INTCR10) CRIC10 8 —

SYNC

separation circuit up/down counter register

Oscillation stabilization time specification register

MK0

MK1

VSUDC 8 — —

OSTS W 8 — —

8 FFH

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (5/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FFE7H Interrupt control register (INTCR01) CRIC01 R/W 8 — 43H FFE8H Interrupt control register (INTCR02) CRIC02 8 — FFE9H Interrupt control register (INTCR11) CRIC11 8 — FFEAH Interrupt control register (INTCPT1) CPTIC1 8 — FFEBH Interrupt control register (INTCR20) CRIC20 8 — FFECH Interrupt control register (INTIIC) FFEDH Interrupt control register (INTTB) TBIC 8 — FFEEH Interrupt control register (INTAD) ADIC 8 — FFEFH Interrupt control register (INTP2)

Interrupt control register (INTCR40) FFF0H Interrupt control register (INTUDC) UDCIC 8 — FFF1H Interrupt control register (INTCR30) CRIC30 8 — FFF2H Interrupt control register (INTCR50) CRIC50 8 — FFF3H Interrupt control register (INTCR13) CRIC13 8 — FFF4H Interrupt control register (INTCSI1) CSIIC1 8 — FFF5H Interrupt control register (INTW) WIC 8 — ×1000011 FFF6H Interrupt control register (INTVISS) VISIC 8 — 43H FFF7H Interrupt control register (INTP1) PIC1 8 — FFF8H Interrupt control register (INTP3) PIC3 8 —

FFFAH Interrupt control register (INTCSI2) CSIIC2 8 —

Note 1

Note 2

IICIC 8 —

PIC2 8 —

CRIC40

Notes 1.µPD784928Y subseries only.

2. PIC2 and CRIC40 are at the same address (register).

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.4 Ports

The µPD784927 is provided with the ports shown in Figure 3-3. Table 3-2 shows the function of each port.

Figure 3-4. Port Configuration

Port 0

Port 2

Port 3

Port 4

Port 5

P00

P07

P20

P23 P30

P37

P40

P47 P50

P57

P60

P67

P70-P77

P80 P82

P87

P90

P96

P100 P103

P110 P113

Port 6

Port 7

Port 8

Port 9

Port 10

Port 11

Table 3-2. Port Function

Name Pin Name Function Specification of Pull-up Resistor Port 0 P00-P07 Can be set in input or output mode in Pull-up resistors are connected to all

1-bit units. pins in input mode.

Port 2 P20-P23 Input port Pull-up resistors are connected to pins

P22 and P23.

Port 3 P30-P37 Can be set in input or output mode in Pull-up resistors are connected to all pins

1-bit units. in input mode.

Port 4 P40-P47 Can be set in input or output mode in

1-bit units.

Can directly drive LED. Port 5 P50-P57 Can be set in input or output mode in Port 6 P60-P67 1-bit units. Port 7 P70-P77 Input port Pull-up resistor is not provided. Port 8 P80, P82-P87 Can be set in input or output mode in Pull-up resistors are connected to all pins Port 9 P90-P96 1-bit units. in input mode.

Port 10 P100-P103 Input port Pull-up resistor is not provided. Port 11 P110-P113

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.5 Real-Time Output Port

A real-time output port consists of a port output latch and a buffer register (refer to Figure 3-5).

The function to transfer the data prepared in advance in the buffer register to the output latch when a trigger such as a timer interrupt occurs, and output the data to an external device is called a real-time output function. A port used in this way is called a real-time output port (RTP).

Table 3-3 shows the real-time output ports of the

PD784927.

Table 3-4 shows the trigger sources of RTPs.

Figure 3-5. Configuration of RTP

Buffer register

Output trigger

Port output latch

Port

Table 3-3. Bit Configuration of RTP

RTP Shared with: Number of Bits of Number of Bits That Can Remark

Real-Time Output Data Be Specified as RTP

RTP0 Port 0 4 bits × 2 channels or 4-bit units —

8 bits × 1 channel

RTP8 Port 8 1 bit × 1 channel and 1-bit units Pseudo VSYNC output: 1 channel (RTP80)

2 bits × 1 channel Head amplifier switch: 1 channel (RTP82)

Chrominance rotation signal output: 1 channel (RTP83)

Table 3-4. Trigger Sources of RTP

Trigger Source INTCR00 INTCR01 INTCR02 INTCR13 INTCR50 INTP0 Remark

RTP RTP0 High-order 4 bits

Low-order 4 bits All 8 bits

RTP8 Bit 0 Note 1

Bits 2 and 3 Note 2

Notes 1. Select one of the four trigger sources.

2. When the real-time output port mode is set by the port mode control register 8 (PMC8), the HASW and

ROT-C signals that are set by the head amplifier switch output control register (HAPC) are directly output. The HASW and ROT-C signals are synchronized with HSW output (TM0-CR00 coincidence signal). However, the set signal is output immediately when the HAPC register is rewritten.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Figures 3-6 and 3-7 show the block diagrams of RTP0 and RTP8. Figure 3-8 shows the types of RTP output trigger

sources.

Figure 3-6. Block Diagram of RTP0

Internal bus

8 4 4

Real-time output port 0 control register (RTPC)

INTP0 INTCR01 INTCR02

Output trigger

Control circuit

Remark INTCR01: TM0-CR01 coincidence signal

INTCR02: TM0-CR02 coincidence signal

Figure 3-7. Block Diagram of RTP8

Head amplifier output control register (HAPC)

SEL

ROTC

ENV

HASW

PB MOD2PBMOD1PBMOD0

Buffer register

P0H P0L

Output latch (P0)

P07 P00

Internal bus

Port 8 buffer register L (P8L)

P8L4

SEL

P8L20P8L0

MD80

TM0-CR00

coincidence signal

PMC80

0 PMC82 PMC83

PMC8

TRG

P80

HASW, ROT-C control circuit

Output latch (P8)

HSYNC

superimposition

circuit

P83P82 P80

Data Sheet U12255EJ2V0DS00

Pseudo V

SYNC

control circuit

output

INTP0

PD784927, 784928, 784927Y, 784928Y

Figure 3-8. Types of RTP Output Trigger Sources

Real-time output port 0 control register (RTPC)

Capture

TM0

CR00

CR01

CR02

TM1

CR10

CR11

CR12

CR13

TM5

Interrupt and timer output

Interrupt

Selector

Trigger source select register 0 (TRGS0)

Trigger of P0H Trigger of P0L

Trigger of P82 and P83

Trigger of P80

CR50

Interrupt

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

RTP80 can output low-level, high-level, and high-impedance values real-time. Because RTP80 can superimpose a horizontal sync signal, it can be used to create pseudo vertical sync signal.

When RTP80 is set in the pseudo V

SYNC output mode, it repeatedly outputs a specific pattern when an output trigger

occurs.

Figure 3-9 shows the operation timing of RTP80.

Figure 3-9. Example of Operation Timing of RTP80

High impedance

P80

Trigger signal

High impedance

P80

Trigger signal

High level

Low level

High level

Low level

(a) When H

SYNC signal is superimposed

(b) Pseudo VSYNC output mode

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.6 Super Timer Unit

The µPD784927 is provided with a super timer unit that consists of the timers, and VCR special circuits such as

a VISS detection circuit and a V

SYNC separation circuit, etc., shown in Table 3-5.

Table 3-5. Configuration of Super Timer Unit

Unit Name Timer/Counter Resolution

Timer 0 TM0 1 µs 65.5 ms CR00 Controls delay of video head switching signal

(16-bit timer) CR01 Controls delay of audio head switching signal

EC — — ECC0, ECC1, Creates internal head switching signal

(8-bit counter) ECC2, ECC3 Free FRC 125 ns 524 ms CPT0 Detects reference phase (to control drum phase) running (22-bit counter) CPT1 Detects phase of drum motor (to control drum counter phase)

Timer 1 TM1 1 µs 65.5 ms CR10 Playback: Creates internal reference signal

(16-bit timer) Recording: Buffer oscillator in case VSYNC is

TM3 1 µs or 65.5 ms or CR30, CR31 Controls duty detection timing of PBCTL signal

(16-bit timer) 1.1 µs 71.5 ms CPT30 Measures cycle of PBCTL signal

EDV — — EDVC Divides CFG signal frequency

(8-bit counter) Timer 2 TM2 1 µs 65.5 ms CR20 Can be used as interval timer (to control system)

(16-bit timer) Timer 4 TM4 2 µs 131 ms CR40 Detects duty of remote controller signal (to decode

(16-bit timer) remote controller signal)

Timer 5 TM5 2 µs 131 ms CR50 Can be used as interval timer (to control system)

(16-bit timer) Up/down UDC — — UDCC Creates linear tape counter counter (5-bit counter) PWM — — — PWM0, PWM1, 16-bit resolution (carrier frequency: 62.5 kHz) output unit PWM5

Maximum

Count Time

CR02 Controls pseudo VSYNC output timing

CPT2 Detects speed of drum motor (to control drum

speed)

CPT3 Detects speed of capstan motor (to control speed

of capstan motor)

CPT4, CPT5 Detects remaining tape for reel FG

missing CR11 Controls RECCTL output timing CR12 Detects phase of capstan motor (to control capstan

phase)

CR13 Controls VSYNC mask as noise preventive measures

CR41 Measures cycle of remote controller signal (to de

code remote controller signal)

PWM2, PWM3, 8-bit resolution (carrier frequency: 62.5 kHz) PWM4

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(1) Timer 0 unit

Timer 0 unit creates head switching signal and pseudo VSYNC output timing from the PG and FG signals of the drum motor. This unit consists of an event counter (EC: 8 bits), compare registers (ECC0 through ECC3), a timer (TM0: 16 bits), and compare registers (CR00 through CR02). A signal indicating coincidence between the value of timer 0 and the value of a compare register can be used as the output trigger of the real-time output port.

(2) Free running counter unit

The free running counter unit detects the speed and phase of the drum motor, and the speed and reel speed of the capstan motor. This unit consists of a free running counter (FRC), capture registers (CPT0 through CPT5), a V circuit, and a HSYNC separation circuit.

(3) Timer 1 unit

Timer 1 unit is a reference timer unit synchronized with the frame cycle and creates the RECCTL signal, detects the phase of the capstan motor, and detects the duty factor of the PBCTL signal. This unit consists of the following three groups:

SYNC separation

• Timer 1 (TM1), compare registers (CR10, CR11, and CR13), and capture register (CR12)

• Timer 3 (TM3), compare registers (CR30 and CR31), and capture register (CPT30)

• Event divider counter (EDV) and compare register (EDVC)

The TM1-CR13 coincidence signal can be used for automatic unmasking of V the real-time output port.

SYNC or as the output trigger of

Data Sheet U12255EJ2V0DS00

PTO00

PTO01

PTO02

PD784927, 784928, 784927Y, 784928Y

PTO10

PTO11

To PBCTL signal

input block

INTCR00

INTCR01

INTCR02

RTP

RTP, A/D

Output control circuit

Selector

SelectorSelector

Clear

TM0

Mask

Figure 3-10. Block Diagram of Super Timer Unit (TM0, FRC, TM1)

Selector

Divider

Writes

00H to EC

Output control circuit

(Superimposition) (Superimposition)

ECC2

ECC1

separation

SYNC

F/F

ECC0

CR00

CR01

Selector

Clear

Selector

CR02

F/F

ECC3

To P80

circuit

separation

SYNC

INTCLR1

FRC

Selector

circuit

Selector

Analog circuit

INTCPT1

CPT0

CPT1

Capture

Selector

Mask

INTCPT2

INTCPT3

CPT2

CPT3

Capture

Selector

INTP3

CPT4

CPT5

Capture

SelectorSelector

INTCR10

Output control circuit

Selector

Clear

TM1

Selector

EDV

Clear

EDVC

INTCR11

INTCR12

INTCR13

INTCR30

Output control circuit

CR10

CR11

CR12

CR13

CR30

CR31

Selector

FFLVL

CTL

CPT30

Capture

Clear

TM3

Selector

F/F

DPGIN

DFGIN

CSYNCIN

Data Sheet U12255EJ2V0DS00

REEL0IN

REEL1IN

CFGIN

PTO10

PBCTL

PTO11

PD784927, 784928, 784927Y, 784928Y

(4) Timer 2 unit

Timer 2 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM2) and a compare register (CR20). The timer is cleared when the TM2-CR20 coincidence signal occurs, and at the same time, an interrupt request is generated.

Figure 3-11. Block Diagram of Timer 2 Unit

Clear

TM2

CR20

INTCR20

(5) Timer 4 unit

Timer 4 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM4), a capture/compare register (CR40), and a capture register (CR41). The value of the timer is captured to CR40/CR41 when the INTP2 signal is input. This timer can be used to decode a remote controller signal.

Figure 3-12. Block Diagram of Timer 4 Unit

Mask

Clear

TM4

INTP2

Selector

CR40 CR41

INTCR40

(6) Timer 5 unit

Timer 5 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM5) and a compare register (CR50). The timer is cleared by the TM5-CR50 coincidence signal, and at the same time, an interrupt request is generated.

Figure 3-13. Block Diagram of Timer 5 Unit

Clear

TM5

CR50

Data Sheet U12255EJ2V0DS00

INTCR50

RTP, A/D

PD784927, 784928, 784927Y, 784928Y

(7) Up/down counter unit

The up/down counter unit is a counter that realizes a linear time counter. This unit consists of an up/down counter (UDC) and a compare register (UDCC). The up/down counter counts up the rising edges of PBCTL and counts down the falling edges of PBCTL. When the value of the up/down counter coincides with the value of the compare register, or when the counter underflows, an interrupt request is generated.

Figure 3-14. Block Diagram of Up/Down Counter Unit

SELUD

PTO10 PTO11

PBCTL

Selector

P77

EDVC output

Selector

Selector Selector

UP/DOWN

UDC

UDCC

INTUDC

(8) PWM output unit

The PWM output unit has three 16-bit accuracy output lines (PWM0, PWM1, and PWM5) and 8-bit accuracy output lines (PWM2 through PWM4). The carrier frequency of all the output lines is 62.5 kHz (f

CLK = 8 MHz).

PWM0 and PWM1 can be used to control the drum motor and capstan motor.

Figure 3-15. Block Diagram of 16-Bit PWM Output Unit

(n = 0, 1, 5)

Internal bus

16 8

PWMn

15 8 7 0

PWMC0

16 MHz

Reload

8-bit down counter

1/256

Reload

Reload control

PWM pulse

generation circuit

8-bit counter

Data Sheet U12255EJ2V0DS00

To selector

Output control

circuit

PWMn

RESET

PD784927, 784928, 784927Y, 784928Y

Figure 3-16. Block Diagram of 8-Bit PWM Output Unit

Internal bus

PWM2

8-bit comparator

16 MHz

(9) VISS detection circuit

Figure 3-17. Block Diagram of VISS Detection Circuit

PBCTL

PWM3

8-bit comparator

PWM counter

PWM4

8-bit comparator

PWMC1

Output control

circuit

Output control

circuit

Output control

circuit

PWM4

PWM3

PWM2

CFG signal

CLK

/16

f f

CLK

/64

CLK

/256

Selector

VPS

(VISS pulse pattern

setting register)

UP/DOWN

VUDC

(8-bit up/down counter)

VISS malfunction prevention circuit

VSFT0

(shift register 0)

(VUDC value

setting register)

VCMP

(compare register)

VUDST

VSFT1

(shift register 1)

Coincidence

INTVISS

Data Sheet U12255EJ2V0DS00

(10) VSYNC separation circuit

PD784927, 784928, 784927Y, 784928Y

Figure 3-18. Block Diagram of V

SYNC

signal

CLK

VSUDC

(8-bit up/down

CLK

Selector

counter)

VSCMP

(8-bit compare

"00"

SYNC Separation Circuit

Digital noise rejection circuit

SYNC

F/F

Selector

3.7 Serial Interface

The µPD784927 is provided with the serial interfaces shown in Table 3-6. Data can be automatically transmitted or received through these serial interfaces, when the macro service is used.

SYNC

Table 3-6. Types of Serial Interfaces

Name Function

Serial interface channel 1 • Clocked serial interface (3-wire)

• Bit length: 8 bits

• Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz

(fCLK = 8 MHz)

• MSB first/LSB first selectable

Serial interface channel 2 • Clocked serial interface (3-wire)

• Bit length: 8 bits

• Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz

(fCLK = 8 MHz)

• MSB first/LSB first selectable

• BUSY/STRB control function

Serial interface channel 3 • I2C bus interface

For multimaster

Data Sheet U12255EJ2V0DS00

(1) Serial interface channels 1, 2

Figure 3-19. Block Diagram of Serial Interface Channel n (n = 1 or 2)

SIn /BUSY

SOn

Selector

PD784927, 784928, 784927Y, 784928Y

Internal bus

SIOn register CSIMn register

Serial clock counter

INTCSIn

SCKn

CLK

/16

CLK

/32

f f

CLK

/64

CLK

/128

CLK

/256

STRB

Busy detection circuit

Strobe generation circuit

Selector

CSIC2 register

Internal bus

Remark The circuits enclosed in the broken line are provided to serial interface channel 2 only.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(2) Serial interface channel 3 (µPD784928Y subseries only)

This channel transfers 8-bit data with multiple devices using two lines: serial clock (SCL) and serial data bus (SDA).

It conforms to the I

C bus format, and can output a “start condition”, “data”, and “stop condition” onto the serial data bus during transmission. This data is automatically detected by hardware during reception. SCL and SDA are open-drain output pins and therefore, must be connected with a pull-up resistor.

Figure 3-20. Serial Interface Channel 3

Master CPU1

Slave CPU1

SDA

SCL

Serial data bus Serial clock

SDA

SCL

SDA

SCL

SDA

SCL

SDA

SCL

Master CPU2 Slave CPU2

Address 1

Slave CPU3

Address 2

Slave IC

Address 3

Slave IC

Address N

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.8 A/D Converter

The µPD784927Y has an analog-to-digital (A/D) converter with 12 multiplexed analog inputs (ANI0 through ANI11). This A/D converter is of successive approximation type, and the conversion result is held by an 8-bit A/D conversion

result register (ADCR) (conversion time: 10

A/D conversion can be started in the following two modes:

• Hardware start : Conversion is started by a hardware trigger

• Software start : Conversion is started by setting a bit of the A/D converter mode register (ADM).

After conversion has been started, the A/D converter operates in the following modes:

• Scan mode : Sequentially selects more than one analog input to obtain data to be converted from all the pins.

• Select mode: Use only one pin for analog input to obtain successive data to be converted.

When the conversion result is transferred to ADCR, interrupt request INTAD is generated. By processing this

interrupt with the macro service, the conversion result can be successively transferred to memory.

A mode in which starting A/D conversion of the next pin is kept pending until the value of ADCR is read is also available. When this ode is used, reading the conversion result by mistake when timing is shifted because an interrupt is disabled can be prevented.

s at fCLK = 8 MHz).

Note

Note A hardware trigger is the following coincidence signals, one of which is selected by the trigger source select

• TM0-CR01 coincidence signal

• TM0-CR02 coincidence signal

• TM1-CR13 coincidence signal

• TM5-CR50 coincidence signal

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Figure 3-21. Block Diagram of A/D Converter

ADM.7 (CS)

ANI0 ANI1 ANI2 ANI3

ANI11

TM0-CR01 coincidence TM0-CR02 coincidence TM1-CR13 coincidence TM5-CR50 coincidence

Trigger source select register 1 (TRGS1)

A/D converter mode

Input selectorSelector

Conversion trigger

Trigger enable

Sample & hold circuit

Successive approximation

Control circuit

Delay detection

circuit

A/D conversion result

Internal bus

Voltage comparator

INTAD

A/D conversion

end interrupt

Series resistor string

R/2

Tap selector

R/2

1 : ON

SS2

REF

3.9 VCR Analog Circuits

PD784927 is provided with the following VCR analog circuits:

The

• CTL amplifier

• RECCTL driver (rewritable)

• DPG amplifier

• DFG amplifier

• DPFG separation circuit (ternary separation circuit)

• CFG amplifier

• Reel FG comparator (2 channels)

• CSYNC comparator

Data Sheet U12255EJ2V0DS00

)

PD784927, 784928, 784927Y, 784928Y

(1) CTL amplifier/RECCTL driver

The CTL amplifier is used to amplify the playback control (PBCTL) signal that is reproduced from the CTL signal recorded on a VCR tape. The gain of the CTL amplifier is set by the gain control register (CTLM). Thirty-two types of gains can be set in increments of about 1.78 dB.

PD784927 is also provided with a gain control signal generation circuit that monitors the status of the

The amplifier output to perform optimum gain control by software. The gain control signal generation circuit generates a CTL detection flag that identifies the amplitude status of the CTL amplifier output. By using this CTL detection flag, the gain of the CTL amplifier can be optimized. The RECCTL driver writes a control signal onto a VCR tape. This driver operates in two modes: REC mode that is used for recording, and rewrite mode used to rewrite the VISS signal. The output status of the RECCTL± pin is changed by hardware, by using the timer output from the super timer unit as a trigger.

Figure 3-22. Block Diagram of CTL Amplifier and RECCTL Driver

ANI11

CTLDLY

TOM1.4-TOM1.6

CTL head

CTLOUT1

CTLOUT2

RECCTL+

RECCTL

CTLIN

TM1-CR11 coincidence signal

RECCTL driver

REF

AMPC. 1

CTLM. 0-CTLM. 4

Gain control signal

generation circuit

Waveform

shaping circuit

TM1-CR13 coincidence signal TM3-CR30 coincidence signal

Selector

CTL detection flag L (AMPM0. 1) CTL detection flag S (AMPM0. 3) CTL detection flag clear

(1 write to AMPM0. 6)

PBCTL signal (to timer unit)

CTLMON (to P67

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(2) DPG amplifier, DFG amplifier, and DFPG separation circuit

The DPG amplifier converts the drum PG (DPG) signal that indicates the phase information of the drum motor into a logic signal. The DFG amplifier amplifies the drum FG (DFG) signal that indicates the speed information of the drum motor. The DPFG separation circuit (ternary separation circuit) separates a drum PFG (DPFG) signal having speed and phase information into a DFG and DPG signals.

Figure 3-23. Block Diagram of DPG Amplifier, DFG Amplifier, and DPFG Separation Circuit

AMPC.7

REF

AMPM0.0

Drum PG signal

DPGIN

0 : ON

REF

+ –

DPG amplifier

AMPC.2

DPG comparator

AMPM0.2

Selector

AMPC.2

Selector

DPG signal (to timer unit)

DPGMON (to P65)

Drum FG signal or

drum PFG signal

AMPM0.0

DFGIN

VREFVREF

AMPM0.2

AMPC.2

DFG amplifier

–

AMPC.2

DPFG separation

circuit (ternary

separation circuit)

AMPM0.2

Selector

AMPC.2

Selector

DFG signal (to timer unit)

DFGMON (to P64)

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(3) CFG amplifier

The CFG amplifier amplifies the capstan FG (CFG) signal that indicates the speed information of the capstan motor. This amplifier consists of an operational amplifier and a comparator. The gain of the operational amplifier is set by using an external resistor. When the gain of the operational amplifier is set to 50 dB, the output duty accuracy of the CFG signal can be improved to 50.0 ± 0.3%.

Figure 3-24. Block Diagram of CFG Amplifier

REF

AMPC.3

CFG amplifier

Capstan FG signal

CFGIN

CFGAMPO

CFGCPIN

AMPM0.0

REF

AMPC.3

CFG comparator

AMPC.3

Selector

CFG signal (to timer unit)

CFGMON (to P66)

(4) Reel FG comparators

The reel FG comparator converts a reel FG signal that indicates the speed information of the reel motor into a logic signal. Two comparators, one for take-up and the other for supply, are provided.

Figure 3-25. Block Diagram of Reel FG Comparators

REF

Supply reel signal

Take-up reel signal

AMPM0.0

REEL0IN

AMPM0.0

REEL1IN

AMPC.6

Reel FG comparator

REF

AMPC.6

Reel FG comparator

Data Sheet U12255EJ2V0DS00

SelectorSelector

AMPC.6

Reel FG0 signal (to timer unit)

Reel FG1 signal (to timer unit)

PD784927, 784928, 784927Y, 784928Y

(5) CSYNC comparator

The CSYNC comparator converts the COMPSYNC signal into a logic signal.

Figure 3-26. Block Diagram of COMPSYNC Comparator

REF

AMPM1.7

AMPC.5

AMPM0.0

COMP

SYNC

signal

CSYNCIN

CSYNC comparator

(6) Reference amplifier

The reference amplifier generates a reference voltage (V

REF) to be supplied to the internal amplifiers and

comparators of the µPD784927.

AMPC.5

Selector

SYNC

signal

C (to timer unit)

VREFC

Figure 3-27. Block Diagram of Reference Amplifier

DD1

SS1

ENCAP (AMPC.3)

REF

(CFG amplifier)

REF

(CFG amplifier)

ENCTL (AMPC.1)

REF

(CTL amplifier)

ENDRUM (AMPC.2) ENREEL (AMPC.6) ENCSYN (AMPC.5)

REF

DFG amplifier, DPG comparator, reel FG comparator, and CSYNC comparator)

Remark Multiple reference amplifiers are provided to assure the accuracy of the amplifiers and comparators.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(7) Analog circuit monitor function

This function is to output the following signals to port pins, and is mainly used for debugging.

• Comparator output of CTL amplifier → CTLMON (multiplexed port: P67)

• Comparator output of CFG amplifier → CFGMON (multiplexed port: P66)

• Comparator output of DPG amplifier → DPGMON (multiplexed port: P65)

• Comparator output of DFG amplifier → DFGMON (multiplexed port: P64)

3.10 Watch Function

PD784927 has a watch function that counts the overflow signals of the watch timer by hardware. As the clock,

The

the subsystem clock (32.768 kHz) is used.

Because this watch function is independent of the CPU, it can be used even while the CPU is in the standby mode

(STOP mode) or is reset. In addition, this function can be used at a low voltage of V

DD = 2.7 V (MIN.).

Therefore, by using only the watch function with the CPU set in the standby mode or reset, a watch operation can

be performed at a low voltage and low current consumption.

In addition, the watch function can also be used while the CPU is in the normal operation mode, because a dedicated

counter is provided.

The watch function can be used to count up to about 17 years of data. The hardware watch counters (HW0 and HW1) are shared with external input counters. These counters execute

counting at the falling edge of input to the P65 pin, and can be used to count the H

SYNC signals.

P65

(32.768 kHz)

Figure 3-28. Block Diagram of Watch Counter

P65

WM.2 (enables/disables operation)

013

Watch timer

Normal

Fast forward

WM.1

WM.5 WM.4

SelectorSelector

WM.7

WM.2

PM65 PMC65

CMS5

Edge detection

Pin level read

015013

HW0 HW1

Selector

Subclock

BUZ signal

WM.2

Selector

WM.6

WM.2 (enables/disables operation)

To NMI generation block

INTW

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.11 Clock Output Function

The µPD784927 can output a square wave (with a duty factor of 50%) to the P60/STRB/CLO pin as the operating clock for the peripheral devices or other microcomputers. To enable or disable the clock output, and to set the frequency of the clock, the clock output mode register (CLOM) is used.

When setting the frequency, the division ratio can be set to f

CLK/n (where n = 1, 2, 4, 8, 16, 32, 64, or 128) (fCLK

= fOSC/2: fOSC is the oscillation frequency of the resonator).

Figure 3-29 shows the block diagram of the clock output circuit.

The clock output (CLO) pin is shared with P60 and STRB.

Figure 3-29. Block Diagram of Clock Output Circuit

CLK

f f

CLK

/16

CLK

/32

CLK

/64

CLK

/128

Remark f

CLOM

Selector

P60

(Output latch)

CLK: internal system clock

CLOM7 CLOM6 CLOM5 ENCLO 0

Selector

RESET

SELFRQ2 SELFRQ1 SELFRQ0

P60/STRB/CLO

Caution Do not use the clock output function in the STOP mode. Clear ENCLO (CLOM.4) to 0 in the STOP

mode.

Figure 3-30. Application Example of Clock Output Function

PD784927

System clock

CLO

SCK1

SI1

SO1

PD7503A

CL1 SCK SO SI

LCD

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.12 Buzzer Output Function

The BUZ signal can be superimposed on P61 or P64. The buzzer output frequency can be generated from the subsystem clock frequency or main system clock

frequency.

Figure 3-31 shows the block diagram of the BUZ output circuit. The BUZ signal can be also used for trimming the subsystem clock.

Figure 3-31. Block Diagram of BUZ Output Circuit

WM4 WM5

2.048 kHz

CMS4

WM7

4.096 kHz

32.768 kHz

CLK

/512

CLK

/1024

CLK

/2048

CLK

/4096

CLOM5 CLOM6

SelectorSelector

CLOM7

Selector

P61

(Output latch)

BUZ

output

P64

(Output latch)

BUZ

output

P61/BUZ

SelectorSelector

P64/BUZ

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

4. INTERNAL/EXTERNAL CONTROL FUNCTION

4.1 Interrupt Function

The µPD784927 has as many as 32 interrupt sources, including internal and external sources. For 28 sources, a high-speed interrupt processing mode such as context switching or macro service can be specified by software.

Table 4-1 lists the interrupt sources.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 4-1. Interrupt Sources

Interrupt

Request Priority Service

Type Reset — RESET RESET pin input — No No — 0000H Non- — NMI NMI pin input edge — — 0002H maskable Maskable 0 INTP0 INTP0 pin input edge PIC0 Yes Yes FE06H 0006H

Operand — — Illegal operand of MOV STBC, #byte or — No No — 003CH error LOCATION instruction Software — — Execution of BRK instruction — — 003EH

Name Trigger

1 INTCPT3 EDVC output signal (CPT3 capture) CPTIC3 FE08H 0008H 2 INTCPT2 DFGIN pin input edge (CPT2 capture) CPTIC2 FE0AH 000AH 3 INTCR12 PBCTL input edge/EDVC output signal CRIC12 FE0CH 000CH

4 INTCR00 TM0-CR00 coincidence signal CRIC00 FE0EH 000EH 5 INTCLR1 CSYNCIN pin input edge CLRIC1 FE10H 0010H 6 INTCR10 TM1-CR10 coincidence signal CRIC10 FE12H 0012H 7 INTCR01 TM0-CR01 coincidence signal CRIC01 FE14H 0014H 8 INTCR02 TM0-CR02 coincidence signal CRIC02 FE16H 0016H 9 INTCR11 TM1-CR11 coincidence signal CRIC11 FE18H 0018H

10 INTCPT1 Pin input edge/EC output signal CPTIC1 FE1AH 001AH

11 INTCR20 TM2-CR20 coincidence signal CRIC20 FE1CH 001CH 12 INTIIC End of I2C bus transfer IICIC 13 INTTB Time base from FRC TBIC FE20H 0020H 14 INTAD A/D converter conversion end ADIC FE22H 0022H 15 INTP2 INTP2 pin input edge PIC2 FE24H 0024H

INTCR40 TM4-CR40 coincidence signal CRIC40 16 INTUDC UDC-UDCC coincidence/UDC underflow UDCIC FE26H 0026H 17 INTCR30 TM3-CR30 coincidence signal CRIC30 FE28H 0028H 18 INTCR50 TM5-CR50 coincidence signal CRIC50 FE2AH 002AH 19 INTCR13 TM1-CR13 coincidence signal CRIC13 FE2CH 002CH 20 INTCSI1 End of serial transfer (channel 1) CSIIC1 FE2EH 002EH 21 INTW Overflow of watch timer WIC FE30H 0030H 22 INTVISS VISS detection signal VISIC FE32H 0032H 23 INTP1 INTP1 pin input edge PIC1 FE34H 0034H 24 INTP3 INTP3 pin input edge PIC3 FE36H 0036H 25 INTCSI2 End of serial transfer (channel 2) CSIIC2 FE3AH 003AH

— — Execution of BRKCS instruction — Yes — —

Interrupt Request Source

(CR12 capture)

(CPT1 capture)

Interrupt

Control

Name

Note

Macro Context

Switching Control Word

Macro Service

Address Address

FE1EH 001EH

Vector

Table

NoteµPD784928Y subseries only.

Remark EVDC : Event divider compare register

EC : Event counter FRC : Free running counter MSCW : Macro service control register

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Figure 4-1. Differences in Operation Depending on Interrupt Processing Mode

Macro service

Context switching

Vectored interrupt

Note 1

Vectored interrupt

Main routine

Macro service processing

Note 2

Note 4

SEL RBn

Saving general-purpose register

Main routine

Interrupt processing

Initializing general-purpose register

Note 3

Interrupt processing

Main routine

Restoring PC and PSW

Main routine

Restoring general-purpose register

Restoring PC and PSW

Main routine

Interrupt request generated

Notes 1. When the register bank switching function is used and when initial values are set in advance to the

registers

2. Selecting a register bank and saving PC and PSW by context switching

3. Restoring register bank, PC, and PSW by context switching

4. Saves PC and PSW to stack and loads vector address to PC

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

4.1.1 Vectored interrupt

When an interrupt request is acknowledged, an interrupt processing program is executed according to the data

stored in the vector table area (the first address of the interrupt processing program created by the user).

In addition, four levels of priorities can be specified by software.

4.1.2 Context switching

When an interrupt request is generated or when the BRKCS instruction is executed, a specific register bank is selected by hardware, and execution branches to a vector address set in advance in the register bank. At the same time, the current contents of the program counter (PC) and program status word (PSW) are saved to the registers in the register bank. Because the contents of PC and PSW are not saved to the stack area, execution can be branched to an interrupt processing routine more quickly than the vectored interrupt.

Figure 4-2. Context Switching Operation When Interrupt Request Is Generated

<7> 0H

PC19-16 PC15-0

<2> Save

Bits 8-11 of temporary register

<1> Save

PSW

<6> Exchange

<5> Save

Temporary register

B R5 R7

UP D H

R4 R6

(0-7)

X C

<3>

Switching register bank (RBS0-RBS2 ← n)

<4>

RSS

← 0

E L

← 0

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

4.1.3 Macro service

The macro service is a function to transfer data between the memory and a special function register (SFR) without

intervention by the CPU. A macro service controller accesses the memory and SFR and directly transfers the data.

Because the status of the CPU is not saved or restored, data can be transferred more quickly than context switching. The processing that can be executed with the macro service is described below.

Figure 4-3. Macro Service

CPU Memory SFR

Internal bus

Read Write

Macro service

controller

Write Read

(1) Counter mode

In this mode, the value of the macro service counter (MSC) is decremented when an interrupt request occurs. This mode can be used to execute the division operation of an interrupt request or count the number of times an interrupt request has occurred. When the value of the macro service counter has been decremented to 0, a vectored interrupt occurs.

MSC

(2) Compound data transfer mode

When an interrupt request occurs, data are simultaneously transferred from an 8-bit SFR to memory, a 16bit SFR to memory (word), memory (byte) to an 8-bit SFR, and memory (word) to a 16-bit SFR (3 points MAX. for each transfer). This mode can also be used to exchange data, instead of transferring data. This mode can be used for automatic transfer/reception by the serial interface or automatic updating of data/ timing by the serial output port. When the value of the macro service counter reaches to 0, a vectored interrupt request occurs.

SFR<4>-1

SFR<2>-1

SFR<4>-2 SFR<4>-3 SFR<3>-1 SFR<3>-2 SFR<3>-3

Internal bus

SFR<2>-2 SFR<2>-3 SFR<1>-1 SFR<1>-2 SFR<1>-3

Internal bus

Data Sheet U12255EJ2V0DS00

Memory

(

)

PD784927, 784928, 784927Y, 784928Y

(3) Macro service type A

When an interrupt request occurs, data is transferred from an 8-/16-bit SFR to memory (byte/word) or from memory (byte/word) to an 8-/16-bit SFR. Data is transferred the number of times set in advance by the macro service counter. This mode can be used to store the result of A/D conversion or for automatic transfer (or reception) by the serial interface. Because transfer data is stored at an address FE00H to FEFFH, if only a small quantity of data is to be transferred, the data can be transferred at high speeds. When the value of the macro service counter is decremented to 0, a vectored interrupt request occurs.

Data storage buffer (memory)

Data n

Internal bus

Data 2 Data 1

SFR

Data storage buffer (memory)

Data n

Internal bus

Data 2 Data 1

SFR

(4) Data pattern identification mode (VISS detection mode)

This mode of macro service is for detection of the VISS signal and is used in combination with a pulse width detection circuit. When an interrupt request occurs, the content of bit 7 of an SFR (usually, TMC3) specified by SFR pointer 1 is shifted into the buffer area. At the same time, the data in the buffer area is compared with the data in the compare area. If the two data coincide, a vectored interrupt request is generated. When the value of the macro service counter is decremented to 0, a vectored interrupt request occurs. It can be specified by option that the value of an SFR (usually, CPT30) specified by SFR pointer 2 be multiplied by a coefficient and the result of this multiplication be stored to an SFR (usually, CR30) specified by SFR pointer 3 (this operation is to automatically update an identification threshold value when the tape speed fluctuates).

Coefficient (memory)

Multiplier

Buffer area (memory) Compare area (memory)

CPT30

TM3

Coincidence

CR30

CTL F/F

bit 7 of TMC3

Data Sheet U12255EJ2V0DS00

Vectored interrupt

(

)

PD784927, 784928, 784927Y, 784928Y

4.1.4 Application example of macro service

(1) Automatic transfer/reception of serial interface

Automatic transfer/reception of 3-byte data by serial interface channel 1 Setting of macro service register: compound data transfer mode (exchange mode)

Macro service channel

Macro service control word

SI1

SO1

Macro service counter (MSC = 2)

Memory pointer H (= FD)

Memory pointer L (= 50)

ddccbbaa (= 01000100B)

SFR pointer <2> (SFRP2 = 85H) SFR pointer <4> (SFRP4 = 85H)

Channel pointer (= 50H)

Mode register (= 10110011B)

(Exchange 2)

SIO1 (FF85H) <3>

<2>

FE50H

FE2EH

(Before transfer)

Transmit data 3

Transmit data 2

High-order address

Low-order address

FD52H

FD51H

(Exchange 1)

Transfer is started by writing

<1>

transmit data 1 to SIO1 by software.

(Transmit data 1)

(After transfer)

Receive data 2 FD51H

Receive data 1

Receive data 3 is the data of SIO1.

FD50H

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(2) Reception operation of serial interface

Transfer of receive data by serial interface channel 1 (16 bytes) Setting of macro service mode register: macro service type A (1-byte data transfer from SFR to memory)

Internal RAM

FE7FH

FE2EH

MSC 0FH

SFR pointer 85H

Channel pointer (= 7FH)

Mode register (= 00010001B)

Setting of number of transfers Low-order 8 bits of address of SIO1 register

Starts macro service when INTCSI1 occurs

SI1

SIO1

(FF85H)

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(3) VISS detection operation

Setting of macro service mode register: data pattern identification mode (with multiplication, 8-byte comparison)

CPT30

High-order address

FE50H

8 bytes

Macro service counter (MSC = FFH) SFR pointer 2 (SFRP2 = 56H)

Coefficient (6EH: 43%)

SFR pointer 3 (SFRP3 = 5CH)

SFR pointer 1 (SFRP1 = 3BH)

Buffer size specification

11111111

11111110

Compare area pointer (high): 10H

Compare area pointer (low): 50H

Coincidence (vectored interrupt)

Multiplier

Bit 7

TM3

CR30

TMC3

00000000

1050H 8 bytes

Channel pointer (= 50H)

FE0CH

Low-order address

Mode register (= 00010100B)

(CTL signal input edge detection interrupt)

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

4.2 Standby Function

The standby function is to reduce the power consumption of the chip and is used in the following modes:

Mode Function

HALT mode Stops operating clock of CPU. Reduces average power consumption when used

in combination with normal mode for intermittent operation

STOP mode Stops oscillator. Stops all internal operations of chip to minimize power consump-

tion to leakage current only

Low power consumption mode Stops main system clock with subsystem clock used as system clock. CPU can

operate with subsystem clock to reduce current consumption

Low power consumption HALT mode Standby function in low power consumption mode. Stops operating clock of CPU.

Reduces power consumption of overall system

These modes are programmable. The macro service can be started in the HALT mode.

Figure 4-4. Status Transition of Standby Function

Macro service request

End of one processing

End of macro service

Sets HALT

Interrupt request

Note 2

Macro service request

End of one processing

HALT mode

(standby)

service

Note 1

NMI input

INTW, INTP2 interrupt request

Low power

consumption

HALT mode

(standby)

Low power

consumption mode

(subsystem

clock operation)

Sets low power consumption HALT mode

Sets low power consumption mode Restores normal operation

End of oscillation stabilization period

Waits for

stabilization

of oscillation

NMI input

RESET input

Note 1

STOP mode

(standby)

Normal

operation

RESET input

Sets STOP

Unmasked interrupt request

Notes 1. NMI input means starting NMI by NMI pin input, watch interrupt, or key interrupt input.

2. Unmasked interrupt request

Macro

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Figure 4-5. Relations among NMI, Watch Interrupt, and Key Interrupt When STOP Mode Is Released

INTM0.0

Standby control

block

NMI

INTP1 INTP2

KEY0 KEY1 KEY2 KEY3 KEY4

Mask Mask Mask

Selector

KEYC.6 KEYC.5 KEYC.4

Latch

Clear

SRQ KEYC.7

Cleared when "0" is written to KEYC.7

SRQ KEYC.0

Cleared when "0" is written to KEYC.0

Mask

WM.3

WM.6

Selector

Interrupt control

block

Watch timer

INTW (OVF)

Divides INTW by 128 (HW0L.7)

Data Sheet U12255EJ2V0DS00

16 MHz or 8 MHz

XT1

XT2

32.768 kHz

PD784927

Main

system

clock

oscillation

circuit

Oscillation stop

From standby control block

Subsystem

clock

oscillation

circuit

STBC.7

Oscillation stop

1/2

Watch timer

Hardware watch function

Watch interrupt

Normal mode

Low-frequency

oscillation mode

CC.7

Selector

1/2

Oscillation stabilization timer

STBC.4, 5

STBC.6

/16 (f

/8)

Note 1

Selector

/8 (f

/4)

Note 1

/4 (f

/2)

Note 1

/2 (f

)

Note 1

CPU

Peripheral hardware

operation clock

Note 2

CLK

PD784927, 784928, 784927Y, 784928Y

4.3 Clock Generation Circuit

The clock generation circuit generates and controls the internal system clock (CLK) to be supplied to the CPU and

peripheral circuits. Figure 4-6 shows the configuration of this circuit.

PD784928,

Figure 4-6. Block Diagram of Clock Generation Circuit

XX: oscillation frequency, ( ): in low-frequency oscillation mode.

Notes 1. f

Data Sheet U12255EJ2V0DS00

784928Y Subseries User’s Manual-Hardware (U12648E).

2. The peripheral hardware units that can operate with the subsystem clock have some restrictions. For details, refer to

PD784927, 784928, 784927Y, 784928Y

4.4 Reset Function

When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset status). During the reset period, oscillation of the system clock is unconditionally stopped, so that the current consumption of the overall system can be reduced.

When the RESET pin goes high, the reset status is cleared. After the count time of the oscillation stabilization timer (32.8 ms at 16 MHz or 65.6 ms at 8 MHz) has elapsed, the contents of the reset vector table are set to the program counter (PC), and execution branches to the address set to the PC, and the program is executed starting from the branch destination address. Therefore, execution can be reset and started from any address.

Figure 4-7. Oscillation of Main System Clock during Reset Period

Main system clock oscillation circuit

During reset, oscillation is unconditionally stopped.

CLT

RESET input

Oscillation stabilization timer count time

The RESET pin is provided with an analog delay noise rejection circuit to prevent malfunctioning due to noise.

Figure 4-8. Accepting Reset Signal

delay

Oscillation

stabilization

time

Analog delay Analog delay

Analog

RESET input

Internal reset signal

Internal clock

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

5. INSTRUCTION SET

(1) 8-bit instructions (( ): combination realized by using A as r)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA

2nd Operand # byte A r saddr sfr !addr16 mem r3 [WHL+] [WHL–] n

None

r' saddr' !!addr24 [saddrp] PSWL 1st Operand [%saddrg] PSWH A (MOV) (MOV) MOV

Note 1

ADD

(XCH) XCH

Note 1

(ADD)

Note 1

r MOV (MOV) MOV MOV MOV MOV

Note 1

ADD

(XCH) XCH XCH XCH XCH DIVUW (ADD)

Note 1

ADD

Note 1

(MOV) (XCH) (ADD)

ADD

Note 6

MOV (MOV) MOV MOV (MOV) (MOV)

Note 6

(XCH) (XCH) XCH (XCH) (XCH)

Notes 1,6

Note 1

(ADD)

ADD

Note 1

ADD

Note 1

ADD

Note 1

(ADD)

Note 1

(ADD)

Note 1

ROR

Note 3

MULU

INC DEC

saddr MOV

ADD

Note 1

(MOV) (ADD)

Note 6

MOV MOV INC

Note 1

ADD

Note 1

XCH DEC

Note 1

ADD

DBNZ

sfr MOV MOV MOV PUSH

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

POP CHKL

CHKLA !addr16 MOV (MOV) MOV !!addr24

ADD

Note 1

mem MOV [saddrp]

ADD

Note 1

[%saddrg] mem3 ROR4

ROL4 r3 MOV MOV PSWL PSWH B, C DBNZ STBC, WDM MOV [TDE+] (MOV)

(ADD) MOVM

[TDE–] (MOV)

(ADD) MOVM

Note 1 Note 4

Note 1

Note 4

MOVBK

Note 5

MOVBK

Note 5

Note 2

Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD.

2. Either the second operand is not used, or the second operation is not an operand address.

3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR.

4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM.

5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK.

6. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(2) 16-bit instructions (( ): combination realized by using AX as rp)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

2nd Operand # word AX rp saddrp sfrp !addr16 mem [WHL+] byte n None

rp' saddrp !!addr24 [saddrp] 1st Operand [%saddrg] AX (MOVM) (MOVW) (MOVW)

Note 1

ADDW

(XCHW) (XCHW) (

Note 1

(ADDW)

Note 1

(MOVW)

XCHW

(ADDW)

Note 3

MOVW (MOVW) MOVW (MOVW)

Note 3

)

(XCHW) XCHW XCHW (XCHW)

Notes 1,3

(ADDW)

Note 1

rp MOVW (MOVW) MOVW MOVW MOVW MOVW SHRW MULW

Note 1

ADDW

saddrp MOVW

ADDW

(XCHW) XCHW XCHW XCHW SHLW INCW

Note 1

(ADDW) (MOVW) (ADDW)

Note 1

Note 3

Note 1

ADDW

Note 1

ADDW

Note 1

ADDW

Note 1

MOVW MOVW INCW

Note 1

ADDW

XCHW DECW

Note 1

ADDW

DECW

sfrp MOVW MOVW MOVW PUSH

Note 1

ADDW

!addr16 MOVW (MOVW) MOVW

(ADDW)

Note 1

ADDW

Note 1

POP

MOVTBLW !!addr24 mem MOVW [saddrp] [%saddrg] PSW PUSH

POP

SP ADDWG

SUBWG

post PUSH

POP PUSHU

POPU [TDE+] (MOVW) SACW byte MACW

MACSW

Note 2

Note 4

Notes 1. SUBW and CMPW are the same as ADDW.

2. Either the second operand is not used, or the second operation is not an operand address.

3. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short.

4. MULUW and DIVUX are the same as MULW.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(3) 24-bit instructions (( ): combination realized by using WHL as rg)

MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP

2nd Operand # imm24 WHL rg saddrg !!addr24 mem1 [%saddrg] SP None

rg' 1st Operand WHL (MOVG) (MOVG) (MOVG) (MOVG) (MOVG) MOVG MOVG MOVG

(ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG

rg MOVG (MOVG) MOVG MOVG MOVG INCG

ADDG (ADDG) ADDG DECG SUBG (SUBG) SUBG PUSH

POP saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG [%saddrg] MOVG SP MOVG MOVG INCG

DECG

Note Either the second operand is not used, or the second operation is not an operand address.

(4) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET

2nd Operand CY saddr.bit /saddr.bit None

sfr.bit /sfr.bit A.bit /A.bit X.bit /X.bit PSWL.bit /PSWL.bit PSWH.bit /PSWH.bit mem2.bit /mem2.bit iaddr16.bit /!addr16.bit

1st Operand !addr24.bit /!!addr24.bit CY MOV1 AND1 NOT1

AND1 OR1 SET1 OR1 CLR1 XOR1

Note

saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit

Note Either the second operand is not used, or the second operation is not an operand address.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(5) Call/return and branch instructions

CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ

Operand of instruction address Basic BC instruction BR BR BR BR BR BR BR BR RET

Compound BF instruction BT

$addr20 $!addr20 !addr16 !!addr20

Note

CALL CALL CALL CALL CALL CALL CALL CALLF CALLT BRKCS BRK

RETCS RETI RETCSB

BTCLR BFSET DBNZ

rp rg [rp] [rg] !addr11 [addr5] RBn None

RETB

Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are

the same as BC.

(6) Other instructions

ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

6. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter Symbol Conditions Ratings Unit

Supply voltage VDD | VDD – AVDD1 | ≤ 0.5 V –0.5 to +7.0 V

AVDD1 | VDD – AVDD2 | ≤ 0.5 V –0.5 to +7.0 V AVDD2 | AVDD1 – AVDD2 | ≤ 0.5 V –0.5 to +7.0 V

AVSS1 –0.5 to +0.5 V

AVSS2 –0.5 to +0.5 V Input voltage VI –0.5 to VDD + 0.5 V Analog input voltage VIAN VDD ≥ AVDD2 –0.5 to AVDD2 + 0.5 V (ANI0-ANI11) VDD < AVDD2 –0.5 to VDD + 0.5 V Output voltage VO –0.5 to VDD + 0.5 V Low-level output current IOL Pin 1 15 mA

Total of all pins 100 mA

High-level output current IOH Pin 1 –10 mA

Total of all pins –50 mA Operating ambient temperature Storage temperature Tstg –65 to +150 °C

TA –10 to +70 °C

Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality

of the product may be degraded. Absolute maximum ratings therefore specify the values exceeding which the product may be physically damaged. Never exceed these values when using the product.

Operating Conditions

Clock Frequency

4 MHz ≤ fXX ≤ 16 MHz –10 to +70°C All functions +4.5 to +5.5 V

32 kHz ≤ fXT ≤ 35 kHz Subclock operation +2.7 to +5.5 V

Operating Ambient Temperature (TA)

Operating Conditions Supply Voltage (VDD)

CPU function only +4.0 to +5.5 V

(CPU, watch, and port functions only)

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Oscillator Characteristics (main clock) (TA = –10 to +70°C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V)

Resonator Recommended Circuit Parameter MIN. MAX. Unit

Crystal resonator Oscillation frequency (fXX) 4 16 MHz

X1 X2 V

C1 C2

Oscillator Characteristics (subclock) (TA = –10 to +70°C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)

Resonator Recommended Circuit Parameter MIN. MAX. Unit

Crystal resonator Oscillation frequency (fXT) 32 35 kHz

XT1 XT2 V

C1 C2

Caution When using the main system clock and subsystem clock oscillator, wire the portion enclosed

by the broken line in the above figures as follows to avoid the adverse influence of wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines. Do not route the wiring in the

neighborhood of a signal line through which a high alternating current flows.

• Always keep the ground point of the capacitor of the oscillator to the same potential as V

SS.

Do not ground the capacitor to a ground pattern to which a high current flows.

• Do not extract signals from the oscillation circuit.

Exercise particular care in using the subsystem clock oscillator because the amplification factor of this circuit is kept low to reduce the current consumption.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

DC Characteristics (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Low-level input voltage VIL1 Pins other than those listed in Note 1 below 0 0.3 VDD V

VIL2 Pins listed in Note 1 below 0 0.2 VDD V VIL3 X1, X2 0 0.4 V

High-level input voltage VIH1 Pins other than those listed in Note 1 below 0.7 VDD VDD V

VIH2 Pins listed in Note 1 below 0.8 VDD VDD V VIH3 X1, X2 VDD – 0.5 VDD V

Low-level output voltage VOL1 IOL = 8.0 mA (pins in Note 2) 1.0 V

VOL2 IOL = 5.0 mA (pins in Note 4) 0.6 V VOL3 IOL = 2.0 mA 0.45 V VOL4 IOL = 100 µA 0.25 V

High-level output voltage VOH1 IOH = –1.0 mA VDD – 1.0 V

VOH2 IOH = –100 µAVDD – 0.4 V Input leakage current ILI 0 ≤ VI ≤ VDD ±10 Output leakage current ILO 0 ≤ VO ≤ VDD ±10 VDD supply current IDD1 Operation fXX = 16 MHz 30 50 mA

mode fXX = 8 MHz (low-frequency os-

cillation mode) Internally, 8 MHz main clock operation fXT = 32.768 kHz 50 80 Subclock operation (CPU, watch, port) VDD = 2.7 V

IDD2 HALT mode fXX = 16 MHz 10 25 mA

fXX = 8 MHz (low-frequency oscillation mode) Internally, 8 MHz main clock operation fXT = 32.768 MHz 25 50 Subclock operation (CPU, watch, port)

VDD = 2.7 V Data hold voltage VDDDR STOP mode 2.5 V Data hold current

Pull-up resistor RL VI = 0 V 25 55 110 kΩ

Note 3

IDDDR

STOP mode VDDDR = 5.0 V STOP mode VDDDR = 2.7 V STOP mode VDDDR = 2.5 V

Subclock oscillates 18 50

Subclock oscillates 2.5 10

Subclock stops 0.2 7.0

Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0 to

P95/KEY4

2. P40 to P47

3. In the STOP mode in which the subclock oscillation is stopped, disconnect the feedback resistor, and

connect the XT1 pin to V

DD.

4. P46, P47

Data Sheet U12255EJ2V0DS00

AC Characteristics

PD784927, 784928, 784927Y, 784928Y

CPU and peripheral circuit operation clock (T

Parameter Symbol Conditions TYP. Unit

CPU operation clock cycle time tCLK fXX = 16 MHz VDD = AVDD = 4.0 to 5.5 V 125 ns

Peripheral operation clock cycle time tCLK1 fXX = 16 MHz 125 ns

A = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)

CPU function only fXX = 16 MHz fXX = 8 MHz low-frequency oscillation mode

(Bit 7 of CC = 1)

fXX = 8MHz low-frequency oscillation mode

(Bit 7 of CC = 1)

Serial interface

(1) SIOn: n = 1 or 2 (T

Parameter Symbol Conditions MIN. MAX. Unit

Serial clock cycle time tCYSK Input External clock 1.0

Serial clock high- and low-level widths tWSKH Input External clock 420 ns

SIn setup time (vs. SCKn ↑)tSSSK 100 ns SIn hold time (vs. SCKn ↑ )tHSSK 400 ns SOn output delay time (vs. SCKn ↓ )tDSSK 0 300 ns

A = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)

Output fCLK1/8 1.0

fCLK1/16 2.0 fCLK1/32 4.0 fCLK1/64 8.0 fCLK1/128 16 fCLK1/256 32

tWSKL Output Internal clock tCYSK/2 – 50 ns

Remarks 1. fCLK1: operating clock of peripheral circuit (8 MHz)

2. n = 1 or 2

(2) SIO2 only (T

SCK2(8) ↑→STRB ↑ tDSTRB tWSKH tCYSK Strobe high-level width tWSTRB tCYSK – 30 tCYSK + 30 ns BUSY setup time tSBUSY 100 ns (vs. BUSY detection timing) BUSY hold time t HBUSY 100 ns (vs. BUSY detection timing) BUSY inactive →SCK2(1) ↓ tLBUSY

A = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Conditions MIN. MAX. Unit

tCYSK + tWSKH

Remarks 1. The value in ( ) following SCK2 indicates the number of SCK2.

2. BUSY is detected after the time of (n + 2) x tCYSK (n = 0, 1, and so on) in respect to SCK2 (8) ↑ .

3. BUSY inactive →SCK2 (1) ↓ is the value when data has been completely written to SIO2.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

I2C bus mode (µPD784928Y subseries only)

Parameter Symbol Standard Mode High-speed Mode Unit

MIN. MAX MIN MAX. SCL clock frequency fCLK 0 100 0 400 kHz Bus free time (between stop and start tBUF 4.7 – 1.3 – conditions) Hold time SCL clock low-level width tLOW 4.7 – 1.3 – SCL clock high-level width tHIGH 4.0 – 0.6 – Start/restart condition setup time tSU : STA 4.7 – 0.6 – Data hold CBUS compatible master tHD : DAT 5.0 – – – time I2C bus 0 Data setup time t SU : DAT 250 – 100 SDA and SCL signal rise time tR – 1000 20+0.1Cb SDA and SCL signal fall time tF – 300 20+0.1Cb Stop condition setup time tSU : STO 4.0 – 0.6 – Pulse width of spike restrained by input tSP ––050ns filter Each bus line capacitative load Cb – 400 – 400 pF

Note 1

tHD : STA 4.0 – 0.6 –

Note 2

–0

Note 2

Note 4

Note 5 Note 5

0.9

300 ns 300 ns

Note 2

–ns

Notes 1. The first clock pulse is generated at the start condition after this period.

2. The device needs to internally supply a hold time of at least 300 ns for the SDA signal to fill the undefined

area at the falling edge of the SCL (V

IHmin. of the SCL signal).

3. Unless the device extends the low hold time (tLOW) of the SCL signal, it is necessary to fill only the maximum data hold time (t

HD : DAT).

4. The high-speed mode I2C bus can be used in the standard mode I2C bus system. In this case, satisfy the following conditions:

• When the device does not extend the low hold time of the SCL signal

SU : DAT ≥ 250 ns

• When the device extends the low hold time of the SCL signal

Send the next data bit to the SDA line before releasing the SCL line (t

= 1250 ns : in the standard mode I2C bus specification)

5. Cb: Total capacitance of one bus line (unit: pF)

Rmax. + tSU:DAT = 1000 + 250

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Other operations (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. MAX. Unit

Timer input signal low-level width tWCTL When DFGIN, CFGIN, DPGIN, REEL0IN, tCLK1 ns

or REEL1IN logic level is input

Timer input signal high-level width tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, tCLK1 ns

or REEL1IN logic level is input Timer input signal valid edge input cycle tPERIN When DFGIN, CFGIN, or DPGIN is input 2 CSYNCIN low-level width tWCR1L

CSYNCIN high-level width tWCR1H

Digital noise Rejected pulse width tWSEP Bit 4 of INTM2 = 0 104tCLK1 ns rejection circuit Bit 4 of INTM2 = 1 176tCLK1 ns

Passed pulse width Bit 4 of INTM2 = 0 108tCLK1 ns

NMI low-level width tWNIL VDD = AVDD = 2.7 to 5.5 V 10 NMI high-level width tWNIH VDD = AVDD = 2.7 to 5.5 V 10 INTP0, INTP3 low-level widths tWIPL0 2tCLK1 ns INTP0, INTP3 high-level widths tWIPH0 2tCLK1 ns INTP1, KEY0-KEY4 low-level widths tWIPL1 Mode other than STOP mode 2tCLK1 ns

INTP1, KEY0-KEY4 high-level widths tWIPH1 Mode other than STOP mode 2tCLK1 ns

INTP2 low-level width tWIPL2 In normal mode, Sampling = fCLK 2tCLK1 ns

INTP2 high-level width tWIPH2 In normal mode, Sampling = fCLK 2tCLK1 ns

RESET low-level width tWRSL 10

When digital noise rejection circuit is not used

When digital noise rejection circuit is used 108tCLK1 ns

(Bit 4 of INTM2 = 0)

When digital noise rejection circuit is used 180tCLK1 ns

(Bit 4 of INTM2 = 1)

When digital noise rejection circuit is not used

When digital noise rejection circuit is used 108tCLK1 ns

(Bit 4 of INTM2 = 0)

When digital noise rejection circuit is used 180tCLK1 ns

(Bit 4 of INTM2 = 1)

Bit 4 of INTM2 = 1 180tCLK1 ns

In STOP mode, for releasing STOP mode 10

with main clock Sampling = fCLK/128 32

Normal mode, Sampling = fCLK 61

with subclock Sampling = fCLK/128 7.9

In STOP mode, for releasing STOP mode 10

with main clock Sampling = fCLK/128 32

Normal mode, Sampling = fCLK 61

with subclock Sampling = fCLK/128 7.9

In STOP mode, for releasing STOP mode 10

8tCLK1 ns

Note

µ µ

s s

Note If a high or low level is successively input two times during the sampling period, a high or low level is

detected.

Remark t

CKL1: operating clock cycle time of peripheral circuit (125 ns)

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Clock output operation (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. MAX. Unit CLO cycle time tCYCL nT 125 16000 ns CLO low-level width tCLL tCYCL/2 ± 25 37.5 8025 ns CLO high-level width tCLH tCYCL/2 ± 25 37.5 8025 ns CLO rise time tCLR 25 ns CLO fall time tCLF 25 ns

Remarks 1. n: system clock division

2. T = 1/fCLK

Data hold characteristics (TA = –10 to +70°C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit Low-level input voltage VIL Special pins (pins in Note) 0 0.1 VDDDR V High-level input voltage V IH 0.9 VDDDR VDDDR V

Note RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/

KEY4

Watch function (T

Subclock oscillation hold voltage VDDXT 2.7 V Hardware watch function operating voltage

A = –10 to +70°C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. MAX. Unit

VDDW 2.7 V

Subclock oscillation stop detection flag (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. MAX. Unit Oscillation stop detection width tOSCF 45

A/D converter characteristics (TA = –10 to +70°C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit Resolution 8 bit Total error AVREF = VDD 2.0 % Quantization error ±1/2 LSB Conversion time tCONV Bit 4 of ADM = 0 160tCLK1

Bit 4 of ADM = 1 80tCLK1

Sampling time tSAMP Bit 4 of ADM = 0 32tCLK1

Bit 4 of ADM = 1 16tCLK1 Analog input voltage VIAN 0AVREF V Analog input impedance ZAN 1000 MΩ AVREF current AIREF 0.4 1.2 mA

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

VREF amplifier (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit Reference voltage VREF 2.35 2.50 2.65 V Charge current ICHG Sets AMPM0.0 to 1 300

(pins in Note)

Note RECCTL+, RECCTL–, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN

CTL amplifier (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit CTL+, – input resistance RICTL 2510kΩ Feedback resistance RFCTL 20 50 100 kΩ Bias resistance RBCTL 20 50 100 kΩ Minimum voltage gain GCTLMIN 17 20 22 dB Maximum voltage gain GCTLMAX 71 75 dB Gain selecting step SGAIN 1.77 dB Same phase signal elimination ratio CMR DC, voltage gain: 20 dB 50 dB High comparator set voltage of waveform shaping High comparator reset voltage of waveform shaping Low comparator set voltage of waveform shaping Low comparator reset voltage of waveform shaping Comparator Schmitt width of waveform shaping High comparator voltage of CTL flag S VFSH Low comparator voltage of CLT flag S V FSL High comparator voltage of CTL flag L VFLH Low comparator voltage of CTL flag L VFLL

VPBCTLHS VPBCTLHR VPBCTLLS VPBCTLLR

VPBSH

VREF + 0.47 VREF + 0.50 VREF + 0.53 VREF + 0.27 VREF + 0.30 VREF + 0.33 VREF – 0.53 VREF – 0.50 VREF – 0.47 VREF – 0.33 VREF – 0.30 VREF – 0.27

150 200 250 mV VREF + 1.00 VREF + 1.05 VREF + 1.10 VREF – 1.10 VREF – 1.05 VREF – 1.00 VREF + 1.40 VREF + 1.45 VREF + 1.50 VREF – 1.50 VREF – 1.45 VREF – 1.40

V V V V

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

CFG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit Voltage gain 1 GCFG1 fi = 2 kHz, open loop 50 dB Voltage gain 2 GCFG2 fi = 30 kHz, open loop 34 dB CFGAMPO High-level output current IOHCFG DC – 1 mA CFGAMPO Low-level output current IOLCFG DC 0.1 mA High comparator voltage VCFGH Low comparator voltage VCFGL Duty accuracy PDUTY Note 49.7 50.0 50.3 %

VREF + 0.09 VREF + 0.12 VREF + 0.15 VREF – 0.15 VREF – 0.12 VREF – 0.09

Note The conditions include the following circuit and input signal.

V V

Input signal : Sine wave input (5 mV

fi = 1 kHz

Voltage gain: 50 dB

DFG amplifier (AC coupling) (T

Parameter Symbol Condition MIN. TYP. MAX. Unit Voltage gain GDFG f i = 900 Hz, open loop 50 dB Feedback resistance RFDFG 160 400 640 kΩ Input protection resistance RIDFG 150 Ω High comparator voltage VDFGH Low comparator voltage VDFGL

A = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

p-p)

–+

22 F

1 kΩ

330 kΩ

PD784927

CFGIN

CFGAMPO

0.01 F

CFGCPIN

VREF + 0.07 VREF + 0.10 VREF + 0.14 VREF – 0.14 VREF – 0.10 VREF – 0.07

V V

Caution Set the input resistance connected to the DFGIN pin to 16 kΩ or below. Connecting a resistor

exceeding that value may cause the DFG amp to oscillate.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

DPG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit Voltage gain GDPG fI = 30 Hz 20 dB High comparator voltage VDPGH1

VDPGH2 VDPGH3

Low comparator voltage VDPGL1

VDPGL2 VDPGL3

SELDPGHL0 = 0, SELDPGHL1 = 0 SELDPGHL0 = 1, SELDPGHL1 = 0 SELDPGHL0 = 0, SELDPGHL1 = 1 SELDPGHL0 = 0, SELDPGHL1 = 0 SELDPGHL0 = 1, SELDPGHL1 = 0 SELDPGHL0 = 0, SELDPGHL1 = 1

VREF + 0.02 VREF + 0.05 VREF + 0.08 VREF + 0.56 VREF + 0.60 VREF + 0.64 VREF – 0.44 VREF – 0.40 VREF – 0.36 VREF – 0.08 VREF – 0.05 VREF – 0.02 VREF + 0.36 VREF + 0.40 VREF + 0.44 VREF – 0.64 VREF – 0.60 VREF – 0.56

Caution When both the SELDPGHL0 and SELDPGHL1 are set to 0, the DPG amplifier is not used.

Therefore, be sure to set AMPC.7 (ENDPG) to 0.

V V V V V V

Ternary separation circuit (T

Parameter Symbol Condition MIN. TYP. MAX. Unit Input impedance ZIPFG 20 50 100 kΩ High comparator voltage VPFGH VREF + 0.5 VREF + 0.7 VREF + 0.9 V Low comparator voltage VPFGL VREF – 1.4 VREF – 1.2 VREF – 1.0 V

A = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

CSYNC comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit Input impedance ZICSYN 20 50 100 kΩ High comparator voltage VCSYNH Low comparator voltage VCSYNL

VREF + 0.07 VREF + 0.10 VREF + 0.13 VREF – 0.13 VREF – 0.10 VREF – 0.07

Reel FG comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit Input impedance ZIRLFG 20 50 100 kΩ High comparator voltage VRLFGH Low comparator voltage VRLFGL

VREF + 0.02 VREF + 0.05 VREF + 0.08 VREF – 0.08 VREF – 0.05 VREF – 0.02

V V

RECCTL driver (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)

Parameter Symbol Condition MIN. TYP. MAX. Unit RECCTL+, – high-level output voltage VCHREC IOH = –4 mA VDD – 0.8 V RECCTL+, – low-level output voltage VOLREC IOL = 4 mA 0.8 V CTLDLY internal resistance RCTL 40 70 140 kΩ CTLDLY charge current IOHCTL Use of internal resistor –3 mA CTLDLY discharge current IOLCTL –3 mA

Data Sheet U12255EJ2V0DS00

Timing waveform

AC timing test point

PD784927, 784928, 784927Y, 784928Y

0.8 VDD or 2.2 V

0.8 V

Serial transfer timing (SIOn: n = 1 or 2)

WSKL

SCKn

SIn

SOn

CYSK

WSKH

Test point

DSSK

Output data

0.8 VDD or 2.2 V

0.8 V

SSSK

HSSK

Input data

Data Sheet U12255EJ2V0DS00

Serial transfer timing (SIO2 only)

No busy processing

WSKL

WSKH

PD784927, 784928, 784927Y, 784928Y

SCK2

BUSY

CYSK

Active high Busy invalid

STRB

Continuation of busy processing

WSKL

SCK2

BUSY

STRB

WSKH

78910

CYSK

Active high

89101 2

DSTRB

WSTRB

10+n

DSTRB

WSTRB

SBUSY

End of busy processing

tWSKL tWSKH

SCK2

BUSY

7 8 9 10+n 11+n

tCYSK

tHBUSY tLBUSY

Active high

Caution When an external clock is selected as the serial clock, do not use the busy control or strobe

control.

Data Sheet U12255EJ2V0DS00

I2C bus mode (µPD784928Y subseries only)

SCL

SDA

LOW

HD : STA

BUF

HD : DAT

HIGH

SU : DAT

PD784927, 784928, 784927Y, 784928Y

SU : STA

HD : STA

SU : STO

Stop condition

Start condition

Restart condition

Stop condition

Data Sheet U12255EJ2V0DS00

Super timer unit input timing

When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input

When CSYNCIN logic level is input

Interrupt request input timing

0.8 V

PD784927, 784928, 784927Y, 784928Y

WCTH

WCTL

0.8 V

WCR1H

WCR1L

0.8 V

NMI

INTP0, INTP3

INTP1, KEY0-KEY4

INTP2

0.8 V

WNIH

WNIL

0.8 V

WIPH0

WIPL0

0.8 V

WIPH1

WIPL1

0.8 V

WIPH2

WIPL2

0.8 V

Data Sheet U12255EJ2V0DS00

Reset input timing

PD784927, 784928, 784927Y, 784928Y

WRSL

RESET

Clock output timing

CLO

0.8 V

CLH

CYCL

CLF

CLL

CLR

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

7. PACKAGE DRAWING

100 PIN PLASTIC LQFP (FINE PITCH) (14×14)

A B

75 51

detail of lead end

100

NOTE

Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS INCHES

A 16.00±0.20 0.630±0.008

+0.009

B 14.00±0.20 0.551

C 14.00±0.20 0.551 D 16.00±0.20 0.630±0.008

F 1.00 0.039

G 1.00 0.039

+7° –3°

+0.05 –0.04

+0.03 –0.07

H 0.22 0.009±0.002

I 0.08 0.003

J 0.50 (T.P.) 0.020 (T.P.) K 1.00±0.20 0.039

L 0.50±0.20 0.020

M 0.17 0.007

N 0.08 0.003 P 1.40±0.05 0.055±0.002

Q 0.10±0.05 0.004±0.002

R3° 3° S 1.60 MAX. 0.063 MAX.

+0.009 –0.008

–0.008 +0.009

–0.008

+0.009 –0.008

+0.008 –0.009

+0.001 –0.003

+7° –3°

S100GC-50-8EU

Remark The package dimensions and materials of ES versions are the same as those of mass-production

versions.

Data Sheet U12255EJ2V0DS00

100PIN PLASTIC QFP (14x20)

PD784927, 784928, 784927Y, 784928Y

A B

100

NOTE

Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.

detail of lead end

ITEM MILLIMETERS INCHES

A 23.6±0.4 0.929±0.016

B 20.0±0.2 0.795

C 14.0±0.2 0.551

D 17.6±0.4 0.693±0.016 F 0.8 0.031

G 0.6 0.024

H 0.30±0.10 0.012

I 0.15 0.006

J 0.65 (T.P.) 0.026 (T.P.)

K 1.8±0.2 0.071

L 0.8±0.2 0.031

M 0.15 0.006

N 0.10 0.004 P 2.7±0.1 0.106

Q 0.1±0.1 0.004±0.004

R5°±5° 5°±5° S 3.0 MAX. 0.119 MAX.

+0.10 –0.05

P100GF-65-3BA1-3

+0.009 –0.008

+0.004 –0.005

+0.008 –0.009

+0.009 –0.008

+0.004 –0.003

+0.005 –0.004

Remark The package dimensions and materials of ES versions are the same as those of mass-production

versions.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

8. RECOMMENDED SOLDERING CONDITIONS

Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended, consult NEC.

Caution

PD784927GF-×××-3BA : 100-pin plastic QFP (14 × 20 mm)

PD784928GF-×××-3BA : 100-pin plastic QFP (14 × 20 mm)

PD784927YGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)

PD784928YGF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)

Soldering Method Soldering Conditions Recommended

Infrared reflow Package peak temperature: 235°C, Time: 30 secs. max. (210°C min.), IR35-00-3

VPS Package peak temperature: 215°C, Time: 40 secs. max. (200°C min.), VP15-00-3

Wave soldering Solder bath temperature: 260°C max., Time: 10 secs. max., WS60-00-1

Partial heating Pin temperature: 300°C max., Time: three secs. max. (per device side) —

PD784927GC-×××-8EU, 784927YGC-×××-8EU, 784928GC-×××-8EU, and 784928YGC-×××-8EU are

under development. Therefore their soldering conditions are not defined.

Table 8-1. Surface Mount Type Soldering Conditions

Conditions Symbol

Number of times: three times max.

Number of times: once, Preheating temperature: 120°C max.(Package surface temperature)

Caution Do not use two or more soldering methods in combination (except partial heating).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for developing systems using the µPD784927. Refer to (5) Cautions when the development tools are used.

(1) Language processing software

RA78K4 78K/IV series common assembler package CC78K4 78K/IV series common C compiler package DF784928 Device file for the µPD784928, 784928Y subseries CC78K4-L 78K/IV series common C compiler library source file

(2) Flash memory writing tools

Flashpro II, III Dedicated flash programmer (Part number: FL-PR2, FL-PR3, PG-FPIII)

FA-100GC Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Be sure to

connect depending on the target product.

FA-100GF Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Be sure to

connect depending on the target product.

(3) Debugging tools

• When using the IE-78K4-NS in-circuit emulator

IE-78K4-NS 78K/IV series common in-circuit emulator IE-70000-MC-PS-B Power supply unit for IE-78K4-NS IE-70000-98-IF-C Interface adapter necessary when a PC-9800 series computer (except notebook

personal computer) is used as host machine (C bus compatible)

IE-70000-CD-IF-A PC card and interface cable necessary when a notebook personal computer is used as

host machine (PCMCIA socket compatible)

IE-70000-PC-IF-C Interface adapter necessary when an IBM PC/ATTM compatible machine is used as host

machine (ISA bus compatible) IE-784928-NS-EM1 Emulation board for emulating the µPD784928, 784928Y subseries EP-784915-GF-R Emulation probe for µPD784915 subseries common 100-pin plastic QFP (GC-3BA type)

and 100-pin plastic LQFP (GC-8EU type). EV-9200GF-100 Conversion socket to be mounted on the board of the target system for 100-pin plastic

QFP (GF-3BA type). It is used in LCC system. NQPACK100RB Conversion socket to be mounted on the board of the target system for 100-pin plastic

QFP (GF-3BA type). It is used in QFP system. ID78K4-NS Integrated debugger for IE-78K4-NS SM78K4 78K/IV series common system simulator DF784928 Device file for the µPD784928, 784928Y subseries

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

• When using the IE-784000-R in-circuit emulator

IE-784000-R 78K/IV series common in-circuit emulator IE-70000-98-IF-C Interface adapter necessary when a PC-9800 series computer (except notebook

personal computer) is used as host machine (C bus compatible)

IE-70000-PC-IF-C Interface adapter necessary when an IBM PC/AT compatible machine is used

as host machine (ISA bus compatible) IE-78000-R-SV3 Interface adapter and cable necessary when an EWS is used as host machine IE-784928-NS-EM1 Emulation board for emulating the µPD784928, 784928Y subseries and µPD784915

IE-784915-R-EM1 subseries IE-784000-R-EM 78K/IV series common emulation board IE-78K4-R-EX3 Conversion board for 100-pin products necessary when the IE-784928-NS-EM1 is used

in the IE-784000-R. Not necessary when the IE-784915-R-EM1 is used. EP-784915-GF-R Emulation probe for µPD784915 subseries common 100-pin plastic QFP (GC-3BA type)

and 100-pin plastic LQFP (GC-8EU type). EV-9200GF-100 Conversion socket to be mounted on the board of the target system for 100-pin plastic

QFP (GF-3BA type). It is used in LCC system. NQPACK100RB Conversion socket to be mounted on the board of the target system for 100-pin plastic

QFP (GF-3BA type). It is used in QFP system. ID78K4 Integrated debugger for IE-784000-R SM78K4 78K/IV series common system simulator DF784928 Device file for the µPD784928, 784928Y subseries

(4) Real-time OS

RX78K/IV Real-time OS for 78K/IV series MX78K4 OS for 78K/IV series

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

(5) Cautions when the development tools are used

• The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784928.

• The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784928.

• FL-PR2, FL-PR3, FA-100GC, and FA-100GF are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: 044822-3813). Contact an NEC distributor when purchasing these products.

• NQPACK100RB is a product of Tokyo Eletech Corp. Reference: Daimaru Kogyo, Ltd. Electronics Dept. (TEL: Tokyo 03-3820-7112)

Electronics 2nd Dept. (TEL: Osaka 06-6244-6672)

• Host machines and OSs compatible with the software are as follows:

Host Machine [OS] PC EWS

PC-9800 Series [WindowsTM] HP9000 series 700TM [HP-UXTM] IBM PC/AT compatible machines SPARCstationTM [SunOSTM, SolarisTM]

Software [Japanese/English Windows] NEWSTM (RISC) [NEWS-OSTM] RA78K4 CC78K4 ID78K4-NS – ID78K4 SM78K4 – RX78K/IV MX78K4

Note

Note DOS based software

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

APPENDIX B. RELATED DOCUMENTS

Device-related documents

Document Document No.

Japanese English

PD784928, 784928Y Subseries User’s Manual - Hardware U12648J U12648E

PD784927, 784928, 784927Y, 784928Y Data Sheet U12255J This document

PD784928 Subseries Special Function Register Table U12798J –

PD78F4928 Preliminary Product Information U12188J U12188E

PD784928Y Subseries Special Function Register Table U12719J –

PD78F4928Y Preliminary Product Information U12271J U12271E

PD784915, 784928, 784928Y Subseries Application Note - VCR Servo 78K/IV Series User’s Manual - Instruction U10905J U10905E 78K/IV Series Instruction Table U10594J – 78K/IV Series Instruction Set U10595J – 78K/IV Series Application Note - Software Basics U10095J U10095E

U11361J U11361E

Development tool-related documents (User’s Manuals)

Document Document No.

Japanese English

RA78K4 Assembler Package Operation U11334J U11334E

Language U11162J U11162E RA78K4 Structured Assembler Preprocessor U11743J U11743E CC78K4 C Compiler Operation U11572J U11572E

Language U11571J U11571E IE-78K4-NS U13356J U13356E IE-784000-R U12903J EEU-1534 IE-784928-NS-EM1 U13819J U13819E IE-784915-R-EM1, EP-784915GF-R U10931J U10931E SM78K4 System Simulator Windows Based SM78K Series System Simulator External Part User Open U10092J U10092E

ID78K4-NS Integrated Debugger Reference U12796J U12796E ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger Reference U11960J U11960E

HP-UX, SunOS, NEWS-OS Based

Reference U10093J U10093E

Interface Specifications

Reference U10440J U10440E

Caution The contents of the above related documents are subject to change without notice. Be sure to use

the latest edition of the document when designing your system.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Embedded software-related documents (User’s Manual)

Document Document No.

Japanese English

78K/IV Series Real-Time OS Fundamental U10603J U10603E

Installation U10604J U10604E Debugger U10364J –

78K/IV Series OS, MX78K4 Fundamental U11779J –

NEC PD784927, PD784928, PD784927Y, PD784928Y DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual