NEC PD784927, PD784928, PD784927Y, PD784928Y DATA SHEET

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PD784927, 784928, 784927Y, 784928Y

DESCRIPTION

The µPD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a high-

speed, high-performance 16-bit CPU for VCR software servo control.

PD784927Y and 784928Y are based on the µPD784928 with the addition of an I2C bus interface compatible

The

with multi-master.

They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer

unit) for software servo control and VCR analog circuits.

Flash memory models, the

DATA SHEET

MOS INTEGRATED CIRCUIT

16-BIT SINGLE-CHIP MICROCONTROLLER

PD78F4928 and µPD78F4928Y, are under development.

The functions of the

manual before designing your system.

PD784928, 784928Y Subseries User’s Manual - Hardware : U12648E

78K/IV Series User’s Manual - Instruction : U10905E

FEATURES

High instruction execution speed realized by 16-bit CPU core

•

• Minimum instruction execution time: 250 ns (with 8 MHz internal clock) High internal memory capacity

•

Item Internal ROM capacity 96K bytes 128K bytes

Internal RAM capacity 2048 bytes 3584 bytes

VCR analog circuits conforming to VHS Standard

•

• CTL amplifier • DFG amplifier • Reel FG comparator (2 channels)

• RECCTL driver (rewritable) • DPG amplifier • CSYNC comparator

• CFG amplifier • DPFG separation circuit (ternary separation circuit) Timer unit (super timer unit) for servo control

•

Serial interface : 3 channels

•

3-wire serial I/O : 2 channels

•

I2C bus interface : 1 channel

•

A/D converter: 12 channels (conversion time: 10 µs)

•

Low-frequency oscillation mode: main system clock frequency = internal clock frequency

•

Low-power consumption mode: CPU can operate with a subsystem clock.

•

Supply voltage range: VDD = +2.7 to 5.5 V

•

Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current consumption

•

PD784927 is described in detail in the following User’s Manual. Be sure to read this

Part Number

PD784927, 784927YµPD784928, 784928Y

Unless otherwise specified, the

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U12255EJ2V0DS00 (2nd edition) Date Published December 1999 N CP(K) Printed in Japan

PD784927 is treated as the representative model throughout this document.

The mark shows major revised points.

1997,1999

APPLICATION FIELDS

Stationary VCR, video camera, In-TV VCR

ORDERING INFORMATION

(1)µPD784928 subseries

Part Number Package

PD784927GC-×××-8EU

PD784927GF-×××-3BA 100-pin plastic QFP (14 × 20 mm)

PD784928GC-×××-8EU

PD784928GF-×××-3BA 100-pin plastic QFP (14 × 20 mm)

PD784928Y subseries

(2)

Part Number Package

PD784927YGC-×××-8EU

PD784927YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)

PD784928YGC-×××-8EU

PD784928YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)

Note

PD784927, 784928, 784927Y, 784928Y

100-pin plastic LQFP (fine pitch) (14 × 14 mm)

Note Under development

Remark ××× indicates ROM code suffix.

PRODUCT DEVELOPMENT OF VCR-SERVO MICROCONTROLLERS

The product development of VCR-servo microcontrollers is shown below. Enclosed in a frame are subseries

names.

The Y subseries is a collection of products supporting the I

Products under mass production

Products under development

78K/IV series

78K/I series

PD784928

PD784915

PD78148

PD784928Y

C bus.

100-pin QFP. With flash memory. Expanded internal memory capacity. More powerful analog amplifier. Improved VCR functions. Increased I/O. High-current port added.

C function added (Y model only).

I 100-pin QFP.

Expanded internal memory capacity. Internal analog amplifier. Reinforced super timer. Low-power consumption mode added.

100-pin QFP Expanded internal RAM capacity. Operational amplifier, watch function, multiplier added.

PD78138

Data Sheet U12255EJ2V0DS00

80-pin QFP

FUNCTION LIST (1/2)

Part Number

Item Internal ROM capacity Internal RAM capacity Operating clock

Minimum instruction execution time

I/O port

Real-time output port

Timer/counter

Capture register

Super timer unit

VCR special circuit

General-purpose timer

PWM output

Serial interface

A/D converter

PD784927, 784928, 784927Y, 784928Y

PD784927, 784927Y

96K bytes 128K bytes 2048 bytes 3584 bytes 16 MHz (internal clock: 8 MHz)

Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz) Low power consumption mode : 32.768 kHz (subsystem clock)

250 ns (with 8 MHz internal clock)

input : 20

I/O : 54 (including 8 ports for LED direct drive)

11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation)

Timer/counter Compare register Capture register Remark

TM0 (16 bits) 3 — TM1 (16 bits) 3 1 FRC (22 bits) — 6 TM3 (16 bits) 2 1

UDC (5 bits) 1 —

EC (8 bits) 4 — For HSW signal generation

EDV (8 bits) 1 — For CFG signal division

Input signal Number of bits Measurable cycle Operating edge

CFG 22 125 ns to 524 ms ↑↓

DFG 22 125 ns to 524 ms ↑ HSW 16 1 µs to 65.5 ms ↑↓ VSYNC 22 125 ns to 524 ms ↑

CTL 16 1 µs to 65.5 ms ↑↓ TREEL 22 125 ns to 524 ms ↑↓ SREEL 22 125 ns to 524 ms ↑↓

•VSYNC separation circuit, HSYNC separation circuit

• VISS detection, wide aspect detection circuits

• Field identification circuit

• Head amplifier switch/chrominance rotation output circuit

Timer Compare register Capture register TM2 (16 bits) 1 — TM4 (16 bits) 1 (capture/compare) 1 TM5 (16 bits) 1 —

• 16-bit resolution : 3 channels (carrier frequency: 62.5 kHz)

• 8-bit resolution : 3 channels (carrier frequency: 62.5 kHz)

3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel)

• I2C bus interface: 1 channel (µPD784928Y subseries only) 8-bit resolution × 12 channels, conversion time: 10 µs

PD784928, 784928Y

Data Sheet U12255EJ2V0DS00

FUNCTION LIST (2/2)

PD784927, 784928, 784927Y, 784928Y

Part Number

Item Analog circuit

Interrupt sources

External Internal

Standby function

Watch function Buzzer output function

Supply voltage Package

Note Under development

PD784927, 784927Y

• CTL amplifier

• RECCTL driver (rewritable)

• DFG amplifier, DPG amplifier, CFG amplifier

• DPFG separation circuit (ternary separation circuit)

• Reel FG comparator (2 channels)

• CSYNC comparator

4 levels (programmable), vectored interrupt, macro service, context switching 9 (including NMI) 22 (including software interrupt) 23 (including software interrupt) HALT mode/STOP mode/low power consumption mode/low power consumption HALT mode STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/

INTP2/KEY0-KEY4 pins

0.5-second measurement, low-voltage operation (VDD = 2.7 V)

1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (Internal clock: 8 MHz)

2.048 kHz, 4.096 kHz, 32.768 kHz (Subsystem clock: 32.768 kHz) VDD = +2.7 to 5.5 V

• 100-pin plastic LQFP (fine pitch)(14 × 14 mm)

• 100-pin plastic QFP (14 × 20 mm)

Note

PD784928, 784928Y

Data Sheet U12255EJ2V0DS00

PIN CONFIGURATION (Top View)

• 100-pin plastic LQFP (fine pitch)(14 × 14 mm)

PD784927GC-×××-8EU

PD784928YGC-×××-8EU, 784928YGC-×××-8EU

P84/PWM2/SDA

P83/ROTC

P82/HASW

Note 2

P80 P57 P56 P55 P54 P53 P52 P51 P50

V P47 P46 P45 P44 P43 P42 P41 P40 P07 P06 P05

1 2 3 4 5 6 7 8 9 10 11 12

SS DD

13 14 15 16 17 18 19 20 21 22 23 24 25

Note 1

, 784928GC-×××-8EU

Note 2

P85/PWM3/SCL

P86/PTO10

P87/PTO11

P30/PTO00

P31/PTO01

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

P32/PTO02ICRESETX1X2

PD784927, 784928, 784927Y, 784928Y

Note 1

VSSXT2

XT1

VDDP33/SI2/BUSY

P34/SO2

P35/SCK2

P36/PWM1

P37/PWM0

P63/SI1

P62/SO1

P61/SCK1/BUZ

P60/STRB/CLO

P67/PWM5/CTLMON

P66/PWM4/CFGMON

80 79 78 77 76

46 47 48 49 50

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P65/HWIN/DPGMON P64/BUZ/DFGMON P103/CSYNCIN P102/REEL0IN/INTP3 P101/REEL1IN DFGIN P100/DPGIN CFGCPIN CFGAMP0 CFGIN AV

DD1

SS1

VREFC CTLOUT2 CTLOUT1 CTLIN RECCTL− RECCTL+ CTLDLY AV

SS2

P113/ANI11 P112/ANI10 P111/ANI9 P110/ANI8 P77/ANI7

DD2AVREF

P04

P03

P02

P01

P00

P23/INTP2

P20/NMI

P22/INTP1

P21/INTP0

P90/ENV

P91/KEY0

P92/KEY1

P93/KEY2

P96

P94/KEY3

P95/KEY4

Notes 1. Under development

2. Pins SCL and SDA are provided for the µPD784928Y subseries only.

Caution Directly connect the IC (Internally Connected) pins to V

Data Sheet U12255EJ2V0DS00

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

SS in the normal operation mode.

• 100-pin plastic QFP (14 × 20 mm)

PD784927GF-×××-3BA, 784928GF-×××-3BA,

PD784927YGF-×××-3BA, 784928YGF-×××-3BA

CSYNCIN/P103

REEL0IN/INTP3/P102

REEL1IN/P101

100

DFGMON/P64/BUZ

DPGMON/P65/HWIN

CFGMON/P66/PWM4

CTLMON/P67/PWM5

P60/STRB/CLO

P61/SCK1/BUZ

P62/SO1

P63/SI1 P37/PWM0 P36/PWM1

P35/SCK2

P34/SO2

P33/SI2/BUSY

XT1 XT2

RESET

P32/PTO02 P31/PTO01 P30/PTO00 P87/PTO11 P86/PTO10

Note

/P85/PWM3

SCL

Note

/P84/PWM2

SDA

P83/ROTC

P82/HASW

1 2 3 4 5 6 7 8 9 10 11 12 13

15 16

19 20

21 22 23 24 25 26 27 28 29 30

3132333435363738 39 40 41 42 43 44 45 46 47 48 49 50

DFGIN96DPGIN/P100

CFGCPIN

CFGAMPO

PD784927, 784928, 784927Y, 784928Y

DD1

CFGIN92AV

SS1

VREFC89CTLOUT2

CTLOUT1

CTLIN86RECCTL

RECCTL+

CTLDLY83AV

SS2

ANI11/P113

ANI10/P112

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

ANI9/P111 ANI8/P110 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0

REF

AV AV

DD2

P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI/P20 INTP0/P21 INTP1/P22 INTP2/23 P00 P01 P02 P03 P04 P05 P06

P80

P57

P56

P55

Note Pins SCL and SDA are provided for the

P54

P53

P52

PD784928Y subseries only.

P51

P50

P47

Caution Directly connect the IC (Internally Connected) pins to V

Data Sheet U12255EJ2V0DS00

P46

P45

P44

P43

SS.

P42

P41

P40

P07

PD784927, 784928, 784927Y, 784928Y

ANI0-ANI11 : Analog Input AVDD1, AVDD2 : Analog Power Supply AV

SS1, AVSS2 : Analog Ground

AVREF : Analog Reference Voltage BUSY : Serial Busy BUZ : Buzzer Output CFGAMPO : Capstan FG Amplifier Output CFGCPIN : Capstan FG Capacitor Input CFGIN : Analog Unit Input CFGMON : Capstan FG Monitor CLO : Clock Output CSYNCIN : Analog Unit Input CTLDLY : Control Delay Input CTLIN : CTL Amplifier Input Capacitor CTLMON : CTL Amplifier Monitor CTLOUT1, CTLOUT2 : CTL Amplifier Output DFGIN : Analog Unit Input DFGMON : DFG Monitor DPGIN : Analog Unit Input DPGMON : DPG Monitor ENV : Envelope Input HASW : Head Amplifier Switch Output HWIN : Hardware Timer External Input IC : Internally Connected INTP0-INTP3 : Interrupt From Peripherals KEY0-KEY4 : Key Return NMI : Nonmaskable Interrupt P00-P07 : Port0

P20-P23 : Port2 P30-P37 : Port3 P40-P47 : Port4 P50-P57 : Port5 P60-P67 : Port6 P70-P77 : Port7 P80, P82-P87 : Port8 P90-P96 : Port9 P100-P103 : Port10 P110-P113 : Port11 PTO00-PTO02, PTO10, PTO11 : Programmable Timer Output PWM0-PWM5 : Pulse Width Modulation Output RECCTL+, RECCTL– : RECCTL Output/PBCLT Input REEL0IN, REEL1IN : Analog Unit Input RESET : Reset ROTC : Chrominance Rotate Output SCK1, SCK2 : Serial Clock

Note

SCL SDA

Note

: Serial Clock

: Serial Data SI1, SI2 : Serial Input SO1, SO2 : Serial Output STRB : Serial Strobe V

DD : Power Supply

VREFC : Reference Amplifier Capacitor V

SS : Ground

X1, X2 : Crystal (Main System Clock) XT1, XT2 : Crystal (Subsystem Clock)

Note Pins SCL and SDA are provided for the

Data Sheet U12255EJ2V0DS00

PD784928Y subseries only.

INTERNAL BLOCK DIAGRAM

PD784927, 784928, 784927Y, 784928Y

NMI

INTP0-INTP3

PWM0-PWM5

PTO00-PTO02

PTO10, PTO11

VREFC REEL0IN REEL1IN

CSYNCIN

DFGIN DPGIN CFGIN

CFGAMPO

CFGCPIN CTLOUT1 CTLOUT2

CTLIN

RECCTL+

RECCTL

CTLDLY

DFGMON

DPGMON

CFGMON

CTLMON

DD1

, AV

DD2

SS1

, AV

REF

AN10-AN11

SI1

SO1

SCK1

SI2/BUSY

SO2

SCK2

STRB

SUPER TIMER

ANALOG UNIT

A/D CONVERTER

SS2

INTERFACE 1

INTERFACE 2

INTERRUPT

CONTROL

UNIT

SERIAL

78K/IV

16-BIT CPU CORE

(RAM: 512 bytes)

RAM

ROM

SYSTEM

CONTROL

CLOCK OUTPUT

BUZZER OUTPUT

KEY INPUT

REAL-TIME

OUTPUT PORT

PORT0 P00-P07

PORT2 P20-P23

PORT3 P30-P37

PORT4 P40-P47

PORT5 P50-P57

PORT6 P60-P67

PORT7 P70-P77

PORT8 P80, P82-P87

PORT9 P90-P96

X1 X2 XT1 XT2 RESET

CLO

BUZ

KEY0-KEY4

P00-P07

P80, P82, P83

SDA

SCL

SERIAL

INTERFACE 3

Note

Note Only the µPD784928 subseries supports I2C bus interface.

Remark Internal ROM and RAM capacities differ depending on the product.

Data Sheet U12255EJ2V0DS00

PORT10 P100-P103

PORT11 P110-P113

SYSTEM CONFIGURATION EXAMPLE

• Video camera

DFG

DPG

Drum motor M

Capstan motor M

CTL head

Loading motor M

Driver

CFG

Driver

PD784927, 784928, 784927Y, 784928Y

PD784927

DFGIN DPGIN

PWM0

CFGIN

PWM1

RECCTL+

RECCTL

PWM2

PORT

SCK1

SI1

SO1

INTP0

PORT

SCK2

SO2

BUSY

Key matrix

INTP0

Camera-

SCK

controlling

microcontroller

PD784038

PORT

Camera block

CS CLK

DATA BUSY

LCD C/D PD7225

Audio/video

signal

processing

circuit

Remote controller signal

Composite sync signal Video head switch Audio head switch Pseudo vertical sync signal

Remote controller reception signal

PC2800A

PORT CSYNCIN

PTO00 PTO01 P80

INTP2

XT1 XT2X1 X2

16 MHz 32.768 kHz

PORT

STRB

PORT

SDA

SCL

Note

+VDD

CS CLK DATA BUSY STB

SDA SCL

LCD display panel

OSD

PD6461

Mechanical block

EEPROM

Other ICs

Note Pins SCL and SDA are provided for the

Data Sheet U12255EJ2V0DS00

PD784928Y subseries only.

• Stationary VCR

Drum motor M

Capstan motor M

CTL head

Loading motor M

Reel motor

PD784927, 784928, 784927Y, 784928Y

PD784927

DFG

DFGIN DPGIN

DPG

Driver

Reel FG0

Driver

Reel FG1

CFG

PWM0

CFGIN

PWM1

RECCTL+

RECCTL

PWM2

REEL0IN

PWM3

PWM4

REEL1IN

PORT

SCK1

SI1

SO1

PORT

SCK2

SO2

PORT

CSYNCIN

PTO00 PTO01

P80

PWM5

PORT

INTP2

Note

SDA

Note

SCL

STB CLK DOUT DIN

FIP

CS CLK

DATA

Composite sync signal Video head switch Audio head switch Pseudo vertical sync signal

Remote controller reception signal

EEPROM

SDA SCL

C/D

FIP

PD16311

Key matrix

OSD PD6464A

Audio/video signal

processing circuit

Tuner

Mechanical block

PC2800A

Remote controller signal

Low frequency oscillation mode

Note Pins SCL and SDA are provided for the

XT1 XT2X1 X2

8 MHz 32.768 kHz

PD784928Y subseries only.

Data Sheet U12255EJ2V0DS00

Other ICs

SDA SCL

PD784927, 784928, 784927Y, 784928Y

CONTENTS

1. DIFFERENCE BETWEEN µPD784928 SUBSERIES AND 784928Y SUBSERIES .................... 12

2. PIN FUNCTION ............................................................................................................................... 13

2.1 Port Pins................................................................................................................................................ 13

2.2 Pins Other Than Port Pins .................................................................................................................. 14

2.3 I/O Circuits of Pins and Processing of Unused Pins...................................................................... 1 6

3. INTERNAL BLOCK FUNCTION ..................................................................................................... 19

3.1 CPU Registers ...................................................................................................................................... 19

3.1.1 General-purpose registers ......................................................................................................... 19

3.1.2 Other CPU registers................................................................................................................... 20

3.2 Memory Space ...................................................................................................................................... 2 1

3.3 Special Function Registers (SFRs) ................................................................................................... 2 4

3.4 Ports....................................................................................................................................................... 3 0

3.5 Real-Time Output Port......................................................................................................................... 31

3.6 Super Timer Unit .................................................................................................................................. 35

3.7 Serial Interface ..................................................................................................................................... 4 1

3.8 A/D Converter ....................................................................................................................................... 44

3.9 VCR Analog Circuits............................................................................................................................ 45

3.10 Watch Function .................................................................................................................................... 50

3.11 Clock Output Function ........................................................................................................................ 51

3.12 Buzzer Output Function ...................................................................................................................... 5 2

4. INTERNAL/EXTERNAL CONTROL FUNCTION ........................................................................... 53

4.1 Interrupt Function ................................................................................................................................53

4.1.1 Vectored interrupt....................................................................................................................... 56

4.1.2 Context switching ....................................................................................................................... 56

4.1.3 Macro service ............................................................................................................................. 57

4.1.4 Application example of macro service ...................................................................................... 59

4.2 Standby Function................................................................................................................................. 62

4.3 Clock Generation Circuit ..................................................................................................................... 64

4.4 Reset Function ..................................................................................................................................... 65

5. INSTRUCTION SET ........................................................................................................................ 66

6. ELECTRICAL SPECIFICATIONS .................................................................................................. 70

7. PACKAGE DRAWING .................................................................................................................... 85

8. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 87

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 88

APPENDIX B. RELATED DOCUMENTS ............................................................................................ 91

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

1. DIFFERENCE BETWEEN µPD784928 SUBSERIES AND 784928Y SUBSERIES

The µPD78F4928 and 78F4928Y are based on the µPD784927 and 784927Y and are provided with a 128K-byte

flash memory instead of a mask ROM.

Table 1-1 shows the differences between the products in the µPD784928 subseries and 784928Y subseries.

Table 1-1. Differences between

PD784928 Subseries and 784928Y Subseries

Part Number

Item Internal ROM Mask ROM Flash memory

Internal RAM 2048 bytes 3584 bytes Internal memory capacity Not provided Provided

select register (IMS) IC pin Provided Not provided VPP pin Not provided Provided Electrical characteristics Refer to the Data Sheet of each product.

PD784927,

PD784927Y

96K bytes 128K bytes

PD784928,

PD784928Y

PD78F4928,

PD78F4928Y

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

2. PIN FUNCTION

2.1 Port Pins

Pin Name I/O Shared with: Function

P00-P07 I/O Real-time 8-bit I/O port (port 0).

output port • Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors. P20 Input NMI 4-bit I/O port (port 2). P21-P23 INTP0-INTP2 • Can be connected with software pull-up resistors (P22 and P23 only). P30-P32 I/O PTO00-PTO02 8-bit I/O port (port 3). P33 SI2/BUSY • Can be set in input or output mode in 1-bit units. P34 SO2 • Can be connected with software pull-up resistors. P35 SCK2 P36, P37 PWM1, PWM0 P40-P47 I/O — 8-bit I/O port (port 4).

• Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors.

• Can directly drive LED.

P50-P57 I/O — 8-bit I/O port (port 5).

• Can be set in input or output mode in 1-bit units.

• Can be connected with software pull-up resistors.

P60 I/O STRB/CLO 8-bit I/O port (port 6). P61 SCK1/BUZ • Can be set in input or output mode in 1-bit units. P62 SO1 • Can be connected with software pull-up resistors. P63 SI1 P64 DFGMON/BUZ P65 DPGMON/HWIN P66 CFGMON/PWM4 P67 CTLMON/PWM5 P70-P77 Input ANI0-ANI7 8-bit input port (port 7) P80 I/O Real-time Pseudo VSYNC output 7-bit I/O port (port 8). P82 output port HASW output • Can be set in input or output mode P83 ROTC output in 1-bit units. P84 PWM2/SDA P85 PWM3/SCL P86 PTO10 P87 PTO11 P90 I/O ENV 7-bit I/O port (port 9). P91-P95 KEY0-KEY4 • Can be set in input or output mode in 1-bit units. P96 — • Can be connected with software pull-up resistors. P100 Input DPGIN 4-bit input port (port 10). P101 REEL1IN P102 REEL0IN/INTP3 P103 CSYNCIN P110-P113 Input ANI8-ANI11 4-bit input port (port 11).

Note

• Can be connected with software pull-up resistors.

Note Pins SCL and SDA are provided for the µPD784928Y subseries only.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

2.2 Pins Other Than Port Pins (1/2)

Pin Name I/O Shared with: Function REEL0IN Input P102/INTP3 Reel FG input REEL1IN P101 DFGIN — Drum FG, PFG input (ternary) DPGIN P100 Drum PG input CFGIN — Capstan FG input CSYNCIN P103 Composite SYNC input CFGCPIN — CFG comparator input CFGAMPO Output — CFG amplifier output PTO00 Output P30 Programmable timer output of super timer unit PTO01 P31 PTO02 P32 PTO10 P86 PTO11 P87 PWM0 Output P37 PWM output of super timer unit PWM1 P36 PWM2 P84/SDA PWM3 P85/SCL PWM4 P66/CFGMON PWM5 P67/CTLMON HASW Output P82 Head amplifier switch signal output ROTC Output P83 Chrominance rotation signal output ENV Input P90 Envelope signal input SI1 Input P63 Serial data input (serial interface channel 1) SO1 Output P62 Serial data output (serial interface channel 1) SCK1 I/O P61/BUZ Serial clock I/O (serial interface channel 1) SI2 Input P33/BUSY Serial data input (serial interface channel 2) SO2 Output P34 Serial data output (serial interface channel 2) SCK2 I/O P35 Serial clock I/O (serial interface channel 2) BUSY Input P33/SI2 Serial busy signal input (serial interface channel 2) STRB Output P60/CLO Serial strobe signal output (serial interface channel 2) SDA I/O P84/PWM2 I2C bus data I/O SCL I/O P85/PWM3 I2C bus clock I/O ANI0-ANI7 Analog input P70-P77 Analog signal input of A/D converter ANI8-ANI11 P110-P113 CTLIN — — CTL amplifier input capacitor connection CTLOUT1 Output — CTL amplifier output CTLOUT2 I/O — Logic signal input/CTL amplifier output RECCTL+, RECCTL– I/O — RECCTL signal output/PBCTL signal input CTLDLY — — External time constant connection (for RECCTL rewriting)

Note

Note Pins SCL and SDA are provided for the µPD784928Y subseries only.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

2.2 Pins Other Than Port Pins (2/2)

Pin Name I/O Shared with: Function VREFC — — VREF amplifier AC connection DFGMON Output P64/BUZ Drum FG signal output DPGMON P65/HWIN Drum PG signal output CFGMON P66/PWM4 CFG signal output CTLMON P67/PWM5 CTL signal output NMI Input P20 Non-maskable interrupt request input INTP0-INTP2 Input P21-P23 External interrupt request input INTP3 Input P102/REEL0IN KEY0-KEY4 Input P91-P95 Key input signal input CLO Output P60/STRB Clock output BUZ Output P61/SCK1 Buzzer output

P64/DFGMON HWIN Input P65/DPGMON External input of hardware watch counter RESET Input — Reset input X1 Input — Crystal connection for main system clock oscillation X2 — XT1 Input — Crystal connection for subsystem clock oscillation. XT2 — Crystal connection for watch clock oscillation AVDD1 — — Positive power supply to analog amplifier circuit AVDD2 — — Positive power supply to A/D converter and analog circuits input buffer AVSS1 — — GND of analog amplifier circuit AVSS2 — — GND of A/D converter and analog circuits input buffer AVREF — — Reference voltage input to A/D converter VDD — — Positive power supply to digital circuits VSS — — GND of digital circuits IC — — Internally connected. Directly connect this pin to VSS.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

2.3 I/O Circuits of Pins and Processing of Unused Pins

Table 2-1 shows the types of the I/O circuits of the respective pins and processing of the unused pins. Figure

2-1 shows the circuits of the respective types.

Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (1/2)

Pin I/O Circuit Type I/O Recommended Connection of Unused Pins

P00-P07 5-A I/O Input: Connect to VDD.

Output: Leave unconnected. P20/NMI 2 Input Connect to VDD. P21/INTP0 Connect to VDD or VSS. P22/INTP1, P23/INTP2 2-A Connect to VDD. P30/PTO00-P32/PTO02 5-A I/O Input: Connect to VDD. P33/SI2/BUSY 8-A Output: Leave unconnected. P34/SO2 5-A P35/SCK2 8-A P36/PWM1, P37/PWM0 5-A P40-P47 P50-P57 P60/STRB/CLO P61/SCK1/BUZ 8-A P62/SO1 5-A P63/SI1 8-A P64/DFGMON/BUZ 5-A P65/HWIN/DPGMON 8-A P66/PWM4/CFGMON 5-A P67/PWM5/CTLMON P70/ANI0-P77/ANI7 9 Input Connect to VSS. P80 5-A I/O Input: Connect to VDD. P82/HASW Output: Leave unconnected. P83/ROTC P84/PWM2/SDA P85/PWM3/SCL P86/PTO10 5-A P87/PTO11 P90/ENV P91/KEY0-P95/KEY4 8-A P96 5-A

Note

10-A

Note Pins SCL and SDA are provided for the µPD784928Y subseries only.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (2/2)

Pin I/O Circuit Type I/O Recommended Connection of Unused Pins

P100/DPGIN — Input When ENDRUM = 0 or ENDRUM = 1 and

SELPGSEPA = 0: Connect to VSS. P101/REEL1IN When ENREEL = 0: Connect to VSS. P102/REEL0IN/INTP3 P103/CSYNCIN When ENCSYN = 0: Connect to VSS. P110/ANI8-P113/ANI11 9 Input Connect to VSS. RECCTL+, RECCTL– — I/O When ENCTL = 0 and ENREC = 0: Connect to VSS. DFGIN — Input When ENDRUM = 0: Connect to VSS. CFGIN, CFGCPIN When ENCAP = 0: Connect to VSS. CTLOUT1 — Output Leave unconnected. CTLOUT2 — I/O When ENCTL = 0 and ENCOMP = 0: Connect to VSS.

When ENCTL = 1: Leave unconnected. CFGAMPO — Output Leave unconnected. CTLIN — — When ENCTL = 0: Leave unconnected. VREFC CTLDLY Leave unconnected. AVDD1, AVDD2 — — Connect to VDD. AVREF, AVSS1, AVSS2 Connect to VSS. RESET 2 — — XT1 — — Connect to VSS. XT2 Leave unconnected.

When ENCTL = 0 and ENCAP = 0 and ENCOMP = 0: Leave unconnected.

IC Directly connect to VSS.

Remark ENCTL : bit 1 of amplifier control register (AMPC)

ENREC : bit 7 of amplifier mode register 0 (AMPM0) ENDRUM : bit 2 of amplifier control register (AMPC) SELPGSEPA: bit 2 of amplifier mode register 0 (AMPM0) ENCAP : bit 3 of amplifier control register (AMPC) ENCSYN : bit 5 of amplifier control register (AMPC) ENREEL : bit 6 of amplifier control register (AMPC) ENCOMP : bit 4 of amplifier control register (AMPC)

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Figure 2-1. I/O Circuits of Respective Pins

Type 2

Schmitt trigger input with hysteresis characteristics

Type 2-A

P-ch

Pull-up enable

Schmitt trigger input with hysteresis characteristics

Type 5-A

Pull-up

enable

Data

Output

disable

P-ch

N-ch

P-ch

IN/ OUT

Type 8-A

Pull-up

enable

Data

Output

disable

Type 9

Type 10-A

Pull-up Enable

P-ch N-ch

P-ch

N-ch

Comparator

REF

(Threshold voltage)

Input enable

P-ch

IN/ OUT

P-ch

Input

enable

Data

Open drain

Output disable

P-ch

IN/OUT

N-ch

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3. INTERNAL BLOCK FUNCTION

3.1 CPU Registers

3.1.1 General-purpose registers

PD784927 has eight banks of general-purpose registers. One bank consists of sixteen 8-bit general-purpose

The registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. Four of the 16-bit general-purpose registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register.

These eight banks of general-purpose registers can be selected by software or context switching function.

The general-purpose registers, except for the address expansion registers V, U, T, and W, are mapped to the internal RAM.

Figure 3-1. Configuration of General-Purpose Register

A (R1) X (R0)

AX (RP0)

B (R3) C (R2)

BC (RP1)

R5 R4

RP2

R7 R6

RP3

R9 R8V

VP (RP4)

VVP (RG4)

R11 R10U

UP (RP5)

UUP (RG5)

D (R13) E (R12)T

DE (RP6)

TDE (RG6)

H (R15) L (R14)W

HL (RP7)

WHL (RG7)

( ): absolute name

8 banks

Caution Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the RSS bit is planned to be deleted from the future models in the 78K/IV Series.

Data Sheet U12255EJ2V0DS00

3.1.2 Other CPU registers

(1) Program counter

The program counter of the updated as the program is executed.

(2) Program status word

This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the program is executed.

PD784927, 784928, 784927Y, 784928Y

PD784927 is 20 bits wide. The value of the program counter is automatically

19 0

12 11 10 9 8

PSWH UF15RBS214RBS113RBS0

PSW

PSWL S7Z

RSS

5AC4IE3

Note

P/V201CY

Note The RSS flag is provided to maintain compatibility with the microcomputers in the 78K/III Series.

Always clear this flag to 0 except when the software of the 78K/III Series is used.

(3) Stack pointer

This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the high-order 4 bits.

23 0

000200SP

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.2 Memory Space

A memory space of 1M bytes can be accessed. The mapping of the internal data area (special function registers and internal RAM) can be selected by using the LOCATION instruction. The LOCATION instruction must be always executed after reset has been cleared, and cannot be used more than once.

(1) When LOCATION 0H instruction is executed

Part Number Internal Data Area Internal ROM Area

PD784927, 784927Y 0F700H-0FFFFH 00000H-0F6FFH

10000H-17FFFH

PD784928, 784928Y 0F100H-0FFFFH 00000H-0F0FFH

10000H-1FFFFH

Remark The area of the internal ROM overlapping the internal data area cannot be used when the

LOCATION 0 instruction is executed.

Part Number Unusable Area

PD784927, 784927Y 0F700H-0FFFFH (2304 bytes)

PD784928, 784928Y 0F100H-0FFFFH (3840 bytes)

(2) When LOCATION 0FH instruction is executed

Part Number Internal Data Area Internal ROM Area

PD784927, 784927Y FF700H-FFFFFH 00000H-17FFFH

PD784928, 784928Y FF100H-FFFFFH 00000H-1FFFFH

Data Sheet U12255EJ2V0DS00

(256 bytes)

Special function registers (SFRs)

Internal ROM

(63232

bytes)

Internal RAM

(2048 bytes)

Cannot be used

General-purpose registers

(128 bytes)

Macro service control

word area (54 bytes)

Data area (512 bytes)

Program/data area

(1536 bytes)

Note 2

CALLF entry area

(2K bytes)

Program/data area

Note 3

CALLT table area

(64 bytes)

Vector table area

(64 bytes)

Internal RAM

(2048 bytes)

Cannot be used

Internal ROM

(96K bytes)

Note 4

When LOCATION 0H instruction is executed

Note 1

When LOCATION 0FH instruction is executed

Internal ROM

(32768 bytes)

FFFFFH

18000H

17FFFH

10000H

0FFFFH

0FFDFH

0FFD0H

0FF00H

0FEFFH

0F700H

0F6FFH

00000H

0FEFFH

0FE80H

0FE7FH

0FE3BH

0FE06H

0FD00H

0FCFFH

0F700H

17FFFH

10000H

0F6FFH

01000H

00800H

007FFH

00080H

0007FH

00040H

0003FH

00000H 00000H

17FFFH

18000H

FFFFFH

FFFDFH

FFFD0H

FFF00H

FFEFFH

FF6FFH

FF700H

FFEFFH

FFE80H

FFE7FH

FFE3BH

FFE06H

FFD00H

FFCFFH

FF700H

17FFFH

Special function registers (SFRs)

(256 bytes)

Note 4

Note 1

00FFFH

PD784927, 784928, 784927Y, 784928Y

PD784927, 784927Y

Figure 3-2. Memory Map of

2. The 2304 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. When LOCATION 0H instruction is executed: 96000 bytes, when LOCATION 0FH instruction is executed: 98304 bytes

4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.

Notes 1. Accessed in external memory expansion mode

Data Sheet U12255EJ2V0DS00

(256 bytes)

Special function registers (SFRs)

Internal ROM

(61696

bytes)

Internal RAM

(3584 bytes)

Cannot be used

General-purpose registers

(128 bytes)

Macro service control

word area (54 bytes)

Data area (512 bytes)

Program/data area

(3072 bytes)

Note 2

CALLF entry area

(2K bytes)

Program/data area

Note 3

CALLT table area

(64 bytes)

Vector table area

(64 bytes)

Internal RAM

(3584 bytes)

Cannot be used

Internal ROM

(128K bytes)

Note 4

When LOCATION 0H instruction is executed

Note 1

When LOCATION 0FH instruction is executed

Internal ROM

(65536 bytes)

FFFFFH

20000H

1FFFFH

10000H

0FFFFH

0FFDFH

0FFD0H

0FF00H

0FEFFH

0F100H

0F0FFH

00000H

0FEFFH

0FE80H

0FE7FH

0FE3BH

0FE06H

0FD00H

0FCFFH

0F100H

1FFFFH

10000H

0F0FFH

01000H

00800H

007FFH

00080H

0007FH

00040H

0003FH

00000H 00000H

1FFFFH

20000H

FFFFFH

FFFDFH

FFFD0H

FFF00H

FFEFFH

FF0FFH

FF100H

FFEFFH

FFE80H

FFE7FH

FFE3BH

FFE06H

FFD00H

FFCFFH

FF100H

1FFFFH

Special function registers (SFRs)

(256 bytes)

Note 4

Note 1

00FFFH

PD784927, 784928, 784927Y, 784928Y

PD784928, 784928Y

Figure 3-3. Memory Map of

2. The 3840 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. When LOCATION 0H instruction is executed: 127232 bytes, when LOCATION 0FH instruction is executed: 131072 bytes

4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.

Notes 1. Accessed in external memory expansion mode

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

3.3 Special Function Registers (SFRs)

Special function registers are assigned special functions and mapped to a 256-byte space of addresses FF00H through FFFFH. These registers include mode registers and control registers that control the internal peripheral hardware units.

Caution Do not access an address to which no SFR is assigned. If such an address is accessed by

mistake, the

Table 3-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

• Symbol .................................... Abbreviation of an SFR. This abbreviation is reserved for NEC’s assembler

• R/ W ......................................... Indicates whether the SFR in question can be read or written.

PD784927 may be deadlocked. This deadlock can be cleared only by reset input.

(RA78K4). With a C compiler (CC78K4), the abbreviation can be used as sfr variable by the #pragma sfr instruction.

R/W : Read/write R : Read only W : Write only

• Bit length................................. Indicates the bit length (word length) of the SFR.

• Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that

can be manipulated in 16-bit units can be used as the operand sfrp of an instruction. Specify an even address to manipulate this SFR. An SFR that can be manipulated in 1-bit units can be used for a bit manipulation instruction.

• After clearing reset ................. Indicates the status of each register immediately after clearing reset.

Caution The addresses shown in Table 3-1 are used when the LOCATION 0H instruction is executed. Add

“F0000H” to the address values shown in the table when the LOCATION 0FH instruction is executed.

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (1/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FF00H Port 0 P0 R/W 8 — Undefined FF02H Port 2 P2 R 8 — FF03H Port 3 P3 R/W 8 — FF04H Port 4 P4 8 — FF05H Port 5 P5 8 — FF06H Port 6 P6 8 — FF07H Port 7 P7 R 8 — FF08H Port 8 P8 R/W 8 — FF09H Port 9 P9 8 —

FF0AH Port 10 P10 R 8 — FF0BH Port 11 P11 8 — FF0EH Port 0 buffer register L P0L R/W 8 —

FF0FH Port 0 buffer register H P0H 8 — FF10H Timer 0 compare register 0 CR00 16 — — Cleared to 0 FF11H Event counter compare register 0 ECC0 W 8 — — FF12H Timer 0 compare register 1 CR01 R/W 16 — — FF13H Event counter compare register 1 ECC1 W 8 — — FF14H Timer 0 compare register 2 CR02 R/W 16 — — FF15H Event counter compare register 2 ECC2 W 8 — — FF16H Timer 1 compare register 0 CR10 R/W 16 — — FF17H Event counter compare register 3 ECC3 W 8 — — FF18H Timer 1 compare register 1 CR11 R/W 16 — —

FF1AH Timer 1 compare register 2 CR12 R 16 — — FF1CH Timer 1 compare register 3 CR13 R/W 16 — — FF1EH Timer 2 compare register 0 CR20 16 — —

FF20H Port 0 mode register PM0 8 — FFH FF23H Port 3 mode register PM3 8 — FF24H Port 4 mode register PM4 8 — FF25H Port 5 mode register PM5 8 — FF26H Port 6 mode register PM6 8 — FF28H Port 8 mode register PM8 8 — FDH FF29H Port 9 mode register PM9 8 — 7FH

FF2EH Real-time output port 0 control register RTPC 8 — 00H

FF30H Timer counter 0 TM0 R 16 — — Cleared to 0 FF31H Event counter EC R/W 8 — — FF32H Timer counter 1 TM1 R 16 — — FF34H Free running counter (bits 0-15) FRCL 16 — — 0000H FF35H Free running counter (bits 16-21) FRCH 8 — — 00H FF36H Timer counter 2 TM2 16 — — Cleared to 0

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (2/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FF38H Timer control register 0 TMC0 R/W 8 — 00H FF39H Timer control register 1 TMC1 8 — FF3AH Timer control register 2 TMC2 8 — FF3BH Timer control register 3 TMC3 8 —00×00000 FF3CH Timer counter 3 TM3 R 16 — — Cleared to 0 FF3DH Timer control register 4 TMC4 R/W 8 — ××000000 FF3EH Timer counter 4 TM4 R 16 — — Cleared to 0 FF43H Port 3 mode control register PMC3 R/W 8 — 00H FF48H Port 8 mode control register PMC8 8 — FF4BH Control mode select register CMS 8 — FF4DH Trigger source select register 0 TRGS0 8 — FF4EH Pull-up resistor option register L PUOL 8 — FF4FH Pull-up resistor option register H PUOH 8 — FF50H Input control register ICR 8 — 10H FF51H Up/down counter count register UDC 8 — — Undefined FF52H Event divider counter EDV R 8 — — Cleared to 0 FF53H Capture mode register CPTM R/W 8 — 00H FF54H Timer counter 5 TM5 R 16 — — Cleared to 0 FF56H Timer 3 capture register 0 CPT30 16 — — FF58H Timer 0 output mode register TOM0 W 8 — — ××000000 FF59H Timer 0 output control register TOC0 8 — — 00H

ADML

Note 1

R/W 8 — — 80H

Note 2

8 —

FF5AH Timer 1 output mode register TOM1 FF5BH Timer 1 output control register TOC1 W 8 — — 00H FF5CH Timer 3 compare register 0 CR30 R/W 16 — — Cleared to 0 FF5EH Timer 3 compare register 1 CR31 16 — — FF60H Port 8 buffer register L P8L 8 — 000×0×0× FF63H Up/down counter compare register UDCC W 8 — — Undefined FF65H Trigger source select register 1 TRGS1 R/W 8 — 00H FF66H Port 6 mode control register PMC6 8 — FF68H A/D converter mode register ADM 16 — — 0000H

FF6AH A/D conversion result register ADCR R 8 — — Undefined FF6CH Hardware watch counter 0 HW0 R/W 16 — — Not affected FF6EH Hardware watch counter 1 HW1 R 16 — — by reset FF6FH Watch mode register WM R/W 8 —00××0×00 FF70H PWM control register 0 PWMC0 8 — 05H

Notes 1. When the TOM1 is read, the write sequence of the REC driver is read (bits 0 and 1).

2. ADML is the low-order 8 bits of ADM and can be manipulated in 1- or 8-bit units.

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (3/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FF71H PWM control register 1 PWMC1 R/W 8 — 15H FF72H PWM0 modulo register PWM0 16 — — 0000H FF73H PWM2 modulo register PWM2 8 — — 00H FF74H PWM1 modulo register PWM1 16 — — 0000H FF75H PWM3 modulo register PWM3 8 — — 00H FF76H PWM5 modulo register PWM5 16 — — 0000H FF77H PWM4 modulo register PWM4 8 — — 00H FF78H Event divider control register EDVC W 8 — — Cleared to 0 FF79H Clock output mode register CLOM R/W 8 — 00H

FF7AH Timer 4 capture/compare register 0 CR40 16 — — Cleared to 0 FF7BH Clock control register CC 8 — 00H FF7CH Timer 4 capture register 1 CR41 R 16 — — Cleared to 0 FF7DH Capture/compare control register CRC W 8 — — 00H FF7EH Timer 5 compare register CR50 R/W 16 — — Cleared to 0

FF80H I2C control register IICC 8 — 00H FF82H I2C clock select register IICCL 8 — FF84H Serial mode register 1 CSIM1 8 — FF85H Serial shift register 1 SIO1 8 — — Undefined FF86H Slave address register SVA 8 — 00H FF88H Serial mode register 2 CSIM2 8 — FF89H Serial shift register 2 SIO2 8 — — Undefined

FF8AH Serial control register 2 CSIC2 8 — — 00H

Note

IICS R 8 —

IIC R/W 8 —

FF8CH I2C bus status register FF8EH I2C bus shift register

FF90H Amplifier mode register 2 AMPM2 8 —

FF91H Head amplifier switch output control register HAPC 8 — FF94H Amplifier control register AMPC 8 — FF95H Amplifier mode register 0 AMPM0 8 — FF96H Amplifier mode register 1 AMPM1 8 — FF97H Gain control register CTLM 8 — FF98H VISS detection circuit shift register 0 VSFT0 16 — — 0000H FF99H

FF9AH VISS detection circuit shift register 1 VSFT1 16 — — FF9BH FFA0H External interrupt mode register INTM0 8 — 000000×0 FFA1H External capture mode register 1 INTM1 8 — 00H FFA2H External capture mode register 2 INTM2 8 — FFA3H VISS detection circuit control register VDC 8 —

Note These registers are provided for the µPD784928Y subseries only.

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (4/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FFA4H VISS detection circuit up/down counter register VUDC R/W 8 — — 00H FFA5H VUDC value setting register VUDST 8 — — FFA6H Key interrupt control register KEYC 8 — 70H FFA7H VISS pulse pattern setting register VPS 8 — — 00H FFA8H In-service priority register ISPR R 8 — FFAAH Interrupt mode control register IMC R/W 8 — 80H FFACH Interrupt mask flag register MK0L FFADH MK0H 8 FFAEH MK1L FFAFH MK1H 8 FFB0H FRC capture register 0L CPT0L R 16 — — Cleared to 0 FFB1H FRC capture register 0H CPT0H 8 — — FFB2H FRC capture register 1L CPT1L 16 — — FFB3H FRC capture register 1H CPT1H 8 — — FFB4H FRC capture register 2L CPT2L 16 — — FFB5H FRC capture register 2H CPT2H 8 — — FFB6H FRC capture register 3L CPT3L 16 — — FFB7H FRC capture register 3H CPT3H 8 — — FFB8H FRC capture register 4L CPT4L 16 — — FFB9H FRC capture register 4H CPT4H 8 — — FFBAH FRC capture register 5L CPT5L 16 — — FFBBH FRC capture register 5H CPT5H 8 — — FFBDH VSYNC separation circuit control register VSC R/W 8 — 00H FFBEH FFBFH VSYNC separation circuit compare register VSCMP 8 — — FFH FFC0H Standby control register STBC 8 — — 0011×000 FFC4H Execution speed select register MM W 8 — — 20H FFCEH CPU clock status register PCS R 8 — 00H FFCFH FFE0H Interrupt control register (INTP0) PIC0 R/W 8 — 43H FFE1H Interrupt control register (INTCPT3) CPTIC3 8 — FFE2H Interrupt control register (INTCPT2) CPTIC2 8 — FFE3H Interrupt control register (INTCR12) CRIC12 8 — FFE4H Interrupt control register (INTCR00) CRIC00 8 — FFE5H Interrupt control register (INTCLR1) CLRIC1 8 — FFE6H Interrupt control register (INTCR10) CRIC10 8 —

SYNC

separation circuit up/down counter register

Oscillation stabilization time specification register

MK0

MK1

VSUDC 8 — —

OSTS W 8 — —

8 FFH

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

PD784927, 784928, 784927Y, 784928Y

Table 3-1. Special Function Registers (5/5)

Address Special Function Register (SFR) Name Symbol R/W Bit Bit Units for Manipulation After Clearing

Length 1 bit 8 bits 16 bits Reset FFE7H Interrupt control register (INTCR01) CRIC01 R/W 8 — 43H FFE8H Interrupt control register (INTCR02) CRIC02 8 — FFE9H Interrupt control register (INTCR11) CRIC11 8 — FFEAH Interrupt control register (INTCPT1) CPTIC1 8 — FFEBH Interrupt control register (INTCR20) CRIC20 8 — FFECH Interrupt control register (INTIIC) FFEDH Interrupt control register (INTTB) TBIC 8 — FFEEH Interrupt control register (INTAD) ADIC 8 — FFEFH Interrupt control register (INTP2)

Interrupt control register (INTCR40) FFF0H Interrupt control register (INTUDC) UDCIC 8 — FFF1H Interrupt control register (INTCR30) CRIC30 8 — FFF2H Interrupt control register (INTCR50) CRIC50 8 — FFF3H Interrupt control register (INTCR13) CRIC13 8 — FFF4H Interrupt control register (INTCSI1) CSIIC1 8 — FFF5H Interrupt control register (INTW) WIC 8 — ×1000011 FFF6H Interrupt control register (INTVISS) VISIC 8 — 43H FFF7H Interrupt control register (INTP1) PIC1 8 — FFF8H Interrupt control register (INTP3) PIC3 8 —

FFFAH Interrupt control register (INTCSI2) CSIIC2 8 —

Note 1

Note 2

IICIC 8 —

PIC2 8 —

CRIC40

Notes 1.µPD784928Y subseries only.

2. PIC2 and CRIC40 are at the same address (register).

Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the

contents before initialization are undefined).

Data Sheet U12255EJ2V0DS00

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