NEC PD784224, PD784225, PD784224Y, PD784225Y Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD784224, 784225, 784224Y, 784225Y

16/8-BIT SINGLE-CHIP MICROCONTROLLERS

The μPD784224 and 784225 are products of the μPD784225 Subseries in the 78K/IV Series. Besides a highspeed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral hardware.

The μPD784224Y and 784225Y are based on the μPD784225 Subseries with the addition of a multimastersupporting I2C bus interface.

Flash memory versions, the μPD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM version with flash memory, and various development tools are also available.

The functions are explained in detail in the following user’s manuals. Be sure to read this manual when

designing your system.

μPD784225, 784225Y Subseries User’s Manual - Hardware : U12697E

78K/IV Series User’s Manual - Instruction

: U10905E

FEATURES

•I2C bus

•ROM correction

•Inherits peripheral functions of μPD780058Y Subseries

•Minimum instruction execution time

160 ns (main system clock fXX = 12.5 MHz) 61 μs (subsystem clock fXT = 32.768 kHz)

•I/O port: 67 pins

•Timer/counter: 16-bit timer/counter × 1 unit

8-bit timer/counter × 4 units

•Serial interface: 3 channels

UART/IOE (3-wire serial I/O): 2 channels

CSI (3-wire serial I/O, multi-master supporting I2C busNote): 1 channel

Note μPD784225Y Subseries only

•Standby function HALT/STOP/IDLE mode

In power-saving mode: HALT/IDLE mode (with subsystem clock)

•Clock division function

•Watch timer: 1 channel

•Watchdog timer: 1 channel

•Clock output function

fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT selectable

•Buzzer output function

fXX/210, fXX/211, fXX/212, fXX/213 selectable

•A/D converter: 8-bit resolution × 8 channels

•D/A converter: 8-bit resolution × 2 channels

•Supply voltage: VDD = 1.8 to 5.5 V

APPLICATION FIELD

Car audio, portable audio, telephones, etc.

Unless contextually excluded, references in this document to μPD784225 mean μPD784224, 784225, 784224Y, and 784225Y.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Document No. U12376EJ1V0DS00 (1st edition)	The mark shows major revised points.
Date Published May 2000 J CP(K)
Printed in Japan

© 1997, 2000

μPD784224, 784225, 784224Y, 784225Y

ORDERING INFORMATION

Part Number	Package	Internal ROM (Bytes)	Internal RAM (Bytes)
μPD784224GC-×××-8BT	80-pin plastic QFP (14 × 14 mm)	96 K	3,584
μPD784224GK-×××-9EUNote	80-pin plastic TQFP (fine pitch) (14 × 20 mm)	96 K	3,584
μPD784225GC-×××-8BT	80-pin plastic QFP (14 × 14 mm)	128 K	4,352
μPD784225GK-×××-9EU	80-pin plastic TQFP (fine pitch) (14 × 20 mm)	128 K	4,352
μPD784224YGC-×××-8BT	80-pin plastic QFP (14 × 14 mm)	96 K	3,584
μPD784224YGK-×××-9EU	80-pin plastic TQFP (fine pitch) (14 × 20 mm)	96 K	3,584
μPD784225YGC-×××-8BTNote	80-pin plastic QFP (14 × 14 mm)	128 K	4,352
μPD784225YGK-×××-9EUNote	80-pin plastic TQFP (fine pitch) (14 × 20 mm)	128 K	4,352

Note Under development

Remark ××× indicates a ROM code suffix.

2	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

78K/IV SERIES LINEUP

: In mass production

: Under development

Standard models

μPD784026

Enhanced A/D converter,

16-bit timer, and power management

ASSP models

μPD784956A

For DC inverter control

μPD784908

On-chip IEBusTM controller

μPD784915

Software servo control

On-chip analog circuit for VCRs Enhanced timer

μ PD784967

On-chip FIP controller/driver

Supports I2C bus

μPD784038Y

μPD784038

Enhanced internal memory capacity Pin-compatible with the μPD784026

Supports multi-master I2C bus

μPD784216AY

μPD784216A

100-pin, enhanced I/O and internal memory capacity

μPD784054

μPD784046

On-chip 10-bit A/D converter

μPD784938A

Enhanced functions of the μ PD784908, enhanced internal memory capacity, ROM correction added.

Supports multi-master I2C bus

μPD784928Y

μPD784928

Enhanced functions of the μPD784915

Supports multi-master I2C bus

μPD784225Y

μPD784225

80-pin, ROM correction added

Supports multi-master I2C bus

μPD784218AY

μPD784218A

Enhanced internal memory capacity, ROM correction added

Data Sheet U12376EJ1V0DS00

3

μPD784224, 784225, 784224Y, 784225Y

FUNCTIONS

		Part Number		μPD784224,			μPD784225,
	Item			μPD784224Y			μPD784225Y
	Number of basic instructions		113
	(mnemonics)
	General-purpose register		8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)
	Minimum instruction execution		•	160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: fXX = 12.5 MHz)
	time		•	61 μs (subsystem clock: fXT = 32.768 kHz)
	Internal	ROM	96 Kbytes			128 Kbytes
	memory
		RAM	3,584 bytes			4,352 bytes
	Memory space		1 MB with program and data spaces combined
	I/O port	Total	67
		CMOS Input	8
		CMOS I/O	59
	Pins with	Pins with pull-up	57
	ancillary	resistor
	functionsNote 1	LEDs direct	16
		drive output
	Real-time output port		4 bits × 2, or 8 bits × 1
	Timer		Timer/event counter		: Timer counter × 1		Pulse output
			(16-bit)		Capture/compare register × 2		• PWM/PPG output
							• Square wave output
							• One-shot pulse output
			Timer/event counter 1		: Timer counter × 1		Pulse output
			(8-bit)		Compare register × 1		• PWM output
							• Square wave output
			Timer/event counter 2		: Timer counter × 1		Pulse output
			(8-bit)		Compare register × 1		• PWM output
							• Square wave output
			Timer 5		: Timer counter × 1
			(8-bit)		Compare register × 1
			Timer 6		: Timer counter × 1
			(8-bit)		Compare register × 1
	Serial interface		•	UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
			•	CSI (3-wire serial I/O, I2C busNote 2 supporting multi master): 1 channel
	A/D converter		8-bit resolution × 8 channels
	D/A converter		8-bit resolution × 2 channels
	Clock output		Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
	Buzzer output		Selectable from fXX/210, fXX/211, fXX/212, fXX/213
	Watch timer		1 channel
	Watchdog timer		1 channel
	Standby		•	HALT/STOP/IDLE mode
			•	In power-saving mode (with subsystem clock): HALT/IDLE mode
	Interrupt	Hardware	25 (internal: 18, external: 7)
		Software	BRK instruction, BRKCS instruction, operand error
		Non-maskable	Internal: 1, external: 1
		Maskable	Internal: 17, external: 6
			•	4 programmable priority levels
			•	3 service modes: vectored interrupt/macro service/context switching
	Supply voltage		VDD = 1.8 to 5.5 V
	Package		•	80-pin plastic QFP(14 × 14 mm)
			•	80-pin plastic TQFP (fine pitch) (12 × 12 mm)

Notes 1. The pins with ancillary functions are included in the I/O pins.

2. μPD784225Y Subseries only

4	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

CONTENTS

1. DIFFERENCES AMONG MODELS IN μPD784225, 784225Y SUBSERIES ..............................

7

2.MAJOR DIFFERENCES BETWEEN μPD784216Y SUBSERIES AND

	μPD780058Y SUBSERIES .............................................................................................................			8
3. PIN CONFIGURATION (Top View) ...............................................................................................				9
4.	BLOCK DIAGRAM ........................................................................................................................			11
5.	PIN FUNCTION ...............................................................................................................................			12
	5.1	Port Pins ................................................................................................................................................		12
	5.2	Pins Other Than Port Pins ..................................................................................................................		14
	5.3	I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ...........		16
6.	CPU ARCHITECTURE ...................................................................................................................			20
	6.1	Memory Space ......................................................................................................................................		20
	6.2	CPU Registers ......................................................................................................................................		23
		6.2.1	General-purpose registers ..........................................................................................................	23
		6.2.2	Control registers ..........................................................................................................................	24
		6.2.3 Special function registers (SFRs) ...............................................................................................		25
7.	PERIPHERAL HARDWARE FUNCTIONS ....................................................................................			30
	7.1	Ports .......................................................................................................................................................		30
	7.2	Clock Generator ...................................................................................................................................		31
	7.3	Real-Time Output Port .........................................................................................................................		33
	7.4	Timer ......................................................................................................................................................		34
	7.5	A/D Converter .......................................................................................................................................		37
	7.6	D/A Converter .......................................................................................................................................		38
	7.7	Serial Interface .....................................................................................................................................		39
		7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ......................................................		40
		7.7.2 Clocked serial interface (CSI) .....................................................................................................		42
	7.8	Clock Output Function ........................................................................................................................		43
	7.9	Buzzer Output Function ......................................................................................................................		44
	7.10	Edge Detection Function ....................................................................................................................		44
	7.11	Watch Timer ..........................................................................................................................................		44
	7.12	Watchdog Timer ...................................................................................................................................		45
8.	INTERRUPT FUNCTION ................................................................................................................			46
	8.1	Interrupt Sources .................................................................................................................................		46
	8.2	Vectored Interrupt ................................................................................................................................		48
	8.3	Context Switching ................................................................................................................................		49
	8.4	Macro Service .......................................................................................................................................		49
	8.5	Application Example of Macro Service .............................................................................................		50

Data Sheet U12376EJ1V0DS00

5

		μPD784224, 784225, 784224Y, 784225Y
9.	LOCAL BUS INTERFACE .............................................................................................................		51
	9.1	Memory Expansion ..............................................................................................................................	51
	9.2	Programmable Wait .............................................................................................................................	51
	9.3	External Access Status Function ......................................................................................................	51
10.	STANDBY FUNCTION ...................................................................................................................		52
11.	RESET FUNCTION .........................................................................................................................		54
12.	ROM CORRECTION ......................................................................................................................		55
13.	INSTRUCTION SET ........................................................................................................................		56
14.	ELECTRICAL SPECIFICATIONS .................................................................................................		61
15.	PACKAGE DRAWINGS .................................................................................................................		82
16.	RECOMMENDED SOLDERING CONDITIONS ............................................................................		84
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................			85
APPENDIX B. RELATED DOCUMENTS ............................................................................................			88

6	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

1. DIFFERENCES AMONG MODELS IN μPD784225, 784225Y SUBSERIES

The only difference among the μPD784224 and 784225 lies in the internal memory capacity.

The μPD784224Y and 784225Y are based on the μPD784224 and 784225 respectively, with the addition of an I2C bus control function.

The μPD78F4225 and 78F4225Y are provided with a 128-Kbyte flash memory instead of the mask ROM of the above models. These differences are summarized in Table 1-1.

Table 1-1. Differences among Models in μPD784225, 784225Y Subseries

Part Number	μPD784224,	μPD784225,	μPD78F4225,
Item	μPD784224Y	μPD784225Y	μPD78F4225Y
Internal ROM	96 Kbytes	128 Kbytes	128 Kbytes
	(mask ROM)	(mask ROM)	(Flash memory)
Internal RAM	3,584 bytes	4,352 bytes
Internal memory	None		Provided
size switching
register (IMS)Note
Supply voltage	VDD = 1.8 to 5.5 V		VDD = 1.9 to 5.5 V
Electrical	Refer to the data sheet for each device.
specifications
Recommended
soldering
conditions
TEST pin	Provided		None
VPP pin	None		Provided

Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory size switching register (IMS).

Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version.

Data Sheet U12376EJ1V0DS00

7

μPD784224, 784225, 784224Y, 784225Y

2. MAJOR DIFFERENCES BETWEEN μPD784216Y SUBSERIES AND μPD780058Y SUBSERIES

			Series Name	μPD784225, 784225Y	μPD784216Y Subseries	μPD780058Y Subseries
Item				Subseries
CPU				16-bit CPU		8-bit CPU
Minimum			With main system	160 ns (at 12.5 MHz)		400 ns (at 5.0 MHz)
instruction			clock selected
execution time
			With subsystem	61 μs (at 32.768 kHz)		122 μs (at 32.768 kHz)
			clock
Memory space				1 Mbytes		64 Kbytes
I/O port			Total	67 pins	86 pins	68 pins
			CMOS input	8 pins	8 pins	2 pins
			CMOS I/O	59 pins	72 pins	62 pins
			N-ch open-drain I/O	−	6 pins	4 pins
	Pins with		Pins with pull-up	57 pins	70 pins	66 pins (flash memory
	ancillary		resistor			model: 62 pins)
	functionNote 1
			LED direct drive	16 pins	22 pins	12 pins
			output
			Medium-voltage pin	−	6 pins	4 pins
Timer/counter				• 16-bit timer/event counter	• 16-bit timer/event counter	• 16-bit timer/event counter
				× 1 unit	× 1 unit	× 1 unit
				• 8-bit timer/event counter	• 8-bit timer/event counter	• 8-bit timer/event counter
				× 4 units	× 6 units	× 2 units
Serial interface				• UART/IOE (3-wire serial I/O) × 2 channels		• UART (time-division transfer
				• CSI (3-wire serial I/O, multi-master supporting I2C		function)/IOE (3-wire
				busNote 2) × 1 channel		serial I/O) × 2 channels
						• CSI (3-wire serial I/O,
						2-wire serial I/O,
						I2C bus) × 1 channel
						• CSI (3-wire serial I/O
						with automatic
						transmission/reception
						function) × 1 channel
Interrupt			NMI pin	Provided		None
			Macro service	Provided		None
			Context switching	Provided		None
			Programmable priority	4 levels		2 levels
Standby function				• HALT/STOP/IDLE mode		HALT/STOP mode
				• Power-saving mode: HALT/IDLE Mode
ROM correction				Provided	None	Provided
Package				• 80-pin plastic QFP	• 100-pin plastic QFP	• 80-pin plastic QFP
				(14 × 14 mm)	(fine pitch) (14 × 14 mm)	(14 × 14 mm)
				• 80-pin plastic TQFP	• 100-pin plastic QFP	• 80-pin plastic TQFP
				(fine pitch) (12 × 12 mm)	(14 × 20 mm)	(fine pitch) (12 × 12 mm)

Notes 1. Pins with ancillary function are included in the I/O pins.

2. μPD784225Y and 784216Y Subseries only

8	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

3. PIN CONFIGURATION (Top View)

•	80-pin plastic QFP (14 × 14 mm)
	μPD784224GC-×××-8BT, μPD784224YGC-×××-8BT,
	μPD784225GC-×××-8BT, μPD784225YGC-×××-8BT
•	80-pin plastic TQFP (fine pitch) (12 × 12 mm)
	μPD784224GK-×××-BE9, μPD784224YGK-×××-BE9,
	μPD784225GK-×××-BE9, μPD784225YGK-×××-BE9																																											P02/INTP2/NMI
																							A14/ANI4	P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVDD VDD0 XT1 XT2						TEST		X1 X2 VDD1				VSS0		P05/INTP5		P04/INTP4		P03/INTP3				P01/INTP1		P00/INTP0
																														Note2
						80
																								79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
				P15/ANI5		1																																										60
				P16/ANI6		2																																										59
				P17/ANI7		3																																										58
					AVSS	4																																										57
			P130/ANO0												5																																	56
			P131/ANO1													6																																55
					AVREF1																		7																									54
		P70/SI2/RxD2															8																															53
		P71/SO2/TxD2															9																															52
																	10																															51
P72/SCK2/ASCK2
		P20/SI1/RxD1															11																															50
		P21/SO1/TxD1															12																															49
																	13																															48
P22/SCK1/ASCK1
				P23/PCL													14																															47
				P24/BUZ														15																														46
P25/SI0/SDA0Note 1																		16																														45
				P26/SO0															17																													44
																				18																												43
P27/SCK0/SCL0Note 1
				P40/AD0																	19																											42
				P41/AD1																		20																										41
						21																		22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

VSS1

P56/A14

P57/A15

P60/A16

P61/A17

P62/A18

P63/A19

P64/RD

Notes 1. The SCL0 and SDA0 pins are available in μPD784225Y Subseries only.

RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RPT2 P121/RTP1 P120/RTP0 P37/EXA P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB

P66/WAIT

P65/WR

2.Connect the TEST pin to VSS0 directly or via a pull-down resistor. For the pull-down connection, use of a resistor with a resistance ranging from 470 Ω to 10 kΩ is recommended.

Caution Connect the AVSS pin to VSS0.

Remark When using in applications where noise from inside the microcomputer has to be reduced, it is

recommended to take countermeasures against noise such as supplying power to VDD0 and VDD1

independently, and connecting VSS0 and VSS1 to different ground lines.

Data Sheet U12376EJ1V0DS00

9

μPD784224, 784225, 784224Y, 784225Y

A8 to A19	: Address Bus			P130, P131							: Port13
AD0 to AD7	: Address/Data Bus			PCL							: Programmable Clock
ANI0 to ANI7	: Analog Input										: Read Strobe
				RD
ANO0, ANO1	: Analog Output
				RESET							: Reset
ASCK1, ASCK2	: Asynchronous Serial Clock			RTP0 to RTP7							: Real-time Output Port
ASTB	: Address Strobe			RxD1, RxD2							: Receive Data
AVDD	: Analog Power Supply
				SCK0				to SCK2			: Serial Clock
AVREF1	: Analog Reference Voltage			SCL0Note							: Serial Clock
AVSS	: Analog Ground			SDA0Note							: Serial Data
BUZ	: Buzzer Clock			SI0 to SI2							: Serial Input
EXA	: External Access Status Output			SO0 to SO2							: Serial Output
INTP0 to INTP5	: Interrupt from Peripherals			TEST							: Test
NMI	: Non-maskable Interrupt			TI00, TI01, TI1, TI2 : Timer Input
P00 to P05	: Port0			TO0 to TO2							: Timer Output
P10 to P17	: Port1			TxD1, TxD2							: Transmit Data
P20 to P27	: Port2			VDD0, VDD1							: Power Supply
P30 to P37	: Port3			VSS0, VSS1							: Ground
											: Wait
P40 to P47	: Port4			WAIT
											: Write Strobe
P50 to P57	: Port5			WR
P60 to P67	: Port6			X1, X2							: Crystal (Main System Clock)
P70 to P72	: Port7			XT1, XT2							: Crystal (Subsystem Clock)
P120 to P127	: Port12

Note The SCL0 and SDA0 pins are available in μPD784225Y Subseries only.

10	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

4. BLOCK DIAGRAM

	INTP2/NMI	PROGRAMMABLE	UART/IOE1	RxD1/SI1
	INTP0, INTP1,	INTERRUPT	BAUD-RATE	TxD1/SO1
				ASCK1/SCK1
	INTP3 to INTP5	CONTROLLER	GENERATOR
	TI00	TIMER/EVENT	UART/IOE2	RxD2/SI2
				TxD2/SO2
	TI01	COUNTER	BAUD-RATE
				ASCK2/SCK2
	TO0	(16 BITS)	GENERATOR
	TI1	TIMER/EVENT	CLOCKED	SI0/SDA0Note
		COUNTER1	SERIAL	SO0
	TO1
		(8 BITS)	INTERFACE	SCK0/SCL0Note
	TI2	TIMER/EVENT		AD0 to AD7
		COUNTER2
	TO2			A8 to A15
		(8 BITS)
		TIMER/COUNTER5		A16 to A19
			BUS I/F	RD
		(8 BITS)
				WR
		78K/IV	ROM
		CPU CORE		WAIT
		TIMER/COUNTER6		ASTB
		(8 BITS)		EXA
		WATCH TIMER	PORT0	P00 to P05
			PORT1
				P10 to P17
		WATCHDOG TIMER	PORT2	P20 to P27
			PORT3
		RAM		P30 to P37
	RTP0 to RTP7	REAL-TIME	PORT4	P40 to P47
	NMI/INTP2	OUTPUT PORT	PORT5	P50 to P57
	ANO0		PORT6	P60 to P67
	ANO1	D/A	PORT7	P70 to P72
	AVREF1	CONVERTER
	AVSS		PORT12	P120 to P127
	ANI0 to ANI7	A/D	PORT13	P130, P131
	AVDD
	AVSS	CONVERTER		RESET
	P03/INTP3
		CLOCK OUTPUT		X1
	PCL		SYSTEM CONTROL	X2
		CONTROL
				XT1
	BUZ	BUZZER OUTPUT		XT2
				VDD0, VDD1

VSS0, VSS1

TEST

Note This function supports the I2C bus interface and is available in μPD784225Y Subseries only.

Remark The internal ROM and RAM capacities differ depending on the model.

Data Sheet U12376EJ1V0DS00

11

									μPD784224, 784225, 784224Y, 784225Y
5.		PIN FUNCTION
5.1		Port Pins (1/2)
	Pin Name		I/O		Alternate Function				Function
	P00		I/O	INTP0					Port 0 (P0):
									• 6-bit I/O port
	P01			INTP1
									• Can be set in input or output mode bit-wise.
	P02			INTP2/NM1
									• Pins set in input mode can be connected to internal pull-up
	P03			INTP3					resistors by software bit-wise.
	P04			INTP4
	P05			INTP5
	P10 to P17		Input	ANI0 to ANI7					Port 1 (P1):
									• 8-bit input port
	P20		I/O	RxD1/SI1					Port 2 (P2):
									• 8-bit I/O port
	P21			TxD1/SO1
									• Can be set in input or output mode bit-wise.
	P22			ASCK1/SCK1					• Pins set in input mode can be connected to internal pull-up
	P23			PCL					resistors by software bit-wise.
	P24			BUZ
	P25			SI0/SDA0Note
	P26			SO0
	P27				SCK0/SCL0Note
	P30		I/O	TO0					Port 3 (P3):
									• 8-bit I/O port
	P31			TO1
									• Can be set in input or output mode bit-wise.
	P32			TO2
									• Pins set in input mode can be connected to internal pull-up
	P33			TI1					resistors by software bit-wise.
	P34			TI2
	P35			TI00
	P36			TI01
	P37			EXA
	P40 to P47		I/O	AD0 to AD7					Port 4 (P4):
									• 8-bit I/O port
									• Can be set in input or output mode bit-wise.
									• All pins set in input mode can be connected to internal pull-up
									resistors by software.
									• Can drive LEDs.
	P50 to P57		I/O	A8 to A15					Port 5 (P5):
									• 8-bit I/O port
									• Can be set in input or output mode bit-wise.
									• All pins set in input mode can be connected to internal pull-up
									resistors by software.
									• Can drive LEDs.

Note This function is available in μPD784255Y Subseries only.

12	Data Sheet U12376EJ1V0DS00

									μPD784224, 784225, 784224Y, 784225Y
	5.1 Port Pins (2/2)
	Pin Name	I/O		Alternate Function						Function
	P60	I/O		A16						Port 6 (P6):
										• 8-bit I/O port
	P61			A17
										• Can be set in input or output mode bit-wise.
	P62			A18
										• All pins set in input mode can be connected to internal pull-up
	P63			A19						resistors by software.
	P64			RD
	P65			WR
	P66			WAIT
	P67			ASTB
	P70	I/O		RxD2/SI2						Port 7 (P7):
										• 3-bit I/O port
										• Can be set in input or output mode bit-wise.
	P71			TxD2/SO2
										• Pins set in input mode can be connected to internal pull-up
										resistor by software bit-wise.
	P72			ASCK2/SCK2
	P120 to P127	I/O		RTP0 to RTP7						Port 12 (P12):
										• 8-bit I/O port
										• Can be set in input or output mode bit-wise.
										• Pins set in input mode can be connected to internal pull-up
										resistor by software bit-wise.
	P130, P131	I/O		ANO0, ANO1						Port 13 (P13):
										• 2-bit I/O port
										• Can be set in input or output mode bit-wise.

Data Sheet U12376EJ1V0DS00

13

μPD784224, 784225, 784224Y, 784225Y

5.2 Pins Other Than Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TI00

Input

P35

External count clock input to 16-bit timer register

TI01

P36

Capture trigger signal input to capture/compare register 00

TI1

P33

External count clock input to 8-bit timer register 1

TI2

P34

External count clock input to 8-bit timer register 2

TO0

Output

P30

16-bit timer output (shared by 14-bit PWM output)

TO1

P31

8-bit timer output (shared by 8-bit PWM output)

TO2

P32

RxD1

Input

P20/SI1

Serial data input (UART1)

RxD2

P70/SI2

Serial data input (UART2)

TxD1

Output

P21/SO1

Serial data output (UART1)

TxD2

P71/SO2

Serial data output (UART2)

ASCK1

Intput

P22/SCK1

Baud rate clock input (UART1)

ASCK2

P72/SCK2

Baud rate clock input (UART2)

SI0

Input

P25/SDA0Note

Serial data input (3-wire serial clock I/O0)

SI1

P20/RxD1

Serial data input (3-wire serial clock I/O1)

SI2

P70/RxD2

Serial data input (3-wire serial clock I/O2)

SO0

Output

P26

Serial data output (3-wire serial I/O0)

SO1

P21/TxD1

Serial data output (3-wire serial I/O1)

SO2

P71/TxD2

Serial data output (3-wire serial I/O2)

SDA0Note

I/O

P25/SI0

Serial data input/output (I2C bus)

P27/SCL0Note

SCK0

I/O

Serial clock input/output (3-wire serial I/O0)

SCK1

P22/ASCK1

Serial clock input/output (3-wire serial I/O1)

SCK2

P72/ASCK2

Serial clock input/output (3-wire serial I/O2)

SCL0Note

Serial clock input/output (I2C bus)

P27/SCK0

NMI

Input

P02/INTP2

Non-maskable interrupt request input

INTP0

P00

External interrupt request input

INTP1

P01

INTP2

P02/NMI

INTP3

P03

INTP4

P04

INTP5

P05

PCL

Output

P23

Clock output (for trimming main system clock and subsystem clock)

BUZ

Output

P24

Buzzer output

RTP0 to RTP7

Output

P120 to P127

Real-time output port that outputs data in synchronization with

trigger

AD0 to AD7

I/O

P40 to P47

Low-order address/data bus when external memory is connected

A8 to A15

Output

P50 to P57

Middle-order address bus when external memory is connected

A16 to A19

P60 to P63

High-order address bus when external memory is connected

Note This function is available in μPD784255Y Subseries only.

14	Data Sheet U12376EJ1V0DS00

									μPD784224, 784225, 784224Y, 784225Y
	5.2 Pins Other Than Port Pins (2/2)
		Pin Name					I/O	Alternate Function		Function
		RD					Output	P64		Strobe signal output for read operation of external memory
		WR						P65		Strobe signal output for write operation of external memory
		WAIT					Input	P66		To insert wait state(s) when external memory is accessed
		ASTB					Output	P67		Strobe output to externally latch address information output to ports
										4 to 6 to access external memory
		EXA					Output	P37		External access status output
								−
		RESET					Input			System reset input
		X1					Input	−		To connect main system clock oscillation crystal
		X2					−
		XT1					Input	−		To connect subsystem clock oscillation crystal
		XT2					−
		ANI0 to ANI7					Input	P10 to P17		Analog voltage input for A/D converter
		ANO0, ANO1					Output	P130, P131		Analog voltage output for D/A converter
		AVREF1					−	−		To apply reference voltage for D/A converter
		AVDD								Positive power supply for A/D converter. Connected to VDD0.
		AVSS								GND for A/D converter and D/A converter. Connected to VSS0.
		VDD0								Positive power supply for port block
		VSS0								GND potential for port block
		VDD1								Positive power supply (except port block)
		VSS1								GND potential (except port block)
		TEST								Connect this pin to VSS0 directly or via pull-down resistor. For the
										pull-down connection, use of a resistor with a resistance ranging
										from 470 Ω to 10 kΩ is recommended.

Data Sheet U12376EJ1V0DS00

15

μPD784224, 784225, 784224Y, 784225Y

5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins

Table 5-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection

of unused pins.

For the circuit diagram of each type of I/O circuit, refer to Figure 5-1.

Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connections of Unused Pins

P00/INTP0

8-K

I/O

Input : Individually connected to VSS0 via resistor

Output: Open

P01/INTP1

P02/INTP2/NMI

P03/INTP3 to P05/INTP5

P10/ANI0 to P17/ANI7

9

Input

Connected to VSS0 or VDD0

P20/RxD1/SI1

10-I

I/O

Input : Individually connected to VSS0 via resistor

Output: Open

P21/TxD1/SO1

10-J

10-I

P22/ASCK1/SCK1

P23/PCL

10-J

P24/BUZ

P25/SDA0Note/SI0

10-I

P26/SO0

10-J

P27/SCL0Note

10-I

/SCK0

P30/TO0 to P32/TO2

8-M

P33/TI1, P34/TI2

8-K

P35/TI00, P36/TI01

8-L

P37/EXA

8-M

P40/AD0 to P47/AD7

5-H

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

P70/RxD2/SI2

8-K

P71/TxD2/SO2

8-L

8-K

P72/ASCK2/SCK2

Note This function is available in μPD784255Y Subseries only.

Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided).

16	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (2/2)

		Pin Name	I/O Circuit Type	I/O		Recommended Connections of Unused Pins
	P120/RTP0 to P127/RTP7		8-K	I/O		Input : Individually connected to VSS0 via resistor
						Output: Open
	P130/ANO0, P131/ANO1		12-D
			2-G	Input		−
	RESET
	XT1		16			Connected to VSS0
	XT2			−		Open
	AVREF1		−			Connected to VDD0
	AVDD
	AVSS					Connected to VSS0
	TEST/VPPNote
						Directly connected to VSS0

Note VPP pin is available in μPD78F4225, 78F4255Y only.

Remark Because the circuit type numbers are standardized among the 78K Series products, they are not sequential in some models (i.e., some circuits are not provided).

Data Sheet U12376EJ1V0DS00

17

μPD784224, 784225, 784224Y, 784225Y

Figure 5-1. Types of Pin I/O Circuits (1/2)

Type 2-G		Type 8-M		VDD0
		pullup		P-ch
		enable
IN				VDD0
		data		P-ch
				IN/OUT
Schmitt trigger input with hysteresis characteristics		output		N-ch
		disable
				VSS0
		input
		enable
Type 5-H	VDD0	Type 9
pullup	P-ch
enable				Comparator
			P-ch
		IN
				+
	VDD0		N-ch
				−
data	P-ch			VREF
	IN/OUT			(threshold voltage)
output	N-ch
disable
				input
	VSS0
				enable
input
enable
Type 8-K	VDD0	Type 10-I		VDD0
pullup	P-ch	pullup		P-ch
		enable
enable
	VDD0			VDD0
data	P-ch	data		P-ch
	IN/OUT	open drain		IN/OUT
output				N-ch
	N-ch	output disable
disable
				VSS0
	VSS0
Type 8-L	VDD0	Type 10-J		VDD0
pullup	P-ch	pullup		P-ch
enable		enable
	VDD0			VDD0
data	P-ch	data		P-ch
	IN/OUT			IN/OUT
open drain	N-ch	open drain		N-ch
output disable		output disable
	VSS0			VSS0

18	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

Figure 5-1. Types of Pin I/O Circuits (2/2)

Type 12-D
		VDD0
data		P-ch
		IN/OUT
output		N-ch
disable		VSS0
input		P-ch
enable	Analog output
	voltage	N-ch
		VSS0
Type 16
	feedback
	cut-off
	P-ch
XT1		XT2

Data Sheet U12376EJ1V0DS00

19

μPD784224, 784225, 784224Y, 784225Y

6. CPU ARCHITECTURE

6.1 Memory Space

A memory space of 1 Mbyte can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after RESET cancellation, and must not be used more than once.

(1) When LOCATION 0H instruction is executed

• Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number	Internal Data Area	Internal ROM Area
μPD784224,	0F100H to 0FFFFH	00000H to 0F0FFH
μPD784224Y		10000H to 17FFFH
μPD784225,	0EE00H to 0FFFFH	00000H to 0EDFFH
μPD784225Y		10000H to 1FFFFH

Caution The following areas that overlap the internal data area of the internal ROM cannot be used when

the LOCATION 0H instruction is executed.

Part Number	Unusable Area
μPD784224,	0F100H to 0FFFFH (3,840 bytes)
μPD784224Y
μPD784225,	0EE00H to 0FFFFH (4,608 bytes)
μPD784225Y

• External memory

The external memory is accessed in external memory expansion mode.

(2) When LOCATION 0FH instruction is executed

• Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number	Internal Data Area	Internal ROM Area
μPD784224,	FF100H to FFFFFH	00000H to 17FFFH
μPD784224Y
μPD784225,	FEE00H to FFFFFH	00000H to 1FFFFH
μPD784225Y

• External memory

The external memory is accessed in external memory expansion mode.

20	Data Sheet U12376EJ1V0DS00

U12376EJ1V0DS00 Sheet Data

21

Figure 6-1.	Memory Map of μPD784224, 784224Y
On execution of	On execution of
LOCATION 0H instruction	LOCATION 0FH instruction

F F F F F H					F F F F F H Special function registers (SFR)
					F F F D F H	Note 1
					F F F D 0 H	(256 bytes)
					F F F 0 0 H
		0 F E F F H		F F E F F H	F F E F F H
	External memoryNote 1		General-purpose			Internal RAM
	(928 Kbytes)		registers (128 bytes)			(3,584 bytes)
		0 F E 8 0 H		F F E 8 0 H	F F 1 0 0 H
1 8 0 0 0 H		0 F E 7 F H		F F E 7 F H	F F 0 F F H
1 7 F F F H	Internal ROM
1 0 0 0 0 H	(32,768 bytes)	0 F E 3 9 H	Macro service control word	F F E 3 9 H
0 F F F F H Special function registers (SFR)
		0 F E 0 6 H	area (52 bytes)	F F E 0 6 H
0 F F D F H	Note 1
0 F F D 0 H
0 F F 0 0 H	(256 bytes)		Data area (512 bytes)
0 F E F F H
		0 F D 0 0 H		F F D 0 0 H
						External memoryNote 1
	Internal RAM	0 F C F F H	Program/data area	F F C F F H
						(980,736 bytes)
	(3,584 bytes)
			(3,072 bytes)
0 F 1 0 0 H		0 F 1 0 0 H		F F 7 0 0 H
0 F 0 F F H
		1 7 F F F H		1 7 F F F H
		1 0 0 0 0 H
			Note 2
		0 F 0 F F H	Program/data areaNote 3
	Note 4	0 1 0 0 0 H
		0 0 F F F H
	Internal ROM		CALLF entry
	(61,696 bytes)		area (2 Kbytes)
		0 0 8 0 0 H			1 8 0 0 0 H
		0 0 7 F F H			1 7 F F F H
		0 0 0 8 0 H
		0 0 0 7 F H	CALLT table			Internal ROM	Note 4
		0 0 0 4 0 H	area (64 bytes)			(96 Kbytes)
		0 0 0 3 F H	Vector table area
0 0 0 0 0 H		0 0 0 0 0 H	(64 bytes)		0 0 0 0 0 H

Notes 1. Accessed in external memory expansion mode.

2.This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3.On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes

4.Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

784225Y 784224Y, 784225, PD784224,μ

22

U12376EJ1V0DS00 Sheet Data

Figure 6-2.	Memory Map of μPD784225, 784225Y
On execution of	On execution of
LOCATION 0H instruction	LOCATION 0FH instruction

F F F F F H					F F F F F H Special function registers (SFR)
					F F F D F H	Note 1
					F F F D 0 H	(256 bytes)
					F F F 0 0 H
	External memoryNote 1	0 F E F F H		F F E F F H	F F E F F H
			General-purpose			Internal RAM
	(896 Kbytes)
			registers (128 bytes)			(4,352 bytes)
		0 F E 8 0 H		F F E 8 0 H	F E E 0 0 H
2 0 0 0 0 H		0 F E 7 F H		F F E 7 F H	F E D F F H
1 F F F F H	Internal ROM
1 0 0 0 0 H	(65,536 bytes)	0 F E 3 9 H	Macro service control word	F F E 3 9 H
0 F F F F H Special function registers (SFR)		0 F E 0 6 H	area (52 bytes)	F F E 0 6 H
0 F F D F H	Note 1
0 F F D 0 H
0 F F 0 0 H	(256 bytes)		Data area (512 bytes)
0 F E F F H
		0 F D 0 0 H		F F D 0 0 H
						External memoryNote 1
	Internal RAM	0 F C F F H	Program/data area	F F C F F H
	(4,352 bytes)					(912,896 bytes)
			(3,840 bytes)
0 E E 0 0 H		0 E E 0 0 H		F E E 0 0 H
0 E D F F H
		1 F F F F H		1 F F F F H
		1 0 0 0 0 H
			Note 2
		0 E D F F H	Program/data areaNote 3
	Note 4
		0 1 0 0 0 H
		0 0 F F F H
	Internal ROM		CALLF entry
	(60,928 bytes)		area (2 Kbytes)
		0 0 8 0 0 H			2 0 0 0 0 H
		0 0 7 F F H			1 F F F F H
		0 0 0 8 0 H
		0 0 0 7 F H	CALLT table			Internal ROM	Note 4
		0 0 0 4 0 H	area (64 bytes)			(128 Kbytes)
		0 0 0 3 F H	Vector table area
0 0 0 0 0 H		0 0 0 0 0 H	(64 bytes)		0 0 0 0 0 H

Notes 1. Accessed in external memory expansion mode.

2.This 4,608-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3.On execution of LOCATION 0H instruction: 126,464 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes

4.Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

784225Y 784224Y, 784225, PD784224,μ

μPD784224, 784225, 784224Y, 784225Y

6.2 CPU Registers

6.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers.

Eight banks of these registers are available which can be selected by using software or the context switching function.

The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM.

Figure 6-3. General-Purpose Register Format

	A (R1)	X (R0)
		AX (RP0)
	B (R3)	C (R2)
		BC (RP1)
	R5	R4
		RP2
	R7	R6
		RP3
V	R9	R8

VVP (RG4)		VP (RP4)
U	R11	R10
UUP (RG5)		UP (RP5)
T	D (R13)	E (R12)
TDE (RG6)		DE (RP6)
W	H (R15)	L (R14)
		HL (RP7)			8 banks
WHL (RG7)
Parentheses (	) indicate an absolute name.

Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series.

Data Sheet U12376EJ1V0DS00

23

μPD784224, 784225, 784224Y, 784225Y

6.2.2Control registers

(1)Program counter (PC)

The program counter is a 20-bit register whose contents are automatically updated when the program is executed.

Figure 6-4. Program Counter (PC) Format

19

0

PC

(2)Program status word (PSW)

This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed.

Figure 6-5. Program Status Word (PSW) Format

		15	14	13	12	11	10	9	8
	PSWH	UF	RBS2	RBS1	RBS0	–	–	–	–
	PSW
		7	6	5	4	3	2	1	0
	PSWL	S	Z	RSSNote	AC	IE	P/V	0	CY

Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except

when the software for the 78K/III Series is used.

(3)Stack pointer (SP)

This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer.

Figure 6-6. Stack Pointer (SP) Format

	23	20				0
PC	0	0	0	0

24	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

6.2.3 Special function registers (SFRs)

The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space of addresses 0FF00H to 0FFFFHNote.

Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH instruction.

Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by mistake, the μPD784225 may be in the deadlock status. This deadlock status can be cleared only by inputting the RESET signal.

Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

•	Symbol ...............................	Symbol indicating an SFR. This symbol is reserved for NEC’s assembler
		(RA78K4). It can be used an sfr variable by the #pragma sfr directive with the
		C compiler (CC78K4).
•	R/W ....................................	Indicates whether the SFR is read-only, write-only, or read/write.
		R/W	: Read/write
		R	: Read-only
		W	: Write-only
• Bit units for manipulation ..		Bit units in which the value of the SFR can be manipulated.
		SFRs that can be manipulated in 16-bit units can be described as the operand
		sfrp of an instruction. To specify the address of this SFR, describe an even
		address.
		SFRs that can be manipulated in 1-bit units can be described as the operand of
		a bit manipulation instruction.
•	..............................At reset	Indicates the status of the register when the		RESET	signal has been input.

Data Sheet U12376EJ1V0DS00

25

μPD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (1/4)

AddressNote 1		Special Function Register (SFR) Name	Symbol	R/W	Bit Units for Manipulation		At Reset
					1 Bit	8 Bits 16 Bits
0FF00H		Port 0	P0	R/W		—	00HNote 2
0FF01H		Port 1	P1	R		—
0FF02H		Port 2	P2	R/W		—
0FF03H		Port 3	P3			—
0FF04H		Port 4	P4			—
0FF05H		Port 5	P5			—
0FF06H		Port 6	P6			—
0FF07H		Port 7	P7			—
0FF0CH		Port 12	P12			—
0FF0DH		Port 13	P13			—
0FF10H		16-bit timer counter	TM0	R	—	—	0000H
0FF11H
0FF12H		Capture/compare register 00	CR00	R/W	—	—
0FF13H		(16-bit timer/counter)
0FF14H		Capture/compare register 01	CR01		—	—
0FF15H		(16-bit timer/counter)
0FF16H		Capture/compare control register 0	CRC0			—	00H
0FF18H		16-bit timer mode control register	TMC0			—
0FF1AH		16-bit timer output control register	TOC0			—
0FF1CH		Prescaler mode register 0	PRM0			—
0FF20H		Port 0 mode register	PM0			—	FFH
0FF22H		Port 2 mode register	PM2			—
0FF23H		Port 3 mode register	PM3			—
0FF24H		Port 4 mode register	PM4			—
0FF25H		Port 5 mode register	PM5			—
0FF26H		Port 6 mode register	PM6			—
0FF27H		Port 7 mode register	PM7			—
0FF2CH		Port 12 mode register	PM12			—
0FF2DH		Port 13 mode register	PM13			—
0FF30H		Pull-up resistor option register 0	PU0			—	00H
0FF32H		Pull-up resistor option register 2	PU2			—
0FF33H		Pull-up resistor option register 3	PU3			—
0FF37H		Pull-up resistor option register 7	PU7			—
0FF3CH		Pull-up resistor option register 12	PU12			—
0FF40H		Clock output control register	CKS			—
Notes 1.	When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

2.Because each port is initialized to input mode at reset, “00H” is not actually read. The output latch is initialized to “0”.

26	Data Sheet U12376EJ1V0DS00

μPD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (2/4)

AddressNote	Special Function Register (SFR) Name		Symbol		R/W	Bit Units for Manipulation		At Reset
						1 Bit	8 Bits 16 Bits
0FF42H	Port function control register		PF2		R/W		—	00H
0FF4EH	Pull-up resistor option register		PUO				—
0FF50H	8-bit timer counter 1		TM1	TM1W	R	—		0000H
0FF51H	8-bit timer counter 2		TM2			—
0FF52H	Compare register 10 (8-bit timer/counter 1)		CR10	CR1W	R/W	—
0FF53H	Compare register 20 (8-bit timer/counter 2)		CR20			—
0FF54H	8-bit timer mode control register 1		TMC1	TMC1W
0FF55H	8-bit timer mode control register 2		TMC2
0FF56H	Prescaler mode register 1		PRM1	PRM1W
0FF57H	Prescaler mode register 2		PRM2
0FF60H	8-bit timer counter 5		TM5	TM5W	R	—
0FF61H	8-bit timer counter 6		TM6			—
0FF64H	Compare register 50 (8-bit timer/counter 5)		CR50	CR5W	R/W	—
0FF65H	Compare register 60 (8-bit timer/counter 6)		CR60			—
0FF68H	8-bit timer mode control register 5		TMC5	TMC5W
0FF69H	8-bit timer mode control register 6		TMC6
0FF6CH	Prescaler mode register 5		PRM5	PRM5W
0FF6DH	Prescaler mode register 6		PRM6
0FF70H	Asynchronous serial interface mode register 1		ASIM1				—	00H
0FF71H	Asynchronous serial interface mode register 2		ASIM2				—
0FF72H	Asynchronous serial interface status register 1		ASIS1		R		—
0FF73H	Asynchronous serial interface status register 2		ASIS2				—
0FF74H	Transmit shift register 1		TXS1		W	—	—	FFH
	Receive buffer register 1		RXB1		R	—	—
0FF75H	Transmit shift register 2		TXS2		W	—	—
	Receive buffer register 2		RXB2		R	—	—
0FF76H	Baud rate generator control register 1		BRGC1		R/W		—	00H
0FF77H	Baud rate generator control register 2		BRGC2				—
0FF7AH	Oscillation mode select register		CC				—
0FF80H	A/D converter mode register		ADM				—
0FF81H	A/D converter input select register		ADIS				—
0FF83H	A/D conversion result register		ADCR		R	—	—	Undefined
0FF84H	D/A conversion value setting register 0		DACS0		R/W		—	00H
0FF85H	D/A conversion value setting register 1		DACS1				—
0FF86H	D/A converter mode register	0	DAM0				—
0FF87H	D/A converter mode register	1	DAM1				—

Note When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

Data Sheet U12376EJ1V0DS00

27

μPD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (3/4)

AddressNote 1	Special Function Register (SFR) Name	Symbol		R/W	Bit Units for Manipulation		At Reset
					1 Bit	8 Bits 16 Bits
0FF88H	ROM correction control register	CORC		R/W		—	00H
0FF89H	ROM correction address pointer H	CORAH			—	—
0FF8AH	ROM correction address pointer L	CORAL			—	—	0000H
0FF8BH
0FF8DH	External access status enable register	EXAE				—	00H
0FF90H	Serial operation mode register 0	CSIM0				—
0FF91H	Serial operation mode register 1	CSIM1				—
0FF92H	Serial operation mode register 2	CSIM2				—
0FF94H	Serial I/O shift register 0	SIO0			—	—
0FF95H	Serial I/O shift register 1	SIO1			—	—
0FF96H	Serial I/O shift register 2	SIO2			—	—
0FF98H	Real-time output buffer register L	RTBL			—	—
0FF99H	Real-time output buffer register H	RTBH			—	—
0FF9AH	Real-time output port mode register	RTPM				—
0FF9BH	Real-time output port control register	RTPC				—
0FF9CH	Watch timer mode control register	WTM				—
0FFA0H	External interrupt rising edge enable register	EGP0				—
0FFA2H	External interrupt falling edge enable register	EGN0				—
0FFA8H	In-service priority register	ISPR		R		—
0FFA9H	Interrupt select control register	SNMI		R/W		—
0FFAAH	Interrupt mode control register	IMC				—	80H
0FFACH	Interrupt mask flag register 0L	MK0L	MK0				FFFFH
0FFADH	Interrupt mask flag register 0H	MK0H
0FFAEH	Interrupt mask flag register 1L	MK1L	MK1
0FFAFH	Interrupt mask flag register 1H	MK1H
0FFB0H	I2C bus control registerNote 2	IICCL0				—	00H
0FFB2H	Prescaler mode register for serial clock	SPRM0				—
0FFB4H	Slave address register	SVA0				—
0FFB6H	I2C bus status registerNote 2	IICS0		R		—
0FFB8H	Serial shift register	IIC0		R/W		—
0FFC0H	Standby control register	STBC			—	—	30H
0FFC2H	Watchdog timer mode register	WDM			—	—	00H
0FFC4H	Memory expansion mode register	MM				—	20H
0FFC7H	Programmable wait control register 1	PWC1				—	AAH
0FFC8H	Programmable wait control register 2	PWC2		W	—	—	AAAAH
00FFCEH	Clock status register	PCS		R		—	32H
0FFCFH	Oscillation stabilization time specification register	OSTS		R/W		—	00H
0FFD0H to	External SFR area	—				—	—
0FFDFH

Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

2. μPD784225Y Subseries only

28	Data Sheet U12376EJ1V0DS00