NEC PD784224, PD784225, PD784224Y, PD784225Y Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

PD784224, 784225, 784224Y, 784225Y

16/8-BIT SINGLE-CHIP MICROCONTROLLERS

The µPD784224 and 784225 are products of the µPD784225 Subseries in the 78K/IV Series. Besides a highspeed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral hardware.

PD784224Y and 784225Y are based on the µPD784225 Subseries with the addition of a multimaster-

The supporting I2C bus interface.

Flash memory versions, the µPD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM version with flash memory, and various development tools are also available.

The functions are explained in detail in the following user’s manuals. Be sure to read this manual when designing your system.

PD784225, 784225Y Subseries User’s Manual - Hardware : U12697E

78K/IV Series User’s Manual - Instruction : U10905E

FEATURES

•I2C bus

• ROM correction

• Inherits peripheral functions of Subseries

• Minimum instruction execution time 160 ns (main system clock f 61 µs (subsystem clock fXT = 32.768 kHz)

• I/O port: 67 pins

• Timer/counter: 16-bit timer/counter × 1 unit

8-bit timer/counter × 4 units

• Serial interface: 3 channels UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O, multi-master supporting I

Note

bus Note

): 1 channel

PD784225Y Subseries only

XX = 12.5 MHz)

PD780058Y

• Standby function HALT/STOP/IDLE mode In power-saving mode: HALT/IDLE mode (with subsystem clock)

• Clock division function

• Watch timer: 1 channel

• Watchdog timer: 1 channel

• Clock output function

XX, fXX/2, fXX/2

f selectable

• Buzzer output function

XX/2

, fXX/211, fXX/212, fXX/213 selectable

• A/D converter: 8-bit resolution × 8 channels

• D/A converter: 8-bit resolution × 2 channels

• Supply voltage: V

, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT

DD = 1.8 to 5.5 V

APPLICATION FIELD

Car audio, portable audio, telephones, etc.

Unless contextually excluded, references in this document to µPD784225 mean µPD784224, 784225, 784224Y,

and 784225Y.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Document No. U12376EJ1V0DS00 (1st edition) Date Published May 2000 J CP(K) Printed in Japan

The mark shows major revised points.

1997, 2000

PD784224, 784225, 784224Y, 784225Y

ORDERING INFORMATION

Part Number Package Internal ROM (Bytes) Internal RAM (Bytes)

PD784224GC-×××-8BT 80-pin plastic QFP (14 × 14 mm) 96 K 3,584

PD784224GK-×××-9EU

PD784225GC-×××-8BT 80-pin plastic QFP (14 × 14 mm) 128 K 4,352

PD784225GK-×××-9EU 80-pin plastic TQFP (fine pitch) (14 × 20 mm) 128 K 4,352

PD784224YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm) 96 K 3,584

PD784224YGK-×××-9EU 80-pin plastic TQFP (fine pitch) (14 × 20 mm) 96 K 3,584

PD784225YGC-×××-8BT

PD784225YGK-×××-9EU

Note Under development

Remark ××× indicates a ROM code suffix.

Note

80-pin plastic TQFP (fine pitch) (14 × 20 mm) 96 K 3,584

Note

80-pin plastic QFP (14 × 14 mm) 128 K 4,352

Note

80-pin plastic TQFP (fine pitch) (14 × 20 mm) 128 K 4,352

Data Sheet U12376EJ1V0DS00

78K/IV SERIES LINEUP

PD784026

PD784956A

PD784908

PD784915

PD784928

PD784928Y

PD784046

PD784054

PD784216A

PD784216AY

PD784038

PD784038Y

PD784225Y

PD784225

PD784218AY

PD784218A

Enhanced A/D converter, 16-bit timer, and power management

Enhanced internal memory capacity Pin-compatible with the PD784026

Supports I

C bus

Supports multi-master I

C bus

80-pin, ROM correction added

Supports multi-master I

C bus

Enhanced internal memory capacity, ROM correction added

100-pin, enhanced I/O and internal memory capacity

On-chip 10-bit A/D converter

For DC inverter control

On-chip IEBus

controller

Software servo control On-chip analog circuit for VCRs Enhanced timer

Supports multi-master I

C bus

Enhanced functions of the PD784915

Standard models

ASSP models

Supports multi-master I2C bus

: In mass production

: Under development

PD784967

On-chip FIP controller/driver

µ µ

PD784938A

Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

FUNCTIONS

PD784224, 784225, 784224Y, 784225Y

Part Number

Item

Number of basic instructions 113 (mnemonics)

General-purpose register 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) Minimum instruction execution • 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: fXX = 12.5 MHz)

time • 61 µs (subsystem clock: fXT = 32.768 kHz) Internal ROM 96 Kbytes 128 Kbytes

memory Memory space 1 MB with program and data spaces combined

I/O port Total 67

Pins with ancillary functions

Real-time output port 4 bits × 2, or 8 bits × 1 Timer Timer/event counter : Timer counter × 1 Pulse output

Serial interface • UART/IOE (3-wire serial I/O): 2 channels (

A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Clock output Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT Buzzer output Selectable from fXX/210, fXX/211, fXX/212, fXX/2 Watch timer 1 channel Watchdog timer 1 channel Standby • HALT/STOP/IDLE mode

Interrupt Hardware 25 (internal: 18, external: 7)

Supply voltage VDD = 1.8 to 5.5 V Package • 80-pin plastic QFP(14 × 14 mm)

RAM 3,584 bytes 4,352 bytes

CMOS Input 8 CMOS I/O 59 Pins with pull-up 57

resistor LEDs direct 16

Note 1

drive output

(16-bit) Capture/compare register × 2 • PWM/PPG output

Timer/event counter 1 : Timer counter × 1 Pulse output (8-bit) Compare register × 1 • PWM output

Timer/event counter 2 : Timer counter × 1 Pulse output (8-bit) Compare register × 1 • PWM output

Timer 5 : Timer counter × 1 (8-bit) Compare register × 1

Timer 6 : Timer counter × 1 (8-bit) Compare register × 1

• CSI (3-wire serial I/O, I2C bus

• In power-saving mode (with subsystem clock): HALT/IDLE mode

Software BRK instruction, BRKCS instruction, operand error Non-maskable Internal: 1, external: 1 Maskable Internal: 17, external: 6

• 4 programmable priority levels

• 3 service modes: vectored interrupt/macro service/context switching

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

PD784224,

PD784224Y

PD784225,

PD784225Y

• Square wave output

• One-shot pulse output

• Square wave output

Note 2

on-chip baud rate generator

supporting multi master): 1 channel

)

Notes 1. The pins with ancillary functions are included in the I/O pins.

2.µPD784225Y Subseries only

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

CONTENTS

1. DIFFERENCES AMONG MODELS IN µPD784225, 784225Y SUBSERIES .............................. 7

2. MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES AND

PD780058Y SUBSERIES............................................................................................................. 8

3. PIN CONFIGURATION (Top View)............................................................................................... 9

4. BLOCK DIAGRAM ........................................................................................................................ 11

5. PIN FUNCTION............................................................................................................................... 12

5.1 Port Pins ................................................................................................................................................ 12

5.2 Pins Other Than Port Pins .................................................................................................................. 14

5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 16

6. CPU ARCHITECTURE ................................................................................................................... 20

6.1 Memory Space ...................................................................................................................................... 2 0

6.2 CPU Registers ...................................................................................................................................... 23

6.2.1 General-purpose registers .......................................................................................................... 23

6.2.2 Control registers .......................................................................................................................... 24

6.2.3 Special function registers (SFRs) ............................................................................................... 25

7. PERIPHERAL HARDWARE FUNCTIONS .................................................................................... 30

7.1 Ports....................................................................................................................................................... 30

7.2 Clock Generator ................................................................................................................................... 31

7.3 Real-Time Output Port......................................................................................................................... 33

7.4 Timer ...................................................................................................................................................... 34

7.5 A/D Converter ....................................................................................................................................... 37

7.6 D/A Converter ....................................................................................................................................... 38

7.7 Serial Interface ..................................................................................................................................... 39

7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 40

7.7.2 Clocked serial interface (CSI) ..................................................................................................... 42

7.8 Clock Output Function ........................................................................................................................ 43

7.9 Buzzer Output Function ...................................................................................................................... 4 4

7.10 Edge Detection Function .................................................................................................................... 44

7.11 Watch Timer.......................................................................................................................................... 4 4

7.12 Watchdog Timer ................................................................................................................................... 45

8. INTERRUPT FUNCTION ................................................................................................................ 4 6

8.1 Interrupt Sources ................................................................................................................................. 46

8.2 Vectored Interrupt ................................................................................................................................48

8.3 Context Switching ................................................................................................................................49

8.4 Macro Service ....................................................................................................................................... 49

8.5 Application Example of Macro Service............................................................................................. 50

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

9. LOCAL BUS INTERFACE ............................................................................................................. 51

9.1 Memory Expansion .............................................................................................................................. 51

9.2 Programmable Wait ............................................................................................................................. 51

9.3 External Access Status Function ...................................................................................................... 51

10. STANDBY FUNCTION ................................................................................................................... 52

11. RESET FUNCTION......................................................................................................................... 54

12. ROM CORRECTION...................................................................................................................... 55

13. INSTRUCTION SET........................................................................................................................ 56

14. ELECTRICAL SPECIFICATIONS................................................................................................. 61

15. PACKAGE DRAWINGS ................................................................................................................. 82

16. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 84

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 85

APPENDIX B. RELATED DOCUMENTS ............................................................................................ 88

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

1. DIFFERENCES AMONG MODELS IN µPD784225, 784225Y SUBSERIES

The only difference among the µPD784224 and 784225 lies in the internal memory capacity. The µPD784224Y and 784225Y are based on the µPD784224 and 784225 respectively, with the addition of an

I2C bus control function.

PD78F4225 and 78F4225Y are provided with a 128-Kbyte flash memory instead of the mask ROM of the

The

above models. These differences are summarized in Table 1-1.

Table 1-1. Differences among Models in

PD784225, 784225Y Subseries

Part Number

Item Internal ROM 96 Kbytes 128 Kbytes 128 Kbytes

(mask ROM) (mask ROM) (Flash memory) Internal RAM 3,584 bytes 4,352 bytes Internal memory None Provided

size switching register (IMS)

Supply voltage VDD = 1.8 to 5.5 V VDD = 1.9 to 5.5 V Electrical Refer to the data sheet for each device.

specifications Recommended

soldering conditions

TEST pin Provided None VPP pin None Provided

Note

PD784224,

PD784224Y

PD784225,

PD784225Y

PD78F4225,

PD78F4225Y

Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory

size switching register (IMS).

Caution There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

2. MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES AND µPD780058Y SUBSERIES

Series Name

Item Subseries CPU 16-bit CPU 8-bit CPU Minimum With main system 160 ns (at 12.5 MHz) 400 ns (at 5.0 MHz)

instruction clock selected execution time

Memory space 1 Mbytes 64 Kbytes I/O port Total 67 pins 86 pins 68 pins

Pins with Pins with pull-up 57 pins 70 pins 66 pins (flash memory ancillary resistor model: 62 pins)

function

Timer/counter • 16-bit timer/event counter • 16-bit timer/event counter • 16-bit timer/event counter

Serial interface • UART/IOE (3-wire serial I/O) × 2 channels

Interrupt NMI pin Provided None

Standby function • HALT/STOP/IDLE mode HALT/STOP mode

ROM correction Provided None Provided Package • 80-pin plastic QFP • 100-pin plastic QFP • 80-pin plastic QFP

With subsystem 61 µs (at 32.768 kHz) 122 µs (at 32.768 kHz) clock

CMOS input 8 pins 8 pins 2 pins CMOS I/O 59 pins 72 pins 62 pins N-ch open-drain I/O

Note 1

LED direct drive 16 pins 22 pins 12 pins output

Medium-voltage pin

Macro service Provided None Context switching Provided None Programmable priority

PD784225, 784225Y

− 6 pins 4 pins

× 1 unit × 1 unit × 1 unit

• 8-bit timer/event counter • 8-bit timer/event counter • 8-bit timer/event counter × 4 units × 6 units × 2 units

• CSI (3-wire serial I/O, multi-master supporting I2C

Note 2

bus

4 levels 2 levels

• Power-saving mode: HALT/IDLE Mode

(14 × 14 mm) (fine pitch) (14 × 14 mm) (14 × 14 mm)

• 80-pin plastic TQFP • 100-pin plastic QFP • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) (14 × 20 mm) (fine pitch) (12 × 12 mm)

) × 1 channel

PD784216Y Subseries

PD780058Y Subseries

• UART (time-division transfer function)/IOE (3-wire

serial I/O) × 2 channels

• CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) × 1 channel

• CSI (3-wire serial I/O with automatic transmission/reception function) × 1 channel

Notes 1. Pins with ancillary function are included in the I/O pins.

2.µPD784225Y and 784216Y Subseries only

Data Sheet U12376EJ1V0DS00

3. PIN CONFIGURATION (Top View)

• 80-pin plastic QFP (14 × 14 mm)

PD784224GC-×××-8BT, µPD784224YGC-×××-8BT,

PD784225GC-×××-8BT, µPD784225YGC-×××-8BT

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

PD784224GK-×××-BE9, µPD784224YGK-×××-BE9,

PD784225GK-×××-BE9, µPD784225YGK-×××-BE9

A14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

PD784224, 784225, 784224Y, 784225Y

Note 2

AVDDV

DD0

XT1

XT2

TEST

X1X2V

DD1

SS0

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2/NMI

P01/INTP1

P00/INTP0

P15/ANI5 P16/ANI6 P17/ANI7

P130/ANO0 P131/ANO1

P70/SI2/RxD2

P71/SO2/TxD2

P72/SCK2/ASCK2

P20/SI1/RxD1

P21/SO1/TxD1

P22/SCK1/ASCK1

P23/PCL P24/BUZ

P25/SI0/SDA0

P26/SO0

P27/SCK0/SCL0

P40/AD0 P41/AD1

REF1

Note 1

1 2 3

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 40393837363534333231302928272625242322

61626364656667686970717273747576777879

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RPT2 P121/RTP1 P120/RTP0 P37/EXA P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR

SS1

P50/A8

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

P60/A16

P61/A17

P62/A18

P63/A19

P64/RD

Notes 1. The SCL0 and SDA0 pins are available in µPD784225Y Subseries only.

2. Connect the TEST pin to V

SS0 directly or via a pull-down resistor. For the pull-down connection, use

of a resistor with a resistance ranging from 470 Ω to 10 kΩ is recommended.

Caution Connect the AV

SS pin to VSS0.

Remark When using in applications where noise from inside the microcomputer has to be reduced, it is

recommended to take countermeasures against noise such as supplying power to V

DD0 and VDD1

independently, and connecting VSS0 and VSS1 to different ground lines.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

A8 to A19 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK1, ASCK2 : Asynchronous Serial Clock ASTB : Address Strobe

DD : Analog Power Supply

AV AVREF1 : Analog Reference Voltage

SS : Analog Ground

AV BUZ : Buzzer Clock EXA : External Access Status Output INTP0 to INTP5 : Interrupt from Peripherals NMI : Non-maskable Interrupt P00 to P05 : Port0 P10 to P17 : Port1 P20 to P27 : Port2 P30 to P37 : Port3 P40 to P47 : Port4 P50 to P57 : Port5 P60 to P67 : Port6 P70 to P72 : Port7 P120 to P127 : Port12

P130, P131 : Port13 PCL : Programmable Clock RD : Read Strobe RESET : Reset RTP0 to RTP7 : Real-time Output Port RxD1, RxD2 : Receive Data SCK0 to SCK2 : Serial Clock SCL0 SDA0

Note

: Serial Clock

: Serial Data SI0 to SI2 : Serial Input SO0 to SO2 : Serial Output TEST : Test TI00, TI01, TI1, TI2 : Timer Input TO0 to TO2 : Timer Output TxD1, TxD2 : Transmit Data

DD0, VDD1 : Power Supply

V VSS0, VSS1 : Ground WAIT : Wait WR : Write Strobe X1, X2 : Crystal (Main System Clock) XT1, XT2 : Crystal (Subsystem Clock)

Note The SCL0 and SDA0 pins are available in

PD784225Y Subseries only.

Data Sheet U12376EJ1V0DS00

4. BLOCK DIAGRAM

PD784224, 784225, 784224Y, 784225Y

INTP2/NMI

INTP0, INTP1,

INTP3 to INTP5

TI00 TI01

TO0

TI1

TO1

TI2

TO2

RTP0 to RTP7

NMI/INTP2

ANO0 ANO1

REF1

ANI0 to ANI7

AV AV

P03/INTP3

PCL

BUZ

PROGRAMMABLE INTERRUPT CONTROLLER

TIMER/EVENT

COUNTER

(16 BITS)

TIMER/EVENT

COUNTER1

(8 BITS)

TIMER/EVENT

COUNTER2

(8 BITS)

TIMER/COUNTER5

(8 BITS)

TIMER/COUNTER6

(8 BITS)

78K/IV

CPU CORE

UART/IOE1 BAUD-RATE GENERATOR

UART/IOE2 BAUD-RATE GENERATOR

CLOCKED SERIAL INTERFACE

BUS I/F

ROM

PORT0

RxD1/SI1 TxD1/SO1

ASCK1/SCK1 RxD2/SI2

TxD2/SO2 ASCK2/SCK2

SI0/SDA0

Note

SO0 SCK0/SCL0

AD0 to AD7 A8 to A15

A16 to A19 RD

WR WAIT ASTB

EXA

P00 to P05

Note

WATCH TIMER

PORT1 PORT2

WATCHDOG TIMER

RAM

REAL-TIME OUTPUT PORT

PORT3 PORT4 PORT5 PORT6

D/A CONVERTER

DD SS

A/D CONVERTER

PORT7 PORT12 PORT13

CLOCK OUTPUT CONTROL

SYSTEM CONTROL

P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67

P70 to P72 P120 to P127 P130, P131

RESET X1 X2 XT1

BUZZER OUTPUT

XT2 V

DD0

SS0

, V , V

DD1 SS1

TEST

Note This function supports the I2C bus interface and is available in µPD784225Y Subseries only.

Remark The internal ROM and RAM capacities differ depending on the model.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5. PIN FUNCTION

5.1 Port Pins (1/2)

Pin Name I/O Alternate Function Function P00 I/O INTP0 P01 INTP1 P02 INTP2/NM1 P03 INTP3 P04 INTP4 P05 INTP5 P10 to P17 Input ANI0 to ANI7

Port 0 (P0):

• 6-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistors by software bit-wise.

Port 1 (P1):

• 8-bit input port

P20 I/O RxD1/SI1 P21 TxD1/SO1 P22 ASCK1/SCK1 P23 PCL P24 BUZ P25 SI0/SDA0 P26 SO0 P27 SCK0/SCL0 P30 I/O TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 TI00 P36 TI01 P37 EXA P40 to P47 I/O AD0 to AD7 Port 4 (P4):

P50 to P57 I/O A8 to A15 Port 5 (P5):

Note

Port 2 (P2):

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistors by software bit-wise.

Port 3 (P3):

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistors by software bit-wise.

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• All pins set in input mode can be connected to internal pull-up resistors by software.

• Can drive LEDs.

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• All pins set in input mode can be connected to internal pull-up resistors by software.

• Can drive LEDs.

Note This function is available in µPD784255Y Subseries only.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5.1 Port Pins (2/2)

Pin Name I/O Alternate Function Function P60 I/O A16 P61 A17 P62 A18 P63 A19 P64 RD P65 WR P66 WAIT P67 ASTB P70 I/O RxD2/SI2

P71 TxD2/SO2

P72 ASCK2/SCK2

Port 6 (P6):

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• All pins set in input mode can be connected to internal pull-up resistors by software.

Port 7 (P7):

• 3-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistor by software bit-wise.

P120 to P127 I/O RTP0 to RTP7 Port 12 (P12):

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistor by software bit-wise.

P130, P131 I/O ANO0, ANO1 Port 13 (P13):

• 2-bit I/O port

• Can be set in input or output mode bit-wise.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5.2 Pins Other Than Port Pins (1/2)

Pin Name I/O Alternate Function Function TI00 Input P35 External count clock input to 16-bit timer register TI01 P36 Capture trigger signal input to capture/compare register 00 TI1 P33 External count clock input to 8-bit timer register 1 TI2 P34 External count clock input to 8-bit timer register 2 TO0 Output P30 16-bit timer output (shared by 14-bit PWM output) TO1 P31 8-bit timer output (shared by 8-bit PWM output) TO2 P32 RxD1 Input P20/SI1 Serial data input (UART1) RxD2 P70/SI2 Serial data input (UART2) TxD1 Output P21/SO1 Serial data output (UART1) TxD2 P71/SO2 Serial data output (UART2) ASCK1 Intput P22/SCK1 Baud rate clock input (UART1) ASCK2 P72/SCK2 Baud rate clock input (UART2) SI0 Input P25/SDA0 SI1 P20/RxD1 Serial data input (3-wire serial clock I/O1) SI2 P70/RxD2 Serial data input (3-wire serial clock I/O2) SO0 Output P26 Serial data output (3-wire serial I/O0) SO1 P21/TxD1 Serial data output (3-wire serial I/O1) SO2 P71/TxD2 Serial data output (3-wire serial I/O2)

Note

SDA0 SCK0 I/O P27/SCL0 SCK1 P22/ASCK1 Serial clock input/output (3-wire serial I/O1) SCK2 P72/ASCK2 Serial clock input/output (3-wire serial I/O2)

Note

SCL0 NMI Input P02/INTP2 Non-maskable interrupt request input INTP0 P00 External interrupt request input INTP1 P01 INTP2 P02/NMI INTP3 P03 INTP4 P04 INTP5 P05 PCL Output P23 Clock output (for trimming main system clock and subsystem clock) BUZ Output P24 Buzzer output RTP0 to RTP7

AD0 to AD7 I/O P40 to P47 Low-order address/data bus when external memory is connected A8 to A15 Output P50 to P57 Middle-order address bus when external memory is connected A16 to A19 P60 to P63 High-order address bus when external memory is connected

I/O P25/SI0 Serial data input/output (I2C bus)

P27/SCK0 Serial clock input/output (I2C bus)

Output P120 to P127 Real-time output port that outputs data in synchronization with

Note

Serial data input (3-wire serial clock I/O0)

Serial clock input/output (3-wire serial I/O0)

trigger

Note This function is available in µPD784255Y Subseries only.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5.2 Pins Other Than Port Pins (2/2)

Pin Name I/O Alternate Function Function RD Output P64 Strobe signal output for read operation of external memory WR P65 Strobe signal output for write operation of external memory WAIT Input P66 To insert wait state(s) when external memory is accessed ASTB Output P67 Strobe output to externally latch address information output to ports

4 to 6 to access external memory EXA Output P37 External access status output RESET Input − System reset input X1 Input − To connect main system clock oscillation crystal X2 − XT1 Input − To connect subsystem clock oscillation crystal XT2 − ANI0 to ANI7 Input P10 to P17 Analog voltage input for A/D converter ANO0, ANO1 Output P130, P131 Analog voltage output for D/A converter AVREF1 −−To apply reference voltage for D/A converter AVDD Positive power supply for A/D converter. Connected to VDD0. AVSS GND for A/D converter and D/A converter. Connected to VSS0. VDD0 Positive power supply for port block VSS0 GND potential for port block VDD1 Positive power supply (except port block) VSS1 GND potential (except port block) TEST Connect this pin to VSS0 directly or via pull-down resistor. For the

pull-down connection, use of a resistor with a resistance ranging

from 470 Ω to 10 kΩ is recommended.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins

Table 5-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection

of unused pins.

For the circuit diagram of each type of I/O circuit, refer to Figure 5-1.

Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)

Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins P00/INTP0 8-K I/O Input : Individually connected to VSS0 via resistor P01/INTP1 P02/INTP2/NMI P03/INTP3 to P05/INTP5 P10/ANI0 to P17/ANI7 9 Input Connected to VSS0 or VDD0 P20/RxD1/SI1 10-I I/O Input : Individually connected to VSS0 via resistor P21/TxD1/SO1 10-J P22/ASCK1/SCK1 10-I P23/PCL 10-J P24/BUZ P25/SDA0 P26/SO0 10-J P27/SCL0 P30/TO0 to P32/TO2 8-M P33/TI1, P34/TI2 8-K P35/TI00, P36/TI01 8-L P37/EXA 8-M P40/AD0 to P47/AD7 5-H P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 8-K P71/TxD2/SO2 8-L P72/ASCK2/SCK2 8-K

Note

/SI0 10-I

Note

/SCK0 10-I

Output: Open

Note This function is available in µPD784255Y Subseries only.

Remark Because the circuit type numbers are standardized among the 78K Series products, they are not

sequential in some models (i.e., some circuits are not provided).

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (2/2)

Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins P120/RTP0 to P127/RTP7 8-K I/O Input : Individually connected to VSS0 via resistor P130/ANO0, P131/ANO1 12-D RESET 2-G Input − XT1 16 Connected to VSS0 XT2 − Open AVREF1 − Connected to VDD0 AVDD AVSS Connected to VSS0 TEST/VPP

Note

Output: Open

Directly connected to VSS0

Note VPP pin is available in µPD78F4225, 78F4255Y only.

Remark Because the circuit type numbers are standardized among the 78K Series products, they are not

sequential in some models (i.e., some circuits are not provided).

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Figure 5-1. Types of Pin I/O Circuits (1/2)

Type 2-G

Schmitt trigger input with hysteresis characteristics

Type 5-H

pullup enable

data

output disable

SS0

DD0

P-ch

DD0

P-ch

N-ch

input enable

IN/OUT

Type 8-M

pullup enable

data

output disable

input enable

Type 9

P-ch

N-ch

DD0

P-ch

N-ch

SS0

Comparator

−

REF

(threshold voltage)

DD0

P-ch

IN/OUT

input enable

Type 8-K

pullup enable

data

output disable

Type 8-L

pullup

enable

data

open drain

output disable

DD0

Type 10-I

pullup

P-ch

DD0

P-ch

IN/OUT

N-ch

SS0

DD0

P-ch

DD0

P-ch

enable

data

open drain

output disable

Type 10-J

pullup

enable

data

IN/OUT

N-ch

SS0

open drain

output disable

SS0

DD0

P-ch

DD0

P-ch

IN/OUT

N-ch

DD0

P-ch

DD0

P-ch

IN/OUT

N-ch

Data Sheet U12376EJ1V0DS00

Type 12-D

data

output disable

input enable

Type 16

Analog output voltage

feedback cut-off

P-ch

VSS0 P-ch

N-ch

PD784224, 784225, 784224Y, 784225Y

Figure 5-1. Types of Pin I/O Circuits (2/2)

DD0

P-ch

IN/OUT

N-ch

VSS0

XT1 XT2

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

6. CPU ARCHITECTURE

6.1 Memory Space

A memory space of 1 Mbyte can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after RESET cancellation, and must not be used more than once.

(1) When LOCATION 0H instruction is executed

• Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number Internal Data Area Internal ROM Area

PD784224, 0F100H to 0FFFFH 00000H to 0F0FFH

PD784224Y 10000H to 17FFFH

PD784225, 0EE00H to 0FFFFH 00000H to 0EDFFH

PD784225Y 10000H to 1FFFFH

Caution The following areas that overlap the internal data area of the internal ROM cannot be used when

the LOCATION 0H instruction is executed.

Part Number Unusable Area

PD784224, 0F100H to 0FFFFH (3,840 bytes)

PD784224Y

PD784225, 0EE00H to 0FFFFH (4,608 bytes)

PD784225Y

• External memory

The external memory is accessed in external memory expansion mode.

(2) When LOCATION 0FH instruction is executed

• Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number Internal Data Area Internal ROM Area

PD784224, FF100H to FFFFFH 00000H to 17FFFH

PD784224Y

PD784225, FEE00H to FFFFFH 00000H to 1FFFFH

PD784225Y

• External memory

The external memory is accessed in external memory expansion mode.

Data Sheet U12376EJ1V0DS00

(256 bytes)

Internal RAM

On execution of

Note 1

Special function registers (SFR)

LOCATION 0FH instruction

HFFFFF

HFDFFF

H0DFFF

H00FFF

(3,584 bytes)

HFFEFF

PD784224, 784225, 784224Y, 784225Y

Note 4

Note 1

Internal ROM

External memory

(980,736 bytes)

HFFF71

HFF0FF

H001FF

H00081

(96 Kbytes)

H00000

HFFEFF

PD784224, 784224Y

HFFEF0

H08EFF

HF7EFF

General-purpose

registers (128 bytes)

H08EF0

Figure 6-1. Memory Map of

Note 1

On execution of

LOCATION 0H instruction

HFFFFF

External memory

(928 Kbytes)

HF7EF0

Internal ROM

H00081

HFFF71

H93EFF

H60EFF

H00DFF

HFFCFF

H007FF

Program/data area

H00DF0

HFFCF0

(3,072 bytes)

H001F0

Data area (512 bytes)

Macro service control word

area (52 bytes)

H93EF0

H60EF0

(256 bytes)

(32,768 bytes)

Internal RAM

(3,584 bytes)

Note 1

Special function registers (SFR)

H00001

HFFFF0

HFDFF0

H0DFF0

H00FF0

HFFEF0

H001F0

HFFF71

Note 3

Note 2

CALLF entry

H00010

HFFF00

area (2 Kbytes)

H00800

HFF700

Internal ROM

(61,696 bytes)

CALLT table

area (64 bytes)

H08000

HF7000

H04000

Vector table area

(64 bytes)

HF3000

H00000

Program/data area

HFF0F0

H00001

HFFF71

Note 4

HFF0F0

Data Sheet U12376EJ1V0DS00

2. This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Notes 1. Accessed in external memory expansion mode.

(256 bytes)

Internal RAM

On execution of

Note 1

Special function registers (SFR)

LOCATION 0FH instruction

HFFFFF

HFDFFF

H0DFFF

H00FFF

(4,352 bytes)

HFFEFF

PD784224, 784225, 784224Y, 784225Y

Note 4

Note 1

Internal ROM

External memory

(912,896 bytes)

HFFFF1

HFFDEF

H00EEF

H00002

(128 Kbytes)

H00000

HFFEFF

PD784225, 784225Y

HFFEF0

H08EFF

HF7EFF

General-purpose

registers (128 bytes)

H08EF0

HF7EF0

Figure 6-2. Memory Map of

Note 1

On execution of

LOCATION 0H instruction

HFFFFF

External memory

(896 Kbytes)

H00002

H93EFF

H60EFF

H00DFF

HFFCFF

Macro service control word

H93EF0

Internal ROM

(65,536 bytes)

Data area (512 bytes)

area (52 bytes)

H00DF0

H60EF0

HFFCF0

(256 bytes)

Internal RAM

Note 1

Special function registers (SFR)

H00001

HFFFF1

HFFFF0

HFDFF0

H0DFF0

H00FF0

HFFEF0

HFFFF1

H00EEF

Note 2

Program/data area

(3,840 bytes)

H00001

HFFFF1

H00EE0

(4,352 bytes)

H00EE0

HFFDE0

Note 3

CALLF entry

H00010

HFFF00

Internal ROM

area (2 Kbytes)

(60,928 bytes)

Program/data area

HFFDE0

Note 4

CALLT table

area (64 bytes)

Vector table area

H00800

HFF700

H08000

HF7000

H04000

HF3000

(64 bytes)

H00000

Data Sheet U12376EJ1V0DS00

2. This 4,608-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 126,464 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Notes 1. Accessed in external memory expansion mode.

(

PD784224, 784225, 784224Y, 784225Y

6.2 CPU Registers

6.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers.

Eight banks of these registers are available which can be selected by using software or the context switching function.

The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM.

Figure 6-3. General-Purpose Register Format

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

Parentheses

A (R1)

AX (RP0)

B (R3)

BC (RP1)

VP (RP4)

R11

UP (RP5)

D (R13)

DE (RP6)

H (R15)

HL (RP7)

) indicate an absolute name.

X (R0)

C (R2)

RP2

RP3

R10

E (R12)

L (R14)

8 banks

Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

6.2.2 Control registers

(1) Program counter (PC)

The program counter is a 20-bit register whose contents are automatically updated when the program is executed.

Figure 6-4. Program Counter (PC) Format

19 0

(2) Program status word (PSW)

This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed.

Figure 6-5. Program Status Word (PSW) Format

15 14 13 12 11 10 9 8

UF RBS2 RBS1 RBS0 – – – –PSWH

PSW

76543210 S Z RSS

Note

AC IE P/V 0 CYPSWL

Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except

when the software for the 78K/III Series is used.

(3) Stack pointer (SP)

This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer.

Figure 6-6. Stack Pointer (SP) Format

23 0

0000

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

6.2.3 Special function registers (SFRs)

The special function registers, such as the mode registers and control registers of the internal peripheral

hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space

Note

of addresses 0FF00H to 0FFFFH

Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH

instruction.

Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed

by mistake, the only by inputting the RESET signal.

Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

• Symbol ............................... Symbol indicating an SFR. This symbol is reserved for NEC’s assembler

PD784225 may be in the deadlock status. This deadlock status can be cleared

(RA78K4). It can be used an sfr variable by the #pragma sfr directive with the C compiler (CC78K4).

• R/ W .................................... Indicates whether the SFR is read-only, write-only, or read/write.

R/W : Read/write R : Read-only W : Write-only

• Bit units for manipulation.. Bit units in which the value of the SFR can be manipulated.

SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction.

• At reset .............................. Indicates the status of the register when the RESET signal has been input.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (1/4)

Address

Note 1

0FF00H Port 0 P0 R/W — 00H 0FF01H Port 1 P1 R — 0FF02H Port 2 P2 R/W — 0FF03H Port 3 P3 — 0FF04H Port 4 P4 — 0FF05H Port 5 P5 — 0FF06H Port 6 P6 — 0FF07H Port 7 P7 — 0FF0CH Port 12 P12 — 0FF0DH Port 13 P13 — 0FF10H 16-bit timer counter TM0 R — — 0000H 0FF11H 0FF12H Capture/compare register 00 CR00 R/W — — 0FF13H 0FF14H Capture/compare register 01 CR01 — — 0FF15H 0FF16H Capture/compare control register 0 CRC0 — 00H 0FF18H 16-bit timer mode control register TMC0 — 0FF1AH 16-bit timer output control register TOC0 — 0FF1CH Prescaler mode register 0 PRM0 — 0FF20H Port 0 mode register PM0 — FFH 0FF22H Port 2 mode register PM2 — 0FF23H Port 3 mode register PM3 — 0FF24H Port 4 mode register PM4 — 0FF25H Port 5 mode register PM5 — 0FF26H Port 6 mode register PM6 — 0FF27H Port 7 mode register PM7 — 0FF2CH Port 12 mode register PM12 — 0FF2DH Port 13 mode register PM13 — 0FF30H Pull-up resistor option register 0 PU0 — 00H 0FF32H Pull-up resistor option register 2 PU2 — 0FF33H Pull-up resistor option register 3 PU3 — 0FF37H Pull-up resistor option register 7 PU7 — 0FF3CH Pull-up resistor option register 12 PU12 — 0FF40H Clock output control register CKS —

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation At Reset

1 Bit 8 Bits 16 Bits

(16-bit timer/counter)

Note 2

Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

2. Because each port is initialized to input mode at reset, “00H” is not actually read. The output latch is initialized to “0”.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (2/4)

Note

Address

0FF42H Port function control register PF2 R/W — 00H 0FF4EH Pull-up resistor option register PUO — 0FF50H 8-bit timer counter 1 0FF51H 8-bit timer counter 2 0FF52H Compare register 10 (8-bit timer/counter 1) 0FF53H Compare register 20 (8-bit timer/counter 2) 0FF54H 8-bit timer mode control register 1 0FF55H 8-bit timer mode control register 2 0FF56H Prescaler mode register 1 0FF57H Prescaler mode register 2 0FF60H 8-bit timer counter 5 TM5 0FF61H 8-bit timer counter 6 TM6 — 0FF64H Compare register 50 (8-bit timer/counter 5) 0FF65H Compare register 60 (8-bit timer/counter 6) 0FF68H 8-bit timer mode control register 5 0FF69H 8-bit timer mode control register 6 0FF6CH Prescaler mode register 5 0FF6DH Prescaler mode register 6 0FF70H 0FF71H 0FF72H 0FF73H 0FF74H Transmit shift register 1 TXS1 W — — FFH

0FF75H Transmit shift register 2 TXS2 W — —

0FF76H Baud rate generator control register 1 BRGC1 R/W — 00H 0FF77H Baud rate generator control register 2 BRGC2 — 0FF7AH Oscillation mode select register CC — 0FF80H A/D converter mode register ADM — 0FF81H A/D converter input select register ADIS — 0FF83H A/D conversion result register ADCR R — — Undefined 0FF84H D/A conversion value setting register 0 DACS0 R/W — 00H 0FF85H D/A conversion value setting register 1 DACS1 — 0FF86H D/A converter mode register 0 DAM0 — 0FF87H D/A converter mode register 1 DAM1 —

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation At Reset

1 Bit 8 Bits 16 Bits

TM1 TM1W TM2 CR10 CR1W CR20 TMC1 TMC2 PRM1 PRM2

CR50 CR5W CR60 TMC5 TMC6 PRM5

PRM6 Asynchronous serial interface mode register 1 Asynchronous serial interface mode register 2 Asynchronous serial interface status register 1 Asynchronous serial interface status register 2

Receive buffer register 1 RXB1 R — —

Receive buffer register 2 RXB2 R — —

ASIM1 — 00H ASIM2 — ASIS1 R — ASIS2 —

R— 0000H

—

R/W —

—

TMC1W

PRM1W

TM5W

R—

R/W —

—

TMC5W

PRM5W

Note When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (3/4)

Address

Note 1

0FF88H ROM correction control register CORC R/W — 00H 0FF89H ROM correction address pointer H CORAH — — 0FF8AH ROM correction address pointer L CORAL — — 0000H 0FF8BH 0FF8DH External access status enable register EXAE — 00H 0FF90H Serial operation mode register 0 CSIM0 — 0FF91H Serial operation mode register 1 CSIM1 — 0FF92H Serial operation mode register 2 CSIM2 — 0FF94H Serial I/O shift register 0 SIO0 — — 0FF95H Serial I/O shift register 1 SIO1 — — 0FF96H Serial I/O shift register 2 SIO2 — — 0FF98H Real-time output buffer register L RTBL — — 0FF99H Real-time output buffer register H RTBH — — 0FF9AH Real-time output port mode register RTPM — 0FF9BH Real-time output port control register RTPC — 0FF9CH Watch timer mode control register WTM — 0FFA0H 0FFA2H 0FFA8H In-service priority register ISPR R — 0FFA9H Interrupt select control register SNMI R/W — 0FFAAH Interrupt mode control register IMC — 80H 0FFACH Interrupt mask flag register 0L 0FFADH Interrupt mask flag register 0H 0FFAEH Interrupt mask flag register 1L 0FFAFH Interrupt mask flag register 1H 0FFB0H I2C bus control register 0FFB2H Prescaler mode register for serial clock SPRM0 — 0FFB4H Slave address register SVA0 — 0FFB6H I2C bus status register 0FFB8H Serial shift register IIC0 R/W — 0FFC0H Standby control register STBC — — 30H 0FFC2H Watchdog timer mode register WDM — — 00H 0FFC4H Memory expansion mode register MM — 20H 0FFC7H Programmable wait control register 1 PWC1 — AAH 0FFC8H Programmable wait control register 2 PWC2 W — — AAAAH 00FFCEH Clock status register PCS R — 32H 0FFCFH 0FFD0H to External SFR area — — —

0FFDFH

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation At Reset

1 Bit 8 Bits 16 Bits

External interrupt rising edge enable register External interrupt falling edge enable register

Note 2

Oscillation stabilization time specification register

EGP0 — EGN0 —

MK0L MK0 MK0H MK1L MK1 MK1H

IICCL0 — 00H

IICS0 R —

OSTS R/W — 00H

FFFFH

Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

PD784225Y Subseries only

Data Sheet U12376EJ1V0DS00

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