NEC PD784224, PD784225, PD784224Y, PD784225Y Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

PD784224, 784225, 784224Y, 784225Y

16/8-BIT SINGLE-CHIP MICROCONTROLLERS

The µPD784224 and 784225 are products of the µPD784225 Subseries in the 78K/IV Series. Besides a highspeed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral hardware.

PD784224Y and 784225Y are based on the µPD784225 Subseries with the addition of a multimaster-

The supporting I2C bus interface.

Flash memory versions, the µPD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM version with flash memory, and various development tools are also available.

The functions are explained in detail in the following user’s manuals. Be sure to read this manual when designing your system.

PD784225, 784225Y Subseries User’s Manual - Hardware : U12697E

78K/IV Series User’s Manual - Instruction : U10905E

FEATURES

•I2C bus

• ROM correction

• Inherits peripheral functions of Subseries

• Minimum instruction execution time 160 ns (main system clock f 61 µs (subsystem clock fXT = 32.768 kHz)

• I/O port: 67 pins

• Timer/counter: 16-bit timer/counter × 1 unit

8-bit timer/counter × 4 units

• Serial interface: 3 channels UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O, multi-master supporting I

Note

bus Note

): 1 channel

PD784225Y Subseries only

XX = 12.5 MHz)

PD780058Y

• Standby function HALT/STOP/IDLE mode In power-saving mode: HALT/IDLE mode (with subsystem clock)

• Clock division function

• Watch timer: 1 channel

• Watchdog timer: 1 channel

• Clock output function

XX, fXX/2, fXX/2

f selectable

• Buzzer output function

XX/2

, fXX/211, fXX/212, fXX/213 selectable

• A/D converter: 8-bit resolution × 8 channels

• D/A converter: 8-bit resolution × 2 channels

• Supply voltage: V

, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT

DD = 1.8 to 5.5 V

APPLICATION FIELD

Car audio, portable audio, telephones, etc.

Unless contextually excluded, references in this document to µPD784225 mean µPD784224, 784225, 784224Y,

and 784225Y.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Document No. U12376EJ1V0DS00 (1st edition) Date Published May 2000 J CP(K) Printed in Japan

The mark shows major revised points.

1997, 2000

PD784224, 784225, 784224Y, 784225Y

ORDERING INFORMATION

Part Number Package Internal ROM (Bytes) Internal RAM (Bytes)

PD784224GC-×××-8BT 80-pin plastic QFP (14 × 14 mm) 96 K 3,584

PD784224GK-×××-9EU

PD784225GC-×××-8BT 80-pin plastic QFP (14 × 14 mm) 128 K 4,352

PD784225GK-×××-9EU 80-pin plastic TQFP (fine pitch) (14 × 20 mm) 128 K 4,352

PD784224YGC-×××-8BT 80-pin plastic QFP (14 × 14 mm) 96 K 3,584

PD784224YGK-×××-9EU 80-pin plastic TQFP (fine pitch) (14 × 20 mm) 96 K 3,584

PD784225YGC-×××-8BT

PD784225YGK-×××-9EU

Note Under development

Remark ××× indicates a ROM code suffix.

Note

80-pin plastic TQFP (fine pitch) (14 × 20 mm) 96 K 3,584

Note

80-pin plastic QFP (14 × 14 mm) 128 K 4,352

Note

80-pin plastic TQFP (fine pitch) (14 × 20 mm) 128 K 4,352

Data Sheet U12376EJ1V0DS00

78K/IV SERIES LINEUP

PD784026

PD784956A

PD784908

PD784915

PD784928

PD784928Y

PD784046

PD784054

PD784216A

PD784216AY

PD784038

PD784038Y

PD784225Y

PD784225

PD784218AY

PD784218A

Enhanced A/D converter, 16-bit timer, and power management

Enhanced internal memory capacity Pin-compatible with the PD784026

Supports I

C bus

Supports multi-master I

C bus

80-pin, ROM correction added

Supports multi-master I

C bus

Enhanced internal memory capacity, ROM correction added

100-pin, enhanced I/O and internal memory capacity

On-chip 10-bit A/D converter

For DC inverter control

On-chip IEBus

controller

Software servo control On-chip analog circuit for VCRs Enhanced timer

Supports multi-master I

C bus

Enhanced functions of the PD784915

Standard models

ASSP models

Supports multi-master I2C bus

: In mass production

: Under development

PD784967

On-chip FIP controller/driver

µ µ

PD784938A

Enhanced functions of the PD784908, enhanced internal memory capacity, ROM correction added.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

FUNCTIONS

PD784224, 784225, 784224Y, 784225Y

Part Number

Item

Number of basic instructions 113 (mnemonics)

General-purpose register 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) Minimum instruction execution • 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: fXX = 12.5 MHz)

time • 61 µs (subsystem clock: fXT = 32.768 kHz) Internal ROM 96 Kbytes 128 Kbytes

memory Memory space 1 MB with program and data spaces combined

I/O port Total 67

Pins with ancillary functions

Real-time output port 4 bits × 2, or 8 bits × 1 Timer Timer/event counter : Timer counter × 1 Pulse output

Serial interface • UART/IOE (3-wire serial I/O): 2 channels (

A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Clock output Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT Buzzer output Selectable from fXX/210, fXX/211, fXX/212, fXX/2 Watch timer 1 channel Watchdog timer 1 channel Standby • HALT/STOP/IDLE mode

Interrupt Hardware 25 (internal: 18, external: 7)

Supply voltage VDD = 1.8 to 5.5 V Package • 80-pin plastic QFP(14 × 14 mm)

RAM 3,584 bytes 4,352 bytes

CMOS Input 8 CMOS I/O 59 Pins with pull-up 57

resistor LEDs direct 16

Note 1

drive output

(16-bit) Capture/compare register × 2 • PWM/PPG output

Timer/event counter 1 : Timer counter × 1 Pulse output (8-bit) Compare register × 1 • PWM output

Timer/event counter 2 : Timer counter × 1 Pulse output (8-bit) Compare register × 1 • PWM output

Timer 5 : Timer counter × 1 (8-bit) Compare register × 1

Timer 6 : Timer counter × 1 (8-bit) Compare register × 1

• CSI (3-wire serial I/O, I2C bus

• In power-saving mode (with subsystem clock): HALT/IDLE mode

Software BRK instruction, BRKCS instruction, operand error Non-maskable Internal: 1, external: 1 Maskable Internal: 17, external: 6

• 4 programmable priority levels

• 3 service modes: vectored interrupt/macro service/context switching

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

PD784224,

PD784224Y

PD784225,

PD784225Y

• Square wave output

• One-shot pulse output

• Square wave output

Note 2

on-chip baud rate generator

supporting multi master): 1 channel

)

Notes 1. The pins with ancillary functions are included in the I/O pins.

2.µPD784225Y Subseries only

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

CONTENTS

1. DIFFERENCES AMONG MODELS IN µPD784225, 784225Y SUBSERIES .............................. 7

2. MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES AND

PD780058Y SUBSERIES............................................................................................................. 8

3. PIN CONFIGURATION (Top View)............................................................................................... 9

4. BLOCK DIAGRAM ........................................................................................................................ 11

5. PIN FUNCTION............................................................................................................................... 12

5.1 Port Pins ................................................................................................................................................ 12

5.2 Pins Other Than Port Pins .................................................................................................................. 14

5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 16

6. CPU ARCHITECTURE ................................................................................................................... 20

6.1 Memory Space ...................................................................................................................................... 2 0

6.2 CPU Registers ...................................................................................................................................... 23

6.2.1 General-purpose registers .......................................................................................................... 23

6.2.2 Control registers .......................................................................................................................... 24

6.2.3 Special function registers (SFRs) ............................................................................................... 25

7. PERIPHERAL HARDWARE FUNCTIONS .................................................................................... 30

7.1 Ports....................................................................................................................................................... 30

7.2 Clock Generator ................................................................................................................................... 31

7.3 Real-Time Output Port......................................................................................................................... 33

7.4 Timer ...................................................................................................................................................... 34

7.5 A/D Converter ....................................................................................................................................... 37

7.6 D/A Converter ....................................................................................................................................... 38

7.7 Serial Interface ..................................................................................................................................... 39

7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 40

7.7.2 Clocked serial interface (CSI) ..................................................................................................... 42

7.8 Clock Output Function ........................................................................................................................ 43

7.9 Buzzer Output Function ...................................................................................................................... 4 4

7.10 Edge Detection Function .................................................................................................................... 44

7.11 Watch Timer.......................................................................................................................................... 4 4

7.12 Watchdog Timer ................................................................................................................................... 45

8. INTERRUPT FUNCTION ................................................................................................................ 4 6

8.1 Interrupt Sources ................................................................................................................................. 46

8.2 Vectored Interrupt ................................................................................................................................48

8.3 Context Switching ................................................................................................................................49

8.4 Macro Service ....................................................................................................................................... 49

8.5 Application Example of Macro Service............................................................................................. 50

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

9. LOCAL BUS INTERFACE ............................................................................................................. 51

9.1 Memory Expansion .............................................................................................................................. 51

9.2 Programmable Wait ............................................................................................................................. 51

9.3 External Access Status Function ...................................................................................................... 51

10. STANDBY FUNCTION ................................................................................................................... 52

11. RESET FUNCTION......................................................................................................................... 54

12. ROM CORRECTION...................................................................................................................... 55

13. INSTRUCTION SET........................................................................................................................ 56

14. ELECTRICAL SPECIFICATIONS................................................................................................. 61

15. PACKAGE DRAWINGS ................................................................................................................. 82

16. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 84

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 85

APPENDIX B. RELATED DOCUMENTS ............................................................................................ 88

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

1. DIFFERENCES AMONG MODELS IN µPD784225, 784225Y SUBSERIES

The only difference among the µPD784224 and 784225 lies in the internal memory capacity. The µPD784224Y and 784225Y are based on the µPD784224 and 784225 respectively, with the addition of an

I2C bus control function.

PD78F4225 and 78F4225Y are provided with a 128-Kbyte flash memory instead of the mask ROM of the

The

above models. These differences are summarized in Table 1-1.

Table 1-1. Differences among Models in

PD784225, 784225Y Subseries

Part Number

Item Internal ROM 96 Kbytes 128 Kbytes 128 Kbytes

(mask ROM) (mask ROM) (Flash memory) Internal RAM 3,584 bytes 4,352 bytes Internal memory None Provided

size switching register (IMS)

Supply voltage VDD = 1.8 to 5.5 V VDD = 1.9 to 5.5 V Electrical Refer to the data sheet for each device.

specifications Recommended

soldering conditions

TEST pin Provided None VPP pin None Provided

Note

PD784224,

PD784224Y

PD784225,

PD784225Y

PD78F4225,

PD78F4225Y

Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory

size switching register (IMS).

Caution There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

2. MAJOR DIFFERENCES BETWEEN µPD784216Y SUBSERIES AND µPD780058Y SUBSERIES

Series Name

Item Subseries CPU 16-bit CPU 8-bit CPU Minimum With main system 160 ns (at 12.5 MHz) 400 ns (at 5.0 MHz)

instruction clock selected execution time

Memory space 1 Mbytes 64 Kbytes I/O port Total 67 pins 86 pins 68 pins

Pins with Pins with pull-up 57 pins 70 pins 66 pins (flash memory ancillary resistor model: 62 pins)

function

Timer/counter • 16-bit timer/event counter • 16-bit timer/event counter • 16-bit timer/event counter

Serial interface • UART/IOE (3-wire serial I/O) × 2 channels

Interrupt NMI pin Provided None

Standby function • HALT/STOP/IDLE mode HALT/STOP mode

ROM correction Provided None Provided Package • 80-pin plastic QFP • 100-pin plastic QFP • 80-pin plastic QFP

With subsystem 61 µs (at 32.768 kHz) 122 µs (at 32.768 kHz) clock

CMOS input 8 pins 8 pins 2 pins CMOS I/O 59 pins 72 pins 62 pins N-ch open-drain I/O

Note 1

LED direct drive 16 pins 22 pins 12 pins output

Medium-voltage pin

Macro service Provided None Context switching Provided None Programmable priority

PD784225, 784225Y

− 6 pins 4 pins

× 1 unit × 1 unit × 1 unit

• 8-bit timer/event counter • 8-bit timer/event counter • 8-bit timer/event counter × 4 units × 6 units × 2 units

• CSI (3-wire serial I/O, multi-master supporting I2C

Note 2

bus

4 levels 2 levels

• Power-saving mode: HALT/IDLE Mode

(14 × 14 mm) (fine pitch) (14 × 14 mm) (14 × 14 mm)

• 80-pin plastic TQFP • 100-pin plastic QFP • 80-pin plastic TQFP (fine pitch) (12 × 12 mm) (14 × 20 mm) (fine pitch) (12 × 12 mm)

) × 1 channel

PD784216Y Subseries

PD780058Y Subseries

• UART (time-division transfer function)/IOE (3-wire

serial I/O) × 2 channels

• CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus) × 1 channel

• CSI (3-wire serial I/O with automatic transmission/reception function) × 1 channel

Notes 1. Pins with ancillary function are included in the I/O pins.

2.µPD784225Y and 784216Y Subseries only

Data Sheet U12376EJ1V0DS00

3. PIN CONFIGURATION (Top View)

• 80-pin plastic QFP (14 × 14 mm)

PD784224GC-×××-8BT, µPD784224YGC-×××-8BT,

PD784225GC-×××-8BT, µPD784225YGC-×××-8BT

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

PD784224GK-×××-BE9, µPD784224YGK-×××-BE9,

PD784225GK-×××-BE9, µPD784225YGK-×××-BE9

A14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

PD784224, 784225, 784224Y, 784225Y

Note 2

AVDDV

DD0

XT1

XT2

TEST

X1X2V

DD1

SS0

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2/NMI

P01/INTP1

P00/INTP0

P15/ANI5 P16/ANI6 P17/ANI7

P130/ANO0 P131/ANO1

P70/SI2/RxD2

P71/SO2/TxD2

P72/SCK2/ASCK2

P20/SI1/RxD1

P21/SO1/TxD1

P22/SCK1/ASCK1

P23/PCL P24/BUZ

P25/SI0/SDA0

P26/SO0

P27/SCK0/SCL0

P40/AD0 P41/AD1

REF1

Note 1

1 2 3

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 40393837363534333231302928272625242322

61626364656667686970717273747576777879

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RPT2 P121/RTP1 P120/RTP0 P37/EXA P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR

SS1

P50/A8

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

P60/A16

P61/A17

P62/A18

P63/A19

P64/RD

Notes 1. The SCL0 and SDA0 pins are available in µPD784225Y Subseries only.

2. Connect the TEST pin to V

SS0 directly or via a pull-down resistor. For the pull-down connection, use

of a resistor with a resistance ranging from 470 Ω to 10 kΩ is recommended.

Caution Connect the AV

SS pin to VSS0.

Remark When using in applications where noise from inside the microcomputer has to be reduced, it is

recommended to take countermeasures against noise such as supplying power to V

DD0 and VDD1

independently, and connecting VSS0 and VSS1 to different ground lines.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

A8 to A19 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ANO0, ANO1 : Analog Output ASCK1, ASCK2 : Asynchronous Serial Clock ASTB : Address Strobe

DD : Analog Power Supply

AV AVREF1 : Analog Reference Voltage

SS : Analog Ground

AV BUZ : Buzzer Clock EXA : External Access Status Output INTP0 to INTP5 : Interrupt from Peripherals NMI : Non-maskable Interrupt P00 to P05 : Port0 P10 to P17 : Port1 P20 to P27 : Port2 P30 to P37 : Port3 P40 to P47 : Port4 P50 to P57 : Port5 P60 to P67 : Port6 P70 to P72 : Port7 P120 to P127 : Port12

P130, P131 : Port13 PCL : Programmable Clock RD : Read Strobe RESET : Reset RTP0 to RTP7 : Real-time Output Port RxD1, RxD2 : Receive Data SCK0 to SCK2 : Serial Clock SCL0 SDA0

Note

: Serial Clock

: Serial Data SI0 to SI2 : Serial Input SO0 to SO2 : Serial Output TEST : Test TI00, TI01, TI1, TI2 : Timer Input TO0 to TO2 : Timer Output TxD1, TxD2 : Transmit Data

DD0, VDD1 : Power Supply

V VSS0, VSS1 : Ground WAIT : Wait WR : Write Strobe X1, X2 : Crystal (Main System Clock) XT1, XT2 : Crystal (Subsystem Clock)

Note The SCL0 and SDA0 pins are available in

PD784225Y Subseries only.

Data Sheet U12376EJ1V0DS00

4. BLOCK DIAGRAM

PD784224, 784225, 784224Y, 784225Y

INTP2/NMI

INTP0, INTP1,

INTP3 to INTP5

TI00 TI01

TO0

TI1

TO1

TI2

TO2

RTP0 to RTP7

NMI/INTP2

ANO0 ANO1

REF1

ANI0 to ANI7

AV AV

P03/INTP3

PCL

BUZ

PROGRAMMABLE INTERRUPT CONTROLLER

TIMER/EVENT

COUNTER

(16 BITS)

TIMER/EVENT

COUNTER1

(8 BITS)

TIMER/EVENT

COUNTER2

(8 BITS)

TIMER/COUNTER5

(8 BITS)

TIMER/COUNTER6

(8 BITS)

78K/IV

CPU CORE

UART/IOE1 BAUD-RATE GENERATOR

UART/IOE2 BAUD-RATE GENERATOR

CLOCKED SERIAL INTERFACE

BUS I/F

ROM

PORT0

RxD1/SI1 TxD1/SO1

ASCK1/SCK1 RxD2/SI2

TxD2/SO2 ASCK2/SCK2

SI0/SDA0

Note

SO0 SCK0/SCL0

AD0 to AD7 A8 to A15

A16 to A19 RD

WR WAIT ASTB

EXA

P00 to P05

Note

WATCH TIMER

PORT1 PORT2

WATCHDOG TIMER

RAM

REAL-TIME OUTPUT PORT

PORT3 PORT4 PORT5 PORT6

D/A CONVERTER

DD SS

A/D CONVERTER

PORT7 PORT12 PORT13

CLOCK OUTPUT CONTROL

SYSTEM CONTROL

P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67

P70 to P72 P120 to P127 P130, P131

RESET X1 X2 XT1

BUZZER OUTPUT

XT2 V

DD0

SS0

, V , V

DD1 SS1

TEST

Note This function supports the I2C bus interface and is available in µPD784225Y Subseries only.

Remark The internal ROM and RAM capacities differ depending on the model.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5. PIN FUNCTION

5.1 Port Pins (1/2)

Pin Name I/O Alternate Function Function P00 I/O INTP0 P01 INTP1 P02 INTP2/NM1 P03 INTP3 P04 INTP4 P05 INTP5 P10 to P17 Input ANI0 to ANI7

Port 0 (P0):

• 6-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistors by software bit-wise.

Port 1 (P1):

• 8-bit input port

P20 I/O RxD1/SI1 P21 TxD1/SO1 P22 ASCK1/SCK1 P23 PCL P24 BUZ P25 SI0/SDA0 P26 SO0 P27 SCK0/SCL0 P30 I/O TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 TI00 P36 TI01 P37 EXA P40 to P47 I/O AD0 to AD7 Port 4 (P4):

P50 to P57 I/O A8 to A15 Port 5 (P5):

Note

Port 2 (P2):

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistors by software bit-wise.

Port 3 (P3):

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistors by software bit-wise.

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• All pins set in input mode can be connected to internal pull-up resistors by software.

• Can drive LEDs.

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• All pins set in input mode can be connected to internal pull-up resistors by software.

• Can drive LEDs.

Note This function is available in µPD784255Y Subseries only.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5.1 Port Pins (2/2)

Pin Name I/O Alternate Function Function P60 I/O A16 P61 A17 P62 A18 P63 A19 P64 RD P65 WR P66 WAIT P67 ASTB P70 I/O RxD2/SI2

P71 TxD2/SO2

P72 ASCK2/SCK2

Port 6 (P6):

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• All pins set in input mode can be connected to internal pull-up resistors by software.

Port 7 (P7):

• 3-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistor by software bit-wise.

P120 to P127 I/O RTP0 to RTP7 Port 12 (P12):

• 8-bit I/O port

• Can be set in input or output mode bit-wise.

• Pins set in input mode can be connected to internal pull-up resistor by software bit-wise.

P130, P131 I/O ANO0, ANO1 Port 13 (P13):

• 2-bit I/O port

• Can be set in input or output mode bit-wise.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5.2 Pins Other Than Port Pins (1/2)

Pin Name I/O Alternate Function Function TI00 Input P35 External count clock input to 16-bit timer register TI01 P36 Capture trigger signal input to capture/compare register 00 TI1 P33 External count clock input to 8-bit timer register 1 TI2 P34 External count clock input to 8-bit timer register 2 TO0 Output P30 16-bit timer output (shared by 14-bit PWM output) TO1 P31 8-bit timer output (shared by 8-bit PWM output) TO2 P32 RxD1 Input P20/SI1 Serial data input (UART1) RxD2 P70/SI2 Serial data input (UART2) TxD1 Output P21/SO1 Serial data output (UART1) TxD2 P71/SO2 Serial data output (UART2) ASCK1 Intput P22/SCK1 Baud rate clock input (UART1) ASCK2 P72/SCK2 Baud rate clock input (UART2) SI0 Input P25/SDA0 SI1 P20/RxD1 Serial data input (3-wire serial clock I/O1) SI2 P70/RxD2 Serial data input (3-wire serial clock I/O2) SO0 Output P26 Serial data output (3-wire serial I/O0) SO1 P21/TxD1 Serial data output (3-wire serial I/O1) SO2 P71/TxD2 Serial data output (3-wire serial I/O2)

Note

SDA0 SCK0 I/O P27/SCL0 SCK1 P22/ASCK1 Serial clock input/output (3-wire serial I/O1) SCK2 P72/ASCK2 Serial clock input/output (3-wire serial I/O2)

Note

SCL0 NMI Input P02/INTP2 Non-maskable interrupt request input INTP0 P00 External interrupt request input INTP1 P01 INTP2 P02/NMI INTP3 P03 INTP4 P04 INTP5 P05 PCL Output P23 Clock output (for trimming main system clock and subsystem clock) BUZ Output P24 Buzzer output RTP0 to RTP7

AD0 to AD7 I/O P40 to P47 Low-order address/data bus when external memory is connected A8 to A15 Output P50 to P57 Middle-order address bus when external memory is connected A16 to A19 P60 to P63 High-order address bus when external memory is connected

I/O P25/SI0 Serial data input/output (I2C bus)

P27/SCK0 Serial clock input/output (I2C bus)

Output P120 to P127 Real-time output port that outputs data in synchronization with

Note

Serial data input (3-wire serial clock I/O0)

Serial clock input/output (3-wire serial I/O0)

trigger

Note This function is available in µPD784255Y Subseries only.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5.2 Pins Other Than Port Pins (2/2)

Pin Name I/O Alternate Function Function RD Output P64 Strobe signal output for read operation of external memory WR P65 Strobe signal output for write operation of external memory WAIT Input P66 To insert wait state(s) when external memory is accessed ASTB Output P67 Strobe output to externally latch address information output to ports

4 to 6 to access external memory EXA Output P37 External access status output RESET Input − System reset input X1 Input − To connect main system clock oscillation crystal X2 − XT1 Input − To connect subsystem clock oscillation crystal XT2 − ANI0 to ANI7 Input P10 to P17 Analog voltage input for A/D converter ANO0, ANO1 Output P130, P131 Analog voltage output for D/A converter AVREF1 −−To apply reference voltage for D/A converter AVDD Positive power supply for A/D converter. Connected to VDD0. AVSS GND for A/D converter and D/A converter. Connected to VSS0. VDD0 Positive power supply for port block VSS0 GND potential for port block VDD1 Positive power supply (except port block) VSS1 GND potential (except port block) TEST Connect this pin to VSS0 directly or via pull-down resistor. For the

pull-down connection, use of a resistor with a resistance ranging

from 470 Ω to 10 kΩ is recommended.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins

Table 5-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection

of unused pins.

For the circuit diagram of each type of I/O circuit, refer to Figure 5-1.

Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)

Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins P00/INTP0 8-K I/O Input : Individually connected to VSS0 via resistor P01/INTP1 P02/INTP2/NMI P03/INTP3 to P05/INTP5 P10/ANI0 to P17/ANI7 9 Input Connected to VSS0 or VDD0 P20/RxD1/SI1 10-I I/O Input : Individually connected to VSS0 via resistor P21/TxD1/SO1 10-J P22/ASCK1/SCK1 10-I P23/PCL 10-J P24/BUZ P25/SDA0 P26/SO0 10-J P27/SCL0 P30/TO0 to P32/TO2 8-M P33/TI1, P34/TI2 8-K P35/TI00, P36/TI01 8-L P37/EXA 8-M P40/AD0 to P47/AD7 5-H P50/A8 to P57/A15 P60/A16 to P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 8-K P71/TxD2/SO2 8-L P72/ASCK2/SCK2 8-K

Note

/SI0 10-I

Note

/SCK0 10-I

Output: Open

Note This function is available in µPD784255Y Subseries only.

Remark Because the circuit type numbers are standardized among the 78K Series products, they are not

sequential in some models (i.e., some circuits are not provided).

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (2/2)

Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins P120/RTP0 to P127/RTP7 8-K I/O Input : Individually connected to VSS0 via resistor P130/ANO0, P131/ANO1 12-D RESET 2-G Input − XT1 16 Connected to VSS0 XT2 − Open AVREF1 − Connected to VDD0 AVDD AVSS Connected to VSS0 TEST/VPP

Note

Output: Open

Directly connected to VSS0

Note VPP pin is available in µPD78F4225, 78F4255Y only.

Remark Because the circuit type numbers are standardized among the 78K Series products, they are not

sequential in some models (i.e., some circuits are not provided).

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Figure 5-1. Types of Pin I/O Circuits (1/2)

Type 2-G

Schmitt trigger input with hysteresis characteristics

Type 5-H

pullup enable

data

output disable

SS0

DD0

P-ch

DD0

P-ch

N-ch

input enable

IN/OUT

Type 8-M

pullup enable

data

output disable

input enable

Type 9

P-ch

N-ch

DD0

P-ch

N-ch

SS0

Comparator

−

REF

(threshold voltage)

DD0

P-ch

IN/OUT

input enable

Type 8-K

pullup enable

data

output disable

Type 8-L

pullup

enable

data

open drain

output disable

DD0

Type 10-I

pullup

P-ch

DD0

P-ch

IN/OUT

N-ch

SS0

DD0

P-ch

DD0

P-ch

enable

data

open drain

output disable

Type 10-J

pullup

enable

data

IN/OUT

N-ch

SS0

open drain

output disable

SS0

DD0

P-ch

DD0

P-ch

IN/OUT

N-ch

DD0

P-ch

DD0

P-ch

IN/OUT

N-ch

Data Sheet U12376EJ1V0DS00

Type 12-D

data

output disable

input enable

Type 16

Analog output voltage

feedback cut-off

P-ch

VSS0 P-ch

N-ch

PD784224, 784225, 784224Y, 784225Y

Figure 5-1. Types of Pin I/O Circuits (2/2)

DD0

P-ch

IN/OUT

N-ch

VSS0

XT1 XT2

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

6. CPU ARCHITECTURE

6.1 Memory Space

A memory space of 1 Mbyte can be accessed. Mapping of the internal data area (special function registers and internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after RESET cancellation, and must not be used more than once.

(1) When LOCATION 0H instruction is executed

• Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number Internal Data Area Internal ROM Area

PD784224, 0F100H to 0FFFFH 00000H to 0F0FFH

PD784224Y 10000H to 17FFFH

PD784225, 0EE00H to 0FFFFH 00000H to 0EDFFH

PD784225Y 10000H to 1FFFFH

Caution The following areas that overlap the internal data area of the internal ROM cannot be used when

the LOCATION 0H instruction is executed.

Part Number Unusable Area

PD784224, 0F100H to 0FFFFH (3,840 bytes)

PD784224Y

PD784225, 0EE00H to 0FFFFH (4,608 bytes)

PD784225Y

• External memory

The external memory is accessed in external memory expansion mode.

(2) When LOCATION 0FH instruction is executed

• Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number Internal Data Area Internal ROM Area

PD784224, FF100H to FFFFFH 00000H to 17FFFH

PD784224Y

PD784225, FEE00H to FFFFFH 00000H to 1FFFFH

PD784225Y

• External memory

The external memory is accessed in external memory expansion mode.

Data Sheet U12376EJ1V0DS00

(256 bytes)

Internal RAM

On execution of

Note 1

Special function registers (SFR)

LOCATION 0FH instruction

HFFFFF

HFDFFF

H0DFFF

H00FFF

(3,584 bytes)

HFFEFF

PD784224, 784225, 784224Y, 784225Y

Note 4

Note 1

Internal ROM

External memory

(980,736 bytes)

HFFF71

HFF0FF

H001FF

H00081

(96 Kbytes)

H00000

HFFEFF

PD784224, 784224Y

HFFEF0

H08EFF

HF7EFF

General-purpose

registers (128 bytes)

H08EF0

Figure 6-1. Memory Map of

Note 1

On execution of

LOCATION 0H instruction

HFFFFF

External memory

(928 Kbytes)

HF7EF0

Internal ROM

H00081

HFFF71

H93EFF

H60EFF

H00DFF

HFFCFF

H007FF

Program/data area

H00DF0

HFFCF0

(3,072 bytes)

H001F0

Data area (512 bytes)

Macro service control word

area (52 bytes)

H93EF0

H60EF0

(256 bytes)

(32,768 bytes)

Internal RAM

(3,584 bytes)

Note 1

Special function registers (SFR)

H00001

HFFFF0

HFDFF0

H0DFF0

H00FF0

HFFEF0

H001F0

HFFF71

Note 3

Note 2

CALLF entry

H00010

HFFF00

area (2 Kbytes)

H00800

HFF700

Internal ROM

(61,696 bytes)

CALLT table

area (64 bytes)

H08000

HF7000

H04000

Vector table area

(64 bytes)

HF3000

H00000

Program/data area

HFF0F0

H00001

HFFF71

Note 4

HFF0F0

Data Sheet U12376EJ1V0DS00

2. This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Notes 1. Accessed in external memory expansion mode.

(256 bytes)

Internal RAM

On execution of

Note 1

Special function registers (SFR)

LOCATION 0FH instruction

HFFFFF

HFDFFF

H0DFFF

H00FFF

(4,352 bytes)

HFFEFF

PD784224, 784225, 784224Y, 784225Y

Note 4

Note 1

Internal ROM

External memory

(912,896 bytes)

HFFFF1

HFFDEF

H00EEF

H00002

(128 Kbytes)

H00000

HFFEFF

PD784225, 784225Y

HFFEF0

H08EFF

HF7EFF

General-purpose

registers (128 bytes)

H08EF0

HF7EF0

Figure 6-2. Memory Map of

Note 1

On execution of

LOCATION 0H instruction

HFFFFF

External memory

(896 Kbytes)

H00002

H93EFF

H60EFF

H00DFF

HFFCFF

Macro service control word

H93EF0

Internal ROM

(65,536 bytes)

Data area (512 bytes)

area (52 bytes)

H00DF0

H60EF0

HFFCF0

(256 bytes)

Internal RAM

Note 1

Special function registers (SFR)

H00001

HFFFF1

HFFFF0

HFDFF0

H0DFF0

H00FF0

HFFEF0

HFFFF1

H00EEF

Note 2

Program/data area

(3,840 bytes)

H00001

HFFFF1

H00EE0

(4,352 bytes)

H00EE0

HFFDE0

Note 3

CALLF entry

H00010

HFFF00

Internal ROM

area (2 Kbytes)

(60,928 bytes)

Program/data area

HFFDE0

Note 4

CALLT table

area (64 bytes)

Vector table area

H00800

HFF700

H08000

HF7000

H04000

HF3000

(64 bytes)

H00000

Data Sheet U12376EJ1V0DS00

2. This 4,608-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 126,464 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Notes 1. Accessed in external memory expansion mode.

(

PD784224, 784225, 784224Y, 784225Y

6.2 CPU Registers

6.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register. Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address specification registers.

Eight banks of these registers are available which can be selected by using software or the context switching function.

The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM.

Figure 6-3. General-Purpose Register Format

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

Parentheses

A (R1)

AX (RP0)

B (R3)

BC (RP1)

VP (RP4)

R11

UP (RP5)

D (R13)

DE (RP6)

H (R15)

HL (RP7)

) indicate an absolute name.

X (R0)

C (R2)

RP2

RP3

R10

E (R12)

L (R14)

8 banks

Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of the 78K/III Series.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

6.2.2 Control registers

(1) Program counter (PC)

The program counter is a 20-bit register whose contents are automatically updated when the program is executed.

Figure 6-4. Program Counter (PC) Format

19 0

(2) Program status word (PSW)

This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed.

Figure 6-5. Program Status Word (PSW) Format

15 14 13 12 11 10 9 8

UF RBS2 RBS1 RBS0 – – – –PSWH

PSW

76543210 S Z RSS

Note

AC IE P/V 0 CYPSWL

Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except

when the software for the 78K/III Series is used.

(3) Stack pointer (SP)

This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this pointer.

Figure 6-6. Stack Pointer (SP) Format

23 0

0000

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

6.2.3 Special function registers (SFRs)

The special function registers, such as the mode registers and control registers of the internal peripheral

hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space

Note

of addresses 0FF00H to 0FFFFH

Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH

instruction.

Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed

by mistake, the only by inputting the RESET signal.

Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

• Symbol ............................... Symbol indicating an SFR. This symbol is reserved for NEC’s assembler

PD784225 may be in the deadlock status. This deadlock status can be cleared

(RA78K4). It can be used an sfr variable by the #pragma sfr directive with the C compiler (CC78K4).

• R/ W .................................... Indicates whether the SFR is read-only, write-only, or read/write.

R/W : Read/write R : Read-only W : Write-only

• Bit units for manipulation.. Bit units in which the value of the SFR can be manipulated.

SFRs that can be manipulated in 16-bit units can be described as the operand sfrp of an instruction. To specify the address of this SFR, describe an even address. SFRs that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction.

• At reset .............................. Indicates the status of the register when the RESET signal has been input.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (1/4)

Address

Note 1

0FF00H Port 0 P0 R/W — 00H 0FF01H Port 1 P1 R — 0FF02H Port 2 P2 R/W — 0FF03H Port 3 P3 — 0FF04H Port 4 P4 — 0FF05H Port 5 P5 — 0FF06H Port 6 P6 — 0FF07H Port 7 P7 — 0FF0CH Port 12 P12 — 0FF0DH Port 13 P13 — 0FF10H 16-bit timer counter TM0 R — — 0000H 0FF11H 0FF12H Capture/compare register 00 CR00 R/W — — 0FF13H 0FF14H Capture/compare register 01 CR01 — — 0FF15H 0FF16H Capture/compare control register 0 CRC0 — 00H 0FF18H 16-bit timer mode control register TMC0 — 0FF1AH 16-bit timer output control register TOC0 — 0FF1CH Prescaler mode register 0 PRM0 — 0FF20H Port 0 mode register PM0 — FFH 0FF22H Port 2 mode register PM2 — 0FF23H Port 3 mode register PM3 — 0FF24H Port 4 mode register PM4 — 0FF25H Port 5 mode register PM5 — 0FF26H Port 6 mode register PM6 — 0FF27H Port 7 mode register PM7 — 0FF2CH Port 12 mode register PM12 — 0FF2DH Port 13 mode register PM13 — 0FF30H Pull-up resistor option register 0 PU0 — 00H 0FF32H Pull-up resistor option register 2 PU2 — 0FF33H Pull-up resistor option register 3 PU3 — 0FF37H Pull-up resistor option register 7 PU7 — 0FF3CH Pull-up resistor option register 12 PU12 — 0FF40H Clock output control register CKS —

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation At Reset

1 Bit 8 Bits 16 Bits

(16-bit timer/counter)

Note 2

Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

2. Because each port is initialized to input mode at reset, “00H” is not actually read. The output latch is initialized to “0”.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (2/4)

Note

Address

0FF42H Port function control register PF2 R/W — 00H 0FF4EH Pull-up resistor option register PUO — 0FF50H 8-bit timer counter 1 0FF51H 8-bit timer counter 2 0FF52H Compare register 10 (8-bit timer/counter 1) 0FF53H Compare register 20 (8-bit timer/counter 2) 0FF54H 8-bit timer mode control register 1 0FF55H 8-bit timer mode control register 2 0FF56H Prescaler mode register 1 0FF57H Prescaler mode register 2 0FF60H 8-bit timer counter 5 TM5 0FF61H 8-bit timer counter 6 TM6 — 0FF64H Compare register 50 (8-bit timer/counter 5) 0FF65H Compare register 60 (8-bit timer/counter 6) 0FF68H 8-bit timer mode control register 5 0FF69H 8-bit timer mode control register 6 0FF6CH Prescaler mode register 5 0FF6DH Prescaler mode register 6 0FF70H 0FF71H 0FF72H 0FF73H 0FF74H Transmit shift register 1 TXS1 W — — FFH

0FF75H Transmit shift register 2 TXS2 W — —

0FF76H Baud rate generator control register 1 BRGC1 R/W — 00H 0FF77H Baud rate generator control register 2 BRGC2 — 0FF7AH Oscillation mode select register CC — 0FF80H A/D converter mode register ADM — 0FF81H A/D converter input select register ADIS — 0FF83H A/D conversion result register ADCR R — — Undefined 0FF84H D/A conversion value setting register 0 DACS0 R/W — 00H 0FF85H D/A conversion value setting register 1 DACS1 — 0FF86H D/A converter mode register 0 DAM0 — 0FF87H D/A converter mode register 1 DAM1 —

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation At Reset

1 Bit 8 Bits 16 Bits

TM1 TM1W TM2 CR10 CR1W CR20 TMC1 TMC2 PRM1 PRM2

CR50 CR5W CR60 TMC5 TMC6 PRM5

PRM6 Asynchronous serial interface mode register 1 Asynchronous serial interface mode register 2 Asynchronous serial interface status register 1 Asynchronous serial interface status register 2

Receive buffer register 1 RXB1 R — —

Receive buffer register 2 RXB2 R — —

ASIM1 — 00H ASIM2 — ASIS1 R — ASIS2 —

R— 0000H

—

R/W —

—

TMC1W

PRM1W

TM5W

R—

R/W —

—

TMC5W

PRM5W

Note When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (3/4)

Address

Note 1

0FF88H ROM correction control register CORC R/W — 00H 0FF89H ROM correction address pointer H CORAH — — 0FF8AH ROM correction address pointer L CORAL — — 0000H 0FF8BH 0FF8DH External access status enable register EXAE — 00H 0FF90H Serial operation mode register 0 CSIM0 — 0FF91H Serial operation mode register 1 CSIM1 — 0FF92H Serial operation mode register 2 CSIM2 — 0FF94H Serial I/O shift register 0 SIO0 — — 0FF95H Serial I/O shift register 1 SIO1 — — 0FF96H Serial I/O shift register 2 SIO2 — — 0FF98H Real-time output buffer register L RTBL — — 0FF99H Real-time output buffer register H RTBH — — 0FF9AH Real-time output port mode register RTPM — 0FF9BH Real-time output port control register RTPC — 0FF9CH Watch timer mode control register WTM — 0FFA0H 0FFA2H 0FFA8H In-service priority register ISPR R — 0FFA9H Interrupt select control register SNMI R/W — 0FFAAH Interrupt mode control register IMC — 80H 0FFACH Interrupt mask flag register 0L 0FFADH Interrupt mask flag register 0H 0FFAEH Interrupt mask flag register 1L 0FFAFH Interrupt mask flag register 1H 0FFB0H I2C bus control register 0FFB2H Prescaler mode register for serial clock SPRM0 — 0FFB4H Slave address register SVA0 — 0FFB6H I2C bus status register 0FFB8H Serial shift register IIC0 R/W — 0FFC0H Standby control register STBC — — 30H 0FFC2H Watchdog timer mode register WDM — — 00H 0FFC4H Memory expansion mode register MM — 20H 0FFC7H Programmable wait control register 1 PWC1 — AAH 0FFC8H Programmable wait control register 2 PWC2 W — — AAAAH 00FFCEH Clock status register PCS R — 32H 0FFCFH 0FFD0H to External SFR area — — —

0FFDFH

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation At Reset

1 Bit 8 Bits 16 Bits

External interrupt rising edge enable register External interrupt falling edge enable register

Note 2

Oscillation stabilization time specification register

EGP0 — EGN0 —

MK0L MK0 MK0H MK1L MK1 MK1H

IICCL0 — 00H

IICS0 R —

OSTS R/W — 00H

FFFFH

Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

PD784225Y Subseries only

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 6-1. Special Function Register (SFR) List (4/4)

Note

Address

0FFE0H Interrupt control register (INTWDTM) WDTIC R/W — 43H 0FFE1H Interrupt control register (INTP0) PIC0 — 0FFE2H Interrupt control register (INTP1) PIC1 — 0FFE3H Interrupt control register (INTP2) PIC2 — 0FFE4H Interrupt control register (INTP3) PIC3 — 0FFE5H Interrupt control register (INTP4) PIC4 — 0FFE6H Interrupt control register (INTP5) PIC5 — 0FFE8H Interrupt control register (INTIIC0/INTCSI0) CSIIC0 — 0FFE9H Interrupt control register (INTSER1) SERIC1 — 0FFEAH Interrupt control register (INTSR1/INTCSI1) SRIC1 — 0FFEBH Interrupt control register (INTST1) STIC1 — 0FFECH Interrupt control register (INTSER2) SERIC2 — 0FFEDH Interrupt control register (INTSR2/INTCSI2) SRIC2 — 0FFEEH Interrupt control register (INTST2) STIC2 — 0FFEFH Interrupt control register (INTTM3) TMIC3 — 0FFF0H Interrupt control register (INTTM00) TMIC00 — 0FFF1H Interrupt control register (INTTM01) TMIC01 — 0FFF2H Interrupt control register (INTTM1) TMIC1 — 0FFF3H Interrupt control register (INTTM2) TMIC2 — 0FFF4H Interrupt control register (INTAD) ADIC — 0FFF5H Interrupt control register (INTTM5) TMIC5 — 0FFF6H Interrupt control register (INTTM6) TMIC6 — 0FFF9H Interrupt control register (INTWT) WTIC —

Special Function Register (SFR) Name Symbol R/W Bit Units for Manipulation At Reset

1 Bit 8 Bits 16 Bits

Note When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH

instruction is executed.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7. PERIPHERAL HARDWARE FUNCTIONS

7.1 Ports

The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the

function of each port. Ports 0, 2 to 7, and 12 can be connected to internal pull-up resistors by software when inputting.

Figure 7-1. Port Configuration

Port 5

Port 6

Port 7

Port 12

Port 13

      

  

      

  

P50

P57 P60

P67 P70

P72 P120

P127 P130

P131

P00

P05

P10 to P17

P20

P27 P30

P37 P40

P47

   

Port 0

  

Port 1

  

Port 2

   

  

Port 3

   

  

Port 4

   

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 7-1. Port Functions

Port Name Pin Name Function Specification of Pull-up Resistor

Connection by Software Port 0 P00 to P05 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 1 P10 to P17 • Input port — Port 2 P20 to P27 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 3 P30 to P37 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 4 P40 to P47 • Can be set in input or output mode bit-wise Can be specified in 1-port units

• Can directly drive LEDs

Port 5 P50 to P57 • Can be set in input or output mode bit-wise Can be specified in 1-port units

• Can directly drive LEDs Port 6 P60 to P67 • Can be set in input or output mode bit-wise Can be specified in 1-port units Port 7 P70 to P72 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 12 P120 to P127 • Can be set in input or output mode bit-wise Can be specified bit-wise Port 13 P130, P131 • Can be set in input or output mode bit-wise —

7.2 Clock Generator

An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider. If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to reduce the current consumption.

Figure 7-2. Block Diagram of Clock Generator

XT1

XT2

Subsystem

clock

oscillator

Main system

clock

oscillator

IDLE

controller

STOP and bit 2 (MCK) of the standby control register (STBC) = 1 when the subsystem clock is selected as CPU clock

Frequency

divider

f 2

Selector

Prescaler

Watch timer, clock output function

Prescaler

Clock to peripheral hardware

Selector

STOP,

IDLE

controller

HALT

controller

CPU clock (f

CPU

)

Data Sheet U12376EJ1V0DS00

Internal system clock

CLK

)

PD784224, 784225, 784224Y, 784225Y

Figure 7-3. Example of Using Main System Clock Oscillator

(1) Crystal/ceramic oscillation (2) External clock

VSS1

Crystal resorator or ceramic resonator

X1 VSS

External clock

PD74HCU04

Figure 7-4. Example of Using Subsystem Clock Oscillator

(1) Crystal oscillation (2) External clock

XT2

32.768 kHz

SS1

XT1

External clock

PD74HCU04

XT2

XT1

Caution When using the main system clock and subsystem clock oscillator, wire the dotted portions in

Figures 7-3 and 7-4 as follows to avoid adverse influence from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring in the vicinity of lines through which a high alternating current flows.

• Always keep the potential at the ground point of the capacitor in the oscillator the same as

SS1. Do not ground to a ground pattern through which a high current flows.

• Do not extract signals from the oscillator.

Note that the subsystem clock oscillator has a low amplification factor to reduce the current consumption.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7.3 Real-Time Output Port

The real-time output function is to transfer data set in advance to the real-time output buffer register to the output latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device. The pins that output the data to the external device constitute a port called a real-time output port.

Because the real-time output port can output signals without jitter, it is ideal for controlling a stepping motor.

Figure 7-5. Block Diagram of Real-Time Output Port

Internal bus

Real-time output port control register (RTPC)

RTPOE BYTE EXTR

INTP2TRG

INTTM1 INTTM2

Output trigger

controller

Port 12 output latch

P127······································ P120

Higher 4 bits of

real-time output

buffer register

(RTBH)

Real-time output port output latch

RTP7······································ RTP0

Lower 4 bits of

real-time output

buffer register

(RTBL)

Real-time output

port mode register

(RTPM)

RTPOE bit

P12n/RTPn pin output (n = 0 to 7)

P127/ P120/

······································

RTP7 RTP0

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7.4 Timer

One unit of 16-bit timers/event counters, two units of timers/event counters, and two 8-bit timers are provided. Because a total of six interrupt requests are supported, these timers/counters and timer can be used as six units

of timers/counters.

Table 7-2. Operations of Timers

Name 16-Bit 8-Bit 8-Bit 8-Bit 8-Bit

Timer/Event Timer/Event Timer/Event

Item Counter Counter 1 Counter 2 Count width 8 bits —

16 bits

Operation mode Interval timer 1ch 1ch 1ch 1ch 1ch

External event counter ——

Function Timer output 1ch 1ch 1ch — —

PPG output ———— PWM output —— Square wave output ——

One-shot pulse output ———— Pulse width measurement 2 inputs ———— Number of interrupt requests 21111

Timer 5 Timer 6

Data Sheet U12376EJ1V0DS00

16-bit timer/event counter

PD784224, 784225, 784224Y, 784225Y

Figure 7-6. Block Diagram of Timers (1/2)

fXX/4

/16

INTTM3

TI01

TI00

Edge detector

8-bit timer/event counter 1

fXX/2

TI1

Edge detector

SelectorSelector

Selector

Clear

16-bit timer counter (TM0)

16-bit capture/compare register 00

(CR00)

16-bit capture/compare register 01

(CR01)

Clear

8-bit timer counter 1

(TM1)

8-bit compare register 10

(CR10)

INTTM2

OVF

INTTM00

INTTM01

Selector

Output controller

Output

controller

INTTM1

TO0

TO1

8-bit timer/event counter 2

TM1

fXX/2

TI2

Edge detector

Remark OVF: Overflow flag

Selector

Clear

8-bit timer counter 2

(TM2)

8-bit compare register 20

(CR20)

Data Sheet U12376EJ1V0DS00

OVF

Output

controller

INTTM2

TO2

8-bit timer 5

8-bit timer 6

fXX/2 fXX/2 fXX/2

fXX/2 fXX/2

fXX/2

PD784224, 784225, 784224Y, 784225Y

Figure 7-6. Block Diagram of Timers (2/2)

(TM5)

(CR50)

Clear

INTTM5

Selector

INTTM6

Selector

8-bit timer counter 5

8-bit compare register 50

TM5

fXX/2 fXX/2 fXX/2 fXX/2

fXX/2 fXX/2

Selector

8-bit timer counter 6

8-bit compare register 60

(TM6)

(CR60)

Clear

INTTM6

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7.5 A/D Converter

An A/D converter converts an analog input variable into a digital signal. This microcontroller is provided with

an A/D converter with a resolution of 8 bits and 8 channels (ANI0 to ANI7).

This A/D converter is of successive approximation type and the result of conversion is stored to an 8-bit A/D

conversion result register (ADCR).

The A/D converter can be started in the following two ways:

• Hardware start Conversion is started by trigger input (P03).

• Software start Conversion is started by setting the A/D converter mode register.

One analog input channel is selected from ANI0 to ANI7 for A/D conversion. When A/D conversion is started by means of hardware start, conversion is stopped after it has been completed. When conversion is started by means of software start, A/D conversion is repeatedly executed, and each time conversion has been completed, an interrupt request (INTAD) is generated.

Figure 7-7. Block Diagram of A/D Converter

Series resistor string

ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7

INTP3/P03 INTAD

Selector

Edge

detector

Edge

detector

Sample & hold circuit

Voltage comparator

Tap selector

Successive approximation register (SAR)

Controller

A/D conversion result register

(ADCR)

Internal bus

AVDD

INTP3

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7.6 D/A Converter

A D/A converter converts an input digital signal into an analog voltage. This microcontroller is provided with a

voltage output type D/A converter with a resolution of 8 bits and two channels.

The conversion method is of R-2R resistor ladder type. D/A conversion is started by setting DACE0 of the D/A converter mode register 0 (DAM0) and DACE1 of the D/

A converter mode register 1 (DAM1).

The D/A converter operates in the following two modes:

• Normal mode The converter outputs an analog voltage immediately after it has completed D/A conversion.

• Real-time output mode The converter outputs an analog voltage in synchronization with an output trigger after it has completed D/A conversion.

Figure 7-8. Block Diagram of D/A Converter

DACS0

REF1

Selector

ANO0

DACS1

Selector

ANO1

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7.7 Serial Interface

Three independent serial interface channels are provided.

• Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2

• Clocked serial interface (CSI) × 1

• 3-wire serial I/O (IOE)

C bus interface (I2C) (µPD784225Y Subseries only)

•I

Therefore, communication with an external system and local communication within the system can be simultaneously

executed (see Figure 7-9).

Figure 7-9. Example of Serial Interface

DD0

PD780078Y (slave)

SDA SCL

PD780308Y (slave)

PD4711A

RS-232C

driver/receiver

PD784225Y (master)

[UART]

RxD1 TxD1



Port

 

SDA0

SCL0

(a) UART + I

PD4711A

RS-232C

driver/receiver

Note Handshake line

[UART]

PD4711A

RS-232C

RxD2 TxD2



Port

 

[UART]

(b) UART + 3-wire serial I/O

PD784225Y (master)

SO1

RxD2 TxD2



Port

 

SI1

SCK1

INTPm

Port

SDA SCL

[3-wise serial I/O]

Note

PD753106 (slave)

SI SO SCK Port INT

LCD

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O

mode are provided.

(1) Asynchronous serial interface mode

In this mode, data of 1 byte following the start bit is transferred or received. Because an on-chip baud rate generator is provided, a wide range of baud rates can be set. Moreover, the clock input to the ASCK pin can be divided to define a baud rate. When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also obtained.

Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode

Internal bus

Receive buffer register

1, 2 (RXB1, RXB2)

RxD1, RxD2

TxD1, TxD2

ASCK1, ASCK2

Baud rate generator

Receive shift register

1, 2 (RX1, RX2)

Receive control

parity check

Transmit/receive clock generation

Transmit shift register

1, 2 (TXS1, TXS2)

INTSR1, INTSR2

5-bit counter × 2

Transmit control

parity addition

Selector

INTST1, INTST2

fXX to fXX/2

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

(2) 3-wire serial I/O mode

In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in synchronization with this clock. This mode is used to communicate with a device having the conventional clocked serial interface. Basically, communication is established by using three lines: serial clocks (SCK1 and SCK2), serial data inputs (SI1 and SI2), and serial data outputs (SO1 and SO2). To connect two or more devices, a handshake line is necessary.

Figure 7-11. Block Diagram in 3-wire Serial I/O Mode

Internal bus

Direction controller

SI1, SI2

SO1, SO2

Serial I/O shift register 1, 2 (SIO1, SIO2)

SCK1, SCK2

Serial clock counter

Serial clock controller

Interrupt generator

Selector

INTCSI1, INTCSI2

TO2

f fXX/16

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7.7.2 Clocked serial interface (CSI)

In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data

in synchronization with this clock.

(1) 3-wire serial I/O mode

This mode is to communicate with devices having the conventional clocked serial interface. Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data (SI0 and SO0) lines. Generally, a handshake line is necessary to check the reception status.

Figure 7-12. Block Diagram in 3-Wise Serial I/O Mode

Internal bus

Direction controller

SI0

Serial I/O shift register 0

(SIO0)

SO0

SCK0

Serial clock counter

Serial clock controller

Interrupt generator

Selector

INTCSI0

TO2

f fXX/16

(2) I2C (Inter IC) bus mode (supporting multi-master) (µPD784225Y Subseries only)

This mode is to communicate with devices conforming to the I2C bus format. This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL0) and serial data bus (SDA0). During transfer, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus. During reception, these data can be automatically detected by hardware.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Figure 7-13. Block Diagram in I2C Bus Mode

Internal bus

Direction controller

Slave address register

(SVA0)

SDA0

Serial I/O shift register 0 (SIO0)

Start condition/ acknowledge detector

Output latch

Stop condition detector

SCL0

Serial clock counter

Serial clock controller

7.8 Clock Output Function

Clocks of the following frequencies can be output.

• 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 MHz (main system clock: 12.5 MHz)

• 32.768 kHz (subsystem clock: 32.768 kHz)

Interrupt generator

Selector

Wakeup controller

Acknowledge generator

INTIIC0

TO2/18 to TO2/68 f

/24 to fXX/178

fXX/2

fXX/2 fXX/2 fXX/2 fXX/2 fXX/2

Figure 7-14. Block Diagram of Clock Output Function

Selector

Synchronizer

Output controller PCL

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

7.9 Buzzer Output Function

Clocks of the following frequencies can be output as buzzer output.

• 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (main system clock: 12.5 MHz)

Figure 7-15. Block Diagram of Buzzer Output Function

fXX/2

fXX/2 fXX/2 fXX/2

Selector

Output controller

BUZ

7.10 Edge Detection Function

The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 to INTP5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise.

Pin Name Detectable Edge Noise Reduction NMI Either or both of rising and falling edges By analog delay INTP0 to INTP5 —

7.11 Watch Timer

The watch timer has the following functions:

• Watch timer

• Interval timer

The watch timer and interval timer functions can be used at the same time.

(1) Watch timer

The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds by using the 32.768-kHz subsystem clock.

(2) Interval timer

The interval timer generates an interrupt request (INTTM3) at predetermined time intervals.

Data Sheet U12376EJ1V0DS00

fXX/2

Prescaler

5-bit counter

INTWT

INTTM3

To 16-bit timer/counter

Selector

PD784224, 784225, 784224Y, 784225Y

Figure 7-16. Block Diagram of Watch Timer

7.12 Watchdog Timer

A watchdog timer is provided to detect a hang up of the CPU. This watchdog timer generates a non-maskable

or maskable interrupt unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be stopped by software. Whether the interrupt by the watchdog timer or the interrupt input from the NMI pin takes precedence can be specified.

Figure 7-17. Block Diagram of Watchdog Timer

Timer

RUN HALT IDLE STOP

CLK

Note

Note Write 1 to bit 7 (RUN) of the watchdog timer (WDM).

Remark f

CLK: Internal system clock (fXX to fXX/8)

CLK

INTWDT

Selector

CLK

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

8. INTERRUPT FUNCTION

As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by

program.

Table 8-1. Servicing of Interrupt Request

Servicing Mode Entity of Servicing Servicing Contents of PC and PSW

Vectored interrupt Software Branches and executes servicing routine Saves to and restores

(servicing is arbitrary). from stack.

Context switching Automatically switches register bank, Saves to or restores from

branches and executes servicing routine fixed area in register bank (servicing is arbitrary).

Macro service Firmware Executes data transfer between memory Retained

and I/O (servicing is fixed)

8.1 Interrupt Sources

Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 25 types of sources,

execution of the BRK instruction, BRKCS instruction, or an operand error.

The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service function is used, however, nesting always proceeds.

The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having the same request, simultaneously generate (see Table 8-2).

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Table 8-2. Interrupt Sources

Type

Software — BRK instruction Instruction execution — —

Non-maskable — NMI Pin input edge detection External —

Maskable 0 (

Default Priority

highest

) INTWDTM Overflow of watchdog timer Internal 1 INTP0 Pin input edge detection External 2 INTP1 3 INTP2 4 INTP3 5 INTP4 6 INTP5 7 INTIIC0

8 INTSER1 Occurrence of UART reception error in ASI1 9 INTSR1 End of UART reception by ASI1

10 INTST1 End of UART transfer by ASI1 11 INTSER2 Occurrence of UART reception error in ASI2 12 INTSR2 End of UART reception by ASI2

13 INTST2 End of UART transfer by ASI2 14 INTTM3 15 INTTM00 Signal indicating coincidence between 16-bit

16 INTTM01 Signal indicating coincidence between 16-bit

17 INTTM1 Occurrence of coincidence signal of 8-bit

18 INTTM2 Occurrence of coincidence signal of 8-bit

19 INTAD End of conversion by A/D converter 20 INTTM5 Occurrence of coincidence signal of 8-bit

21 INTTM6 Occurrence of coincidence signal of 8-bit

(lowest)

Name Trigger

BRKCS instruction Instruction execution Operand error If result of exclusive OR between operands

INTWDT Overflow of watchdog timer Internal

Note

INTCSI0 End of 3-wire transfer by CSI0

INTCSI1 End of 3-wire transfer by CSI1

INTCSI2 End of 3-wire transfer by CSI2

INTWT Overflow of watch timer

Source

byte and byte is not FFH when MOV STBC, #byte instruction or MOV WDM, #byte instruction, LOCATION instruction is executed

End of I2C bus transfer by CSI0 Internal

Reference time interval signal from watch timer

timer counter and capture/compare register (CR00)

timer counter and capture/compare register (CR01)

timer/counter 1

timer/counter 2

timer/counter 5

timer/counter 6

Internal/ Macro External Service

NoteµPD784255Y Subseries only

Remarks 1. ASI : Asynchronous Serial Interface

CSI: Clocked Serial Interface

2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and maskable interrupts (INTWDTM). Either one (but not both) should be selected for actual use.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

8.2 Vectored Interrupt

Execution branches to a servicing routing by using the memory contents of a vector table address corresponding

to the interrupt source as the address of the branch destination.

So that the CPU performs interrupt servicing, the following operations are performed:

• On branching: Saves the status of the CPU (contents of PC and PSW) to stack

• On returning : Restores the status of the CPU (contents of PC and PSW) from stack

To return to the main routine from an interrupt service routine, the RETI instruction is used. The branch destination address is in a range of 0 to FFFFH.

Table 8-3. Vector Table Address

Interrupt Source Vector Table Address Interrupt Source Vector Table Address BRK instruction 003EH INTST1 001CH Operand error 003CH INTSER2 001EH NMI 0002H INSR2 0020H INTWDT ( INTWDTM (maskable) INTP0 0008H INTTM3 0024H INTP1 000AH INTTM00 0026H INTP2 000CH INTTM01 0028H INTP3 000EH INTTM1 002AH INTP4 0010H INTTM2 002CH INTP5 0012H INTAD 002EH INTIIC0 0016H INTTM5 00030H INTCSI0 INTTM6 0032H INTSER1 0018H INTWT 0038H INTSR1 001AH INTCSI1

non-maskable

) 0004H INTCSI2

0006H INTST2 0022H

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

8.3 Context Switching

When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the register bank.

The branch address is in a range of 0 to FFFFH.

Figure 8-1. Context Switching Operation When Interrupt Request Is Generated

0000B <7> Transfer

PC19 to PC16

<2> Save (bits 8 through 11 of temporary register)

<1> Save

PC15 to PC0

Temporary register

PSW

<6> Exchange

<5> Save

B R5 R7

V U T

UP D H

C R4 R6

E L

<3> Switching of register bank (RBS0 to RBS2 ← n)

<4> RSS ← 0 IE ← 0

(0 to 7)

8.4 Macro Service

This function is to transfer data between memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without loading it.

Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high speeds.

CPU

Internal bus

Figure 8-2. Macro Service

Read

Memory SFR

Write

Data Sheet U12376EJ1V0DS00

Macro service

controller

Write

Read

8.5 Application Example of Macro Service

(1) Transmission of serial interface

Transfer data storage buffer (memory)

PD784224, 784225, 784224Y, 784225Y

Data n

Data n − 1

Data 2 Data 1

Internal bus

TxD1, TxD2

Transmit shift register

Transfer control

TXS1, TXS2 (SFR)

INTST1, INTST2

Each time macro service request INTST1 and INTST2 are generated, the next transmit data is transferred from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the transmit data storage buffer has become empty), vectored interrupt request INTST1 and INTST2 are generated.

(2) Reception of serial interface

Receive data storage buffer (memory)

Data n

Data n − 1

Data 2 Data 1

Internal bus

RXB1, RXB2 (SFR)

INTSR1, INTSR2

RxD1, RxD2

Receive buffer register

Receive shift register

Reception control

Each time macro service request INTSR1 and INTSR2 are generated, the receive data is transferred from RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt request INTSR1 and INTSR2 are generated.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

9. LOCAL BUS INTERFACE

The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space of 1 Mbyte (refer to Figure 9-1).

Figure 9-1. Example of Local Bus Interface (Multiplexed bus)

PD784225

A8 to A19

DD1

Address latch

Address bus

SRAM

CS OE

WE I/O1 to I/O8

A0 to A19

Data bus

ASTB

AD0 to AD7

LE Q0 to Q7

D0 to D7

9.1 Memory Expansion

External program and data memory can be connected in two stages: 256 Kbytes and 1 Mbytes.

To connect the external memory, ports 4 to 6 are used.

The external memory is connected by using a time-division address/data bus. The number of ports used when the external memory is connected can be reduced in this mode.

9.2 Programmable Wait

Wait state(s) can be inserted to the memory space (00000H to FFFFFH) while the RD and WR signals are active.

In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address decode time.

9.3 External Access Status Function

An active low external access status signal is output from the P37/EXA pin. This signal notifies other devices connected to the external bus of the external access status, to disable data output to the external bus from other devices, or enables reception.

The external access status signal is output during external access.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

10. STANDBY FUNCTION

This function is to reduce the power consumption of the chip, and can be used in the following modes:

• HALT mode : Stops supply of the operating clock to the CPU. This mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption.

• IDLE mode : Stops the entire system with the oscillator continuing operation. The power consumption in this mode is close to that in the STOP mode. However, the time required to restore the normal program operation from this mode is almost the same as that from the HALT mode.

• STOP mode : Stops the main system clock and thereby to stop all the internal operations of the chip. Consequently, the power consumption is minimized with only leakage current flowing.

• Power-saving mode : The main system clock is stopped with the subsystem clock used as the system clock. The CPU can operate on the subsystem clock to reduce the current consumption.

• Power-saving HALT mode: This is a standby function in the power-saving mode and stops the operation clock of the CPU, to reduce the power consumption of the entire system.

• Power-saving IDLE mode : This is a standby function in the power-saving mode and stops the entire system except the oscillator, to reduce the power consumption of the entire system.

These modes are programmable. The macro service can be started from the HALT mode and power-saving HALT mode. After executing macro service processing, it returns to the HALT mode.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Figure 10-1. Transition of Standby Status

Macro

End of one processing

Macro service request

Power-

saving HALT

mode

(standby)

Power-saving HALT mode is set.

service

Interrupt request

Macro service request

End of one processing

End of macro service

saving mode

(operation on

Note 1

Power-

subsystem

clock)

Power-saving IDLE mode is set. NMI, INTP0 to INTP6 input,

Note 2

INTWT

saving IDLE

(standby)

Power-

mode

STOP

(standby)

Interrupt request of masked interrupt

Sets STOP mode

Interrupt request of masked interrupt

NMI, INTP0 to INTP6 input,

INTWT, key return interrupt

IDLE

(standby)

RESET input

Power-saving HALT mode is set.

Normal operation is restored.

Normal

operation

(operation on

main system

clock)

Sets HALT mode

RESET input

Sets IDLE mode

NMI, INTP0 to INTP6 input, INTWT,

key return interrupt

Interrupt request of masked interrupt

RESET input

Note 2

Interrupt request of masked interrupt

End of oscillation stabilization time

RESET input

Macro service request End of one processing

End of macro service

Interrupt request

HALT

(standby)

Macro

service

Macro service request

End of one processing

Interrupt request of masked interrupt

Note 2

Waits for

oscillation

stabilization

Notes 1. Only unmasked interrupt requests

2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87)

Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby

(HALT mode/STOP mode/IDLE mode).

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

11. RESET FUNCTION

When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset). During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the current consumption of the entire system can be reduced.

When the RESET signal goes high, the reset status is cleared, oscillation stabilization time (41.9 ms at 12.5 MHz) elapses, the contents of the reset vector table are set to the program counter (PC), execution branches to an address set to the PC, and program execution is started from that branch address. Therefore, the program can be reset and started from any address.

Figure 11-1. Oscillation of Main System Clock during Reset Period

Main system clock oscillator

Oscillation is unconditionally stopped during rest period

CLK

RESET input

Oscillation stabilization time

The RESET input pin has an analog delay noise eliminator to prevent malfunctioning due to noise.

Figure 11-2. Accepting Reset Signal

Time until the clock starts oscillation

Oscillation stabilization time

RESET input

Internal reset signal

Analog delay Analog delay

Analog delay

Internal clock

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

12. ROM CORRECTION

ROM correction is a function to replace part of the program in the internal ROM with a program in the internal

RAM.

By using the ROM correction function, instruction bugs found in the internal ROM can be avoided or the flow of

the program can be changed.

ROM correction can be used at up to four places in the internal ROM (program).

Figure 12-1. Block Diagram of ROM Correction

Program counter (PC)

Comparator

Correction address pointer n

Correction address registers

(CORAH, CORAL)

Remark n = 0 to 3, m = 0 or 1

Coincidence

Internal bus

Correction branch processing request signal (CALLT instruction)

CORENn CORCHm

ROM correction control register (CORC)

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

13. INSTRUCTION SET

(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA

Table 13-1. Instruction List by 8-Bit Addressing

Second Operand #byte A r saddr sfr !addr16 mem r3 [WHL+] n None

Note 2

r' saddr' !!addr24 [saddrp] PSWL [WHL–]

First Operand

(ADD)

Note 6

MOV (MOV) MOV MOV (MOV)

Note 6

(XCH) (XCH) XCH (XCH)

Note 1,6

(ADD)

Note 1

ADD

A (MOV) (MOV) MOV (MOV)

Note 1

ADD

(XCH) XCH (XCH)

(ADD)

Note 1

(ADD)

Note 1

r MOV (MOV) MOV MOV MOV MOV ROR

Note 1

ADD

(XCH) XCH XCH XCH XCH DIVUW

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

ADD

Note 1

[%saddrg]

Note 1

ADD

PSWH

(ADD)

Note 1

Note 3

MULU

INC

DEC

(ADD)

Note 6

MOV MOV INC

Note 1

ADD

Note 1

XCH DEC

Note 1

ADD

DBNZ

saddr MOV (MOV)

Note 1

ADD

sfr MOV MOV MOV PUSH

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

POP

CHKL

CHKLA

!addr16 MOV (MOV) MOV !!addr24 ADD

Note 1

mem MOV [saddrp] ADD

Note 1

[%saddrg] mem3 ROR4

ROL4

r3 MOV MOV PSWL PSWH

B, C DBNZ STBC, WDM MOV [TDE+] (MOV)

[TDE–] (ADD)

MOVM

Note 1

Note 4

MOVBK

Note 5

Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR.

4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM.

5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of

MOVBK.

6. The code length of some instructions having saddr2 as saddr in this combination is short.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as

rp)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 13-2. Instruction List by 16-Bit Addressing

Second Operand #word AX rp saddrp sfrp !addr16 mem [WHL+] byte n None

rp' saddrp' !!addr24 [saddrp]

First Operand

AX (MOVW) (MOVW) (MOVW)

Note 1

ADDW

(XCHW) (XCHW)

Note 1

(ADD)

(ADDW)

Note 1

(MOVW) (XCHW)

(ADDW)

Note 3

MOVW (MOVW) MOVW (MOVW)

Note 3

(XCHW) XCHW XCHW (XCHW)

Note 1,3

(ADDW)

Note 1

[%saddrg]

rp MOVW (MOVW) MOVW MOVW MOVW MOVW SHRW MULW

Note 1

ADDW

saddrp MOVW

ADDW

(XCHW) XCHW XCHW XCHW SHLW INCW

Note 1

(ADDW)

(MOVW)

(ADDW)

Note 1

Note 3

Note 1

ADDW

Note 1

ADDW

Note 1

ADDW

Note 1

MOVW MOVW INCW

Note 1

ADDW

XCHW DECW

Note 1

ADDW

DECW

sfrp MOVW MOVW MOVW PUSH

Note 1

ADDW

!addr16 MOVW (MOVW) MOVW

(ADDW)

Note 1

ADDW

Note 1

POP

MOVTBLW

!!addr24

mem MOVW [saddrp] [%saddrg]

Note 2

Note 4

PSW PUSH

SP ADDWG

SUBWG

post PUSH

PUSHU

POPU

[TDE+] (MOVW) SACW

byte MACW

MACSW

Notes 1. The operands of SUBW and CMPW are the same as that of ADDW.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The code length of some instructions having saddrp2 as saddrp in this combination is short.

4. The operands of MULUW and DIVUX are the same as that of MULW.

POP

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

(3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL

as rg)

MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP

Table 13-3. Instruction List by 24-Bit Addressing

Second Operand #imm24 WHL rg saddrg !!addr24 mem1

rg'

First Operand

WHL (MOVG) (MOVG) (MOVG) (MOVG) (MOVG) MOVG MOVG MOVG

(ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG

rg MOVG (MOVG) MOVG MOVG MOVG INCG

ADDG (ADDG) ADDG DECG

SUBG (SUBG) SUBG PUSH

saddrg (MOVG) MOVG

!!addr24 (MOVG) MOVG

mem1 MOVG

[%saddrg] MOVG

SP MOVG MOVG INCG

[%saddrg]

SP None

Note

POP

DECG

Note Either the second operand is not used, or the second operand is not an operand address.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

(4) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET

Table 13-4. Bit Manipulation Instructions

Second Operand CY saddr.bit sfr.bit /saddr.bit /sfr. bit None

A.bit X.bit /A.bit /X.bit PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit mem2.bit /mem2.bit

First Operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit

CY MOV1 AND1 NOT1

AND1 OR1 SET1 OR1 CLR1 XOR1

saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit

Note

Note Either the second operand is not used, or the second operand is not an

operand address.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

(5) Call and return/branch instructions

CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ

Table 13-5. Call and Return/Branch Instructions

Operand of Instruction $addr20 Address

Basic instruction BC

Compound instruction BF

$!addr20

!addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None

Note

CALL CALL CALL CALL CALL CALL CALL CALLF CALLF BRKCS BRK

BR BR BR BR BR BR BR BR RET

RETCS RETI RETCSB

BT BTCLR BFSET DBNZ

RETB

Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT,

BNH, and BH are the same as BC.

(6) Other instructions

ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

14. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter Symbol Conditions Ratings Unit

Supply voltage VDD0 −0.3 to +6.5 V

AVDD −0.3 to VDD0 + 0.3 V AVSS −0.3 to VSS0 + 0.3 V

AVREF1 D/A converter reference voltage input −0.3 to VDD0 + 0.3 V Input voltage VI −0.3 to VDD0 + 0.3 V Analog input voltage VAN Analog input pin AVSS − 0.3 to AVREF1 + 0.3 V Output voltage VO −0.3 to VDD + 0.3 V Output current, low IOL Per pin 15 mA

Total of all pins 100 mA

Output current, high IOH Per pin −10 mA

Total of all pins −40 mA

Operating ambient TA −40 to +85 °C temperature

Storage temperature Tstg −65 to +150 °C

Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the

product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values.

Data Sheet U12376EJ1V0DS00

Operating Conditions

PD784224, 784225, 784224Y, 784225Y

• Operating ambient temperature (T

A): −40°C to +85°C

• Power supply voltage and clock cycle time: see Figure 14-1

• Operating voltage when the subsystem clock is operating: VDD = 1.8 to 5.5 V

Figure 14-1. Power Supply Voltage and Clock Cycle Time (CPU Clock Frequency: f

10,000

8,000

500

400

[ns]

CYK

320 300

Guaranteed

operation range

CPU)

Clock cycle time t

200 160

100

01231.8 2.7 4.5 5.5

Supply voltage [V]

456

Capacitance (TA = 25°C, VDD = VDD0 = VDD1 = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CI f = 1 MHz 15 pF Output capacitance CO I/O capacitance CIO 15 pF

Unmeasured pins returned to 0 V.

15 pF

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Main System Clock Oscillator Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Ceramic Oscillation frequency (fX) 4.5 V ≤ VDD ≤ 5.5 V 2 12.5 MHz resonator or crystal resonator

External X1 input frequency (fX) 4.5 V ≤ VDD ≤ 5.5 V 2 12.5 MHz clock

X2 X1 V

X2 X1

PD74HCU04

X1 input high-/low- 15 250 ns level width (tWXH, tWXL)

X1 input rising/falling 4.5 V ≤ VDD ≤ 5.5 V 0 5 ns time (tXR, tXF)

2.7 V ≤ VDD < 4.5 V 2 6.25

2.0 V ≤ VDD < 2.7 V 2 3.125

1.8 V ≤ VDD < 2.0 V 2 2

2.7 V ≤ VDD < 4.5 V 2 6.25

2.0 V ≤ VDD < 2.7 V 2 3.125

1.8 V ≤ VDD < 2.0 V 2 2

2.7 V ≤ VDD < 4.5 V 0 10

2.0 V ≤ VDD < 2.7 V 0 20

1.8 V ≤ VDD < 2.0 V 0 30

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V

SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Subsystem Clock Oscillator Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Crystal Oscillation frequency (fXT)32

resonator

VSSXT2 XT1

Oscillation stabilization 4.5 V ≤ VDD ≤ 5.5 V 1.2 2 s

Note

time

1.8 V ≤ VDD < 4.5 V 10

32.768

35 kHz

External XT1 input frequency (fXT) 32 35 kHz clock

XT2 XT1

PD74HCU04

XT1 input high-/low-level 14.3 15.6 width (tXTH, tXTL)

Note Time required to stabilize oscillation after applying supply voltage (VDD).

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V

SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

DC Characteristics

(TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input voltage, low VIL1 Note 1 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDD V

1.8 V ≤ VDD < 2.2 V 0 0.2VDD

VIL2 P00 to P05, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V 0 0.2VDD V

P34, P70, P72, RESET

VIL4 P10 to P17, P130, P131 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDD V

VIL5 X1, X2, XT1, XT2 2.2 V ≤ VDD ≤ 5.5 V 0 0.2VDD V

VIL6 P25, P27 2.2 V ≤ VDD ≤ 5.5 V 0 0.3VDD V

Input voltage, high VIH1 Note 1 2.2 V ≤ VDD ≤ 5.5 V 0.7VDD VDD V

VIH2 P00 to P05, P20, P22, P33, 2.2 V ≤ VDD ≤ 5.5 V 0.8VDD VDD V

P34, P70, P72, RESET

VIH4 P10 to P17, P130, P131 2.2 V ≤ VDD ≤ 5.5 V 0.7VDD VDD V

VIH5 X1, X2, XT1, XT2 2.2 V ≤ VDD ≤ 5.5 V 0.8VDD VDD V

VIH6 P25, P27 2.2 V ≤ VDD ≤ 5.5 V 0.7VDD VDD V

Output voltage, low VOL1 For pins other than 4.5 V ≤ VDD ≤ 5.5 V 0.4 V

P40 to P47, P50 to P57, IOL = 1.6 mA

P40 to P47, P50 to P57 4.5 V ≤ VDD ≤ 5.5 V 1.0 V IOL = 8 mA

VOL2 IOL = 400 µA

Output voltage, high VOH1 IOH = −1 mA

IOH = −100 µA

Input leakage current, ILIL1 VIN = 0 V Except X1, X2, −3 low XT1, XT2

ILIL2 X1, X2, XT1, XT2 −20µA

Input leakage current, ILIH1 VIN = VDD0 Except X1, X2, 3 high XT1, XT2

ILIH2 X1, X2, XT1, XT2 20

Output leakage current, ILOL1 VOUT = 0 V −3 low

Output leakage current, ILOH1 VOUT = VDD 3 high

Note 2

1.8 V ≤ VDD < 2.2 V 0

1.8 V ≤ VDD < 2.2 V 0 0.2VDD

1.8 V ≤ VDD < 2.2 V 0 0.1VDD

1.8 V ≤ VDD < 2.2 V 0 0.2VDD

1.8 V ≤ VDD < 2.2 V 0.8VDD VDD

1.8 V ≤ VDD < 2.2 V

1.8 V ≤ VDD < 2.2 V 0.8VDD VDD

1.8 V ≤ VDD < 2.2 V

1.8 V ≤ VDD < 2.2 V 0.8VDD VDD

4.5 V ≤ VDD ≤ 5.5 V

0.85VDD

VDD − 1.0 VDD − 0.5

0.15VDD

VDD

0.5 V V V

Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87,

P120 to P127

2. Per pin

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

DC Characteristics

(TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply voltage IDD1 Operation fXX = 12.5 MHz, VDD = 5.0 V ±10% 17 40 mA

mode

IDD2 HALT mode fXX = 12.5 MHz, VDD = 5.0 V ±10% 7 20 mA

IDD3 IDLE mode fXX = 12.5 MHz, VDD = 5.0 V ±10% 1 2.5 mA

IDD4 Operation fXX = 32 kHz, VDD = 5.0 V ±10% 80 200µA

Note

mode

IDD5 HALT fXX = 32 kHz, VDD = 5.0 V ±10% 60 160µA

Note

mode

IDD6 IDLE fXX = 32 kHz, VDD = 5.0 V ±10% 50 150µA

Note

mode

Data retention voltage VDDDR HALT, IDLE modes 1.8 5.5 V Data retention current IDDDR STOP mode VDD = 2.0 V ±10% 2 10

Pull-up resistor RL VIN = 0 V 10 30 100 kΩ

fXX = 6 MHz, VDD = 3.0 V ±10% 5 17 mA fXX = 2 MHz, VDD = 2.0 V ±10% 2 8 mA

fXX = 6 MHz, VDD = 3.0 V ±10% 2 8 mA fXX = 2 MHz, VDD = 2.0 V ±10% 0.5 3.5 mA

fXX = 6 MHz, VDD = 3.0 V ±10% 0.4 1.3 mA fXX = 2 MHz, VDD = 2.0 V ±10% 0.2 0.9 mA

fXX = 32 kHz, VDD = 3.0 V ±10% 60 110 fXX = 32 kHz, VDD = 2.0 V ±10% 30 100

fXX = 32 kHz, VDD = 3.0 V ±10% 20 80 fXX = 32 kHz, VDD = 2.0 V ±10% 10 70

fXX = 32 kHz, VDD = 3.0 V ±10% 15 70 fXX = 32 kHz, VDD = 2.0 V ±10% 5 60

VDD = 5.0 V ±10% 10 50

Note When main system clock is stopped.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

AC Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)

(1) Read/write operation (1/3)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Cycle time tCYK 4.5 V ≤ VDD ≤ 5.5 V 80 ns

2.7 V ≤ VDD < 4.5 V 160 ns

2.0 V ≤ VDD < 2.7 V 320 ns

1.8 V ≤ VDD < 2.0 V 500 ns

Address setup time tSAST VDD = 5.0 V ±10% (0.5 + a) T − 20 ns (to ASTB↓)

Address hold time tHSTLA VDD = 5.0 V ±10% 0.5T − 19 ns (from ASTB↓)

ASTB high-level width tWSTH VDD = 5.0 V ±10% (0.5 + a) T − 17 ns

Address hold time tHRA VDD = 5.0 V ±10% 0.5T − 14 ns (from RD↑)

Delay time from address to tDAR VDD = 5.0 V ±10% (1 + a) T − 24 ns RD↓

Address float time tFAR VDD = 5.0 V ±10% 0 ns (from RD↓)

Data input time from tDAID VDD = 5.0 V ±10% (2.5 + a + n) T − 37 ns address

Data input time from ASTB↓ tDSTID VDD = 5.0 V ±10% (2 + n) T − 35 ns

Data input time from RD↓ tDRID VDD = 5.0 V ±10% (1.5 + n) T − 40 ns

VDD = 3.0 V ±10% (0.5 + a) T − 40 ns VDD = 2.0 V ±10% (0.5 + a) T − 80 ns

VDD = 3.0 V ±10% 0.5T − 24 ns VDD = 2.0 V ±10% 0.5T − 34 ns

VDD = 3.0 V ±10% (0.5 + a) T − 40 ns VDD = 2.0 V ±10% (0.5 + a) T − 110 ns

VDD = 3.0 V ±10% 0.5T − 14 ns VDD = 2.0 V ±10% 0.5T − 14 ns

VDD = 3.0 V ±10% (1 + a) T − 35 ns VDD = 2.0 V ±10% (1 + a) T − 80 ns

VDD = 3.0 V ±10% 0 ns VDD = 2.0 V ±10% 0 ns

VDD = 3.0 V ±10% (2.5 + a + n) T − 52 ns VDD = 2.0 V ±10% (2.5 + a + n) T − 120 ns

VDD = 3.0 V ±10% (2 + n) T − 50 ns VDD = 2.0 V ±10% (2 + n) T − 80 ns

VDD = 3.0 V ±10% (1.5 + n) T − 50 ns VDD = 2.0 V ±10% (1.5 + n) T − 90 ns

Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)

a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0)

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

AC Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)

(1) Read/write operation (2/3)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Delay time from ASTB↓ tDSTR VDD = 5.0 V ±10% 0.5T − 9ns to RD↓

Data hold time (from RD↑)tHRID VDD = 5.0 V ±10% 0 ns

Address active time from tDRA VDD = 5.0 V ±10% 0.5T − 2ns RD↑

Delay time from RD↑ to tDRST VDD = 5.0 V ±10% 0.5T − 9ns ASTB↑

RD low-level width tWRL VDD = 5.0 V ±10% (1.5 + n) T − 25 ns

Delay time from address to tDAW VDD = 5.0 V ±10% (1 + a) T − 24 ns WR↓

Address hold time tHRD VDD = 5.0 V ±10% 0.5T − 14 ns (from WR↑)

Delay time from ASTB↓ to tDSTOD VDD = 5.0 V ±10% 0.5T + 15 ns data output

Delay time from WR↓ to tDWOD VDD = 5.0 V ±10% 0.5T − 30 ns data output

Delay time from ASTB↓ to tDSTW VDD = 5.0 V ±10% 0.5T − 9ns WR↓

Data setup time (to WR↑)tSODWR VDD = 5.0 V ±10% (1.5 + n) T − 20 ns

VDD = 3.0 V ±10% 0.5T − 9ns VDD = 2.0 V ±10% 0.5T − 20 ns

VDD = 3.0 V ±10% 0 ns VDD = 2.0 V ±10% 0 ns

VDD = 3.0 V ±10% 0.5T − 12 ns VDD = 2.0 V ±10% 0.5T − 35 ns

VDD = 3.0 V ±10% 0.5T − 9ns VDD = 2.0 V ±10% 0.5T − 40 ns

VDD = 3.0 V ±10% (1.5 + n) T − 30 ns VDD = 2.0 V ±10% (1.5 + n) T − 25 ns

VDD = 3.0 V ±10% (1 + a) T − 34 ns VDD = 2.0 V ±10% (1 + a) T − 70 ns

VDD = 3.0 V ±10% 0.5T − 14 ns VDD = 2.0 V ±10% 0.5T − 14 ns

VDD = 3.0 V ±10% 0.5T + 30 ns VDD = 2.0 V ±10% 0.5T + 240 ns

VDD = 3.0 V ±10% 0.5T − 30 ns VDD = 2.0 V ±10% 0.5T − 30 ns

VDD = 3.0 V ±10% 0.5T − 9ns VDD = 2.0 V ±10% 0.5T − 20 ns

VDD = 3.0 V ±10% (1.5 + n) T − 25 ns VDD = 2.0 V ±10% (1.5 + n) T − 70 ns

Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)

a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0)

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

AC Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)

(1) Read/write operation (3/3)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data hold time (from WR↑)tHWOD VDD = 5.0 V ±10% 0.5T − 14 ns

VDD = 3.0 V ±10% 0.5T − 14 ns VDD = 2.0 V ±10% 0.5T − 50 ns

Delay time from WR↑ to tDWST VDD = 5.0 V ±10% 0.5T − 9ns ASTB↑

WR low-level width tWWL VDD = 5.0 V ±10% (1.5 + n) T − 25 ns

VDD = 3.0 V ±10% 0.5T − 9ns VDD = 2.0 V ±10% 0.5T − 30 ns

VDD = 3.0 V ±10% (1.5 + n) T − 30 ns VDD = 2.0 V ±10% (1.5 + n) T − 30 ns

Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)

a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0)

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

AC Characteristics (TA = −40°C to +85°C, VDD = V

DD0

= V

DD1

= AVDD = 1.8 to 5.5 V, VSS = V

SS0

= V

SS1

= AVSS = 0 V)

(2) External wait timing (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input time from address to tDAWT VDD = 5.0 V ±10% (2 + a) T − 40 ns WAIT↓

Input time from ASTB↓ to tDSTWT VDD = 5.0 V ±10% 1.5T − 40 ns WAIT↓

Hold time from ASTB↓ to tHSTWT VDD = 5.0 V ±10% (0.5 + n) T + 5 ns WAIT

Delay time from ASTB↓ to tDSTWTH VDD = 5.0 V ±10% (1.5 + n) T − 40 ns WAIT↑

Input time from RD↓ to tDRWTL VDD = 5.0 V ±10% T − 40 ns WAIT↓

Hold time from RD↓ to tHRWT VDD = 5.0 V ±10% nT + 5 ns WAIT↓

Delay time from RD↓ to tDRWTH VDD = 5.0 V ±10% (1 + n) T − 40 ns WAIT↑

Input time from WAIT↑ to tDWTID VDD = 5.0 V ±10% 0.5T − 5ns data

Delay time from WAIT↑ to tDWTR VDD = 5.0 V ±10% 0.5T ns RD↑

Delay time from WAIT↑ to tDWTW VDD = 5.0 V ±10% 0.5T ns WR↑

Delay time from WR↓ to tDWWTL VDD = 5.0 V ±10% T − 40 ns WAIT↓

VDD = 3.0 V ±10% (2 + a) T − 60 ns VDD = 2.0 V ±10% (2 + a) T − 300 ns

VDD = 3.0 V ±10% 1.5T − 60 ns VDD = 2.0 V ±10% 1.5T − 260 ns

VDD = 3.0 V ±10% (0.5 + n) T + 10 ns VDD = 2.0 V ±10% (0.5 + n) T + 30 ns

VDD = 3.0 V ±10% (1.5 + n) T − 60 ns VDD = 2.0 V ±10% (1.5 + n) T − 90 ns

VDD = 3.0 V ±10% T − 60 ns VDD = 2.0 V ±10% T − 70 ns

VDD = 3.0 V ±10% nT + 10 ns VDD = 2.0 V ±10% nT + 30 ns

VDD = 3.0 V ±10% (1 + n) T − 60 ns VDD = 2.0 V ±10% (1 + n) T − 90 ns

VDD = 3.0 V ±10% 0.5T − 10 ns VDD = 2.0 V ±10% 0.5T − 30 ns

VDD = 3.0 V ±10% 0.5T ns VDD = 2.0 V ±10% 0.5T + 5 ns

VDD = 3.0 V ±10% T − 60 ns VDD = 2.0 V ±10% T − 90 ns

Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)

a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0)

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

(2) External wait timing (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Hold time from WR↓ to tHWWT VDD = 5.0 V ±10% nT + 5 ns WAIT

Delay time from WR↓ to tDWWTH VDD = 5.0 V ±10% (1 + n) T − 40 ns WAIT↑

Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)

a: 1 (during address wait), otherwise, 0 n: Number of wait states (n ≥ 0)

VDD = 3.0 V ±10% nT + 10 ns VDD = 2.0 V ±10% nT + 30 ns

VDD = 3.0 V ±10% (1 + n) T − 60 ns VDD = 2.0 V ±10% (1 + n) T − 90 ns

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Serial Operation (TA = −40°C to +85°C, VDD = V

DD0

= V

DD1

= AVDD = 1.8 to 5.5 V, VSS = V

SS0

= V

SS1

= AVSS = 0 V)

(a) 3-wire serial I/O mode (SCK: Internal clock output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY1 2.7 V ≤ VDD ≤ 5.5 V 800 ns

3,200 ns

SCK high-/low-level tKH1, 2.7 V ≤ VDD ≤ 5.5 V 350 ns width tKL1

SI setup time (to SCK↑)tSIK1 2.7 V ≤ VDD ≤ 5.5 V 10 ns

SI hold time (from SCK↑) SO output delay time tKSO1 30 ns

(from SCK↓)

tKSI1 40 ns

1,500 ns

30 ns

(b) 3-wire serial I/O mode (SCK: External clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY2 2.7 V ≤ VDD ≤ 5.5 V 800 ns

3,200 ns

SCK high-/low-level tKH2 2.7 V ≤ VDD ≤ 5.5 V 400 ns width tKL2

SI setup time (to SCK↑)tSIK2 2.7 V ≤ VDD ≤ 5.5 V 10 ns

SI hold time (from SCK↑) SO output delay time tKSO2 30 ns

(from SCK↓)

tKSI2 40 ns

1,600 ns

30 ns

Parameter Symbol Conditions MIN. TYP. MAX. Unit

ASCK cycle time tKCY3 4.5 V ≤ VDD ≤ 5.5 V 417 ns

2.7 V ≤ VDD < 4.5 V 833 ns 1,667 ns

ASCK high-/low-level tKH3 4.5 V ≤ VDD ≤ 5.5 V 208 ns width tKL3

2.7 V ≤ VDD < 4.5 V 416 ns

833 ns

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

(d) I2C bus mode (µPD784225Y only)

Parameter Symbol Standard Mode High-Speed Mode Unit

MIN. MAX. MIN. MAX. SCL0 clock frequency fCLK 0 100 0 400 kHz Bus free time (between stop tBUF 4.7 − 1.3 −

and start conditions) Hold time Low-level width of SCL0 tLOW 4.7 − 1.3 −

clock High-level width of SCL0 tHIGH 4.0 − 0.6 −

clock Setup time of start/restart tSU : STA 4.7 − 0.6 −

conditions Data hold When using tHD : DAT 5.0 −−−

time

Data setup time tSU : DAT 250 − 100 Rising time of SDA0 and tR − 1,000 20 + 0.1Cb

SCL0 signals Falling time of SDA0 and tF − 300 20 + 0.1Cb

SCL0 signals Setup time of stop condition t SU : STO 4.0 − 0.6 − Pulse width of spike tSP −−050ns

restricted by input filter Load capacitance of each Cb − 400 − 400 pF

bus line

Note1

CBUS-compatible master

When using I2C0 bus

tHD : STA 4.0 − 0.6 −

Note 2

− 0

Note 2

Note 4

Note 5

Note 3

0.9

− ns

300 ns

Notes 1. For the start condition, the first clock pulse is generated after the hold time.

2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal

SDA0 signal (on V

IHmin.) with at least 300 ns of hold time.

3. If the device does not extend the SCL0 signal low-level hold time (t LOW), only the maximum data hold time tHD : DAT needs to be satisfied.

4. The high-speed mode I

C bus can be used in a standard mode I2C bus system. In this case, the

conditions described below must be satisfied.

• If the device does not extend the SCL0 signal low-level hold time

SU : DAT ≥ 250 ns

• If the device extends the SCL0 signal low-level hold time

Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU : DAT =

1,000 + 250 = 1,250 ns by standard mode I

C bus specification)

5. Cb: Total capacitance per bus line (unit: pF)

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Other Operations (TA = −40°C to +85°C, VDD = V

Parameter Symbol Conditions MIN. TYP. MAX. Unit

NMI high-/low-level tWNIL 10 width tWNIH

INTP input high-/low- tWITL INTP0 to INTP6 100 ns level width t WITH

RESET high-/low-level tWRSL 10 width t WRSH

DD0

= V

DD1

= AVDD = 1.8 to 5.5 V, VSS = V

SS0

= V

SS1

= AVSS = 0 V)

Clock Output Operation

A = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit PCL cycle time tCYCL 4.5 V ≤ VDD ≤ 5.5 V, nT 80 31,250 ns PCL high-/low-level tCLL 4.5 V ≤ VDD ≤ 5.5 V, 0.5T − 10 30 15,615 ns

width tCLH PCL rising/falling time tCLR 4.5 V ≤ VDD ≤ 5.5 V 5 ns

tCLF

2.7 V ≤ VDD < 4.5 V 10 ns

1.8 V ≤ VDD < 2.7 V 20 ns

Remark T: tCYK = 1/fXX (fXX: Main system clock frequency)

n: Divided frequency ratio set by software in the CPU

• When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128

• When using the subsystem clock: n = 1

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

A/D Converter Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 888bit Overall error

Conversion time tCONV 14 144 Sampling time tSAMP 24/fXX Analog input voltage VIAN AVSS AVDD V Reference voltage AVDD VDD VDD VDD V Resistance between RAVREF0 A/D conversion is not performed 40 kΩ

AVDD and AVSS

Note

6.25 MHz < fXX ≤ 12.5 MHz, ±1.2 %FSR

4.5 V ≤ VDD ≤ 5.5 V, AVDD = VDD0

3.125 MHz < fXX ≤ 6.25 MHz, ±1.2 %FSR

2.7 V ≤ VDD ≤ 5.5 V, AVDD = VDD0 2 MHz < fXX ≤ 3.125 MHz, ±1.6 %FSR

2.0 V ≤ VDD ≤ 5.5 V, AVDD = VDD0 fXX = 2 MHz, 1.8 V ≤ VDD ≤ 5.5 V ±1.6 %FSR

AVDD = VDD0

Note Excludes quantization error (±0.2%FSR).

Remark FSR: Full-scale range

D/A Converter Characteristics

A = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 888bit Overall error

Settling time Load conditions: 4.5 V ≤ AVREF1 ≤ 5.5 V 10

Output resistance RO DACS0, 1 = 55H 8 kΩ Reference voltage AVREF1 1.8 VDD0 V AVREF1 current AIREF1 For only 1 channel 2.5 mA

Note

2.0 V ≤ VDD ≤ 5.5 V ±0.6 %FSR R = 10 MΩ, 2.0 V ≤ AVREF1 ≤ 5.5 V

1.8 V ≤ VDD ≤ 2.0 V ±1.2 %FSR R = 10 MΩ, 1.8 V ≤ AVREF1 ≤ 5.5 V

C = 30 pF

2.7 V ≤ AVREF1 < 4.5 V 15

1.8 V ≤ AVREF1 < 2.7 V 20

Note Excludes quantization error (±0.2%FSR).

Remark FSR: Full-scale range

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Data Retention Characteristics (TA = −40°C to +85°C, VDD = VDD0 = VDD1 = AVDD = 1.8 to 5.5 V, VSS = VSS0 = VSS1 = AVSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage VDDDR STOP mode 1.8 5.5 V Data retention current IDDDR VDDDR = 5.0 V ±10% 10 50

VDDDR = 2.0 V ±10% 2 10 VDD rise time tRVD 200 VDD fall time tFVD 200 VDD hold time (from tHVD 0ms

STOP mode setting) STOP release signal tDREL 0ms

input time Oscillation stabilization tWAIT Crystal resonator 30 ms

wait time Low-level input voltage VIL RESET, P00/INTP0 to P06/INTP6 0

High-level input voltage VIH

Ceramic resonator 5 ms

0.1VDDDR

0.9VDDDR

VDDDR V

AC Timing Measurement Points

− 1 V

0.45 V

0.8VDD or 1.8 V

0.8 V

Points of

measurement

0.8VDD or 1.8 V

0.8 V

Data Sheet U12376EJ1V0DS00

Timing Waveform

(1) Read operation

(CLK)

CYK

PD784224, 784225, 784224Y, 784225Y

A0 to A7

(Output)

A8 to A19

(Output)

AD0 to AD7

(Input/output)

ASTB

(Output)

RD (Output)

WAIT

(Input)

Lower address Lower address

Higher address

DAID

DSTID

Hi-Z Hi-Z Hi-Z

Lower address (Output)

SAST

WSTH

DAWT

DAR

HSTLA

DSTR

DRWTL

t t t

DSTWT DSTWTH HSTWT

Data (Input)

HRID

FAR

DRID

WRL

DRWTH

HRWT

DWTID

DWTR

HRA

DRA

DRST

Higher address

Lower address (Output)

Data Sheet U12376EJ1V0DS00

(2) Write operation

(CLK)

PD784224, 784225, 784224Y, 784225Y

CYK

A0 to A7

(Output)

A8 to A19

(Output)

AD0 to AD7

(Output)

ASTB

(Output)

WAIT

(Input)

Lower address Lower address

Higher address Higher address

DAID

DSTOD

Hi-Z Hi-Z Hi-Z

Lower address (Output)

SAST

WSTH

DAWT

DAW

HSTLA

DSTW

DWWTL

t t t

DSTWT DSTWTH HSTWT

FAR

DWOD

DWWTH

HWWT

WWL

Data (Output)

HWOD

SODWR

DWTW

DWTID

HWA

DAW

DWST

Lower address (Output)

Data Sheet U12376EJ1V0DS00

Serial Operation

(1) 3-wire serial I/O mode

SI/SO

(2) UART mode

ASCK

SCK

PD784224, 784225, 784224Y, 784225Y

KSO1, 2

KSI1, 2

KCY1, 2

KL1, 2

SIK1, 2

KH1, 2

KCY3

KH3

KL3

(3) I2C bus mode (µPD784255Y Subseries only)

LOW

SCL0

SDA0

Stop condition

BUF

HD : STA

Start condition

HD : DAT

HIGH

SU : DAT

SU : STA

Restart condition

HD : STA

Stop condition

SU : STO

Data Sheet U12376EJ1V0DS00

Clock Output Timing

CLKOUT

Interrupt Input Timing

NMI

PD784224, 784225, 784224Y, 784225Y

CLH

CLR

CYCL

WNIH

CLL

CLF

WNIL

INTP0 to INTP6

Reset Input Timing

RESET

WRSH

WITH

WRSL

WITL

Data Sheet U12376EJ1V0DS00

Clock Timing

XT1

PD784224, 784225, 784224Y, 784225Y

WXH

1/f

XTH

1/f

WXL

XTL

Data Retention Characteristics

STOP mode setting

HVD

RESET

NMI (Cleared by falling edge)

NMI (Cleared by rising edge)

FVD

DDDR

RVD

DREL

WAIT

Data Sheet U12376EJ1V0DS00

15. PACKAGE DRAWINGS

80-PIN PLASTIC QFP (14x14)

PD784224, 784225, 784224Y, 784225Y

4160

4061

detail of lead end

C D

2180

201

NOTE

Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

17.20±0.20

14.00±0.20 C 14.00±0.20 D

17.20±0.20 F 0.825 G

0.825 H 0.32±0.06

0.13

0.65 (T.P.) K

1.60±0.20 L

0.80±0.20

M 0.17

N 0.10

Q R3 S 1.70 MAX.

+0.03

−0.07

1.40±0.10

0.125±0.075

+7

−3

P80GC-65-8BT-1

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

80-PIN PLASTIC TQFP (FINE PITCH) (12x12)

A B

60 41

detail of lead end

120

NOTE

Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A 14.0±0.2 B 12.0±0.2 C 12.0±0.2 D

14.0±0.2 F 1.25 G

1.25 H 0.22±0.05

I 0.08

J 0.5 (T.P.)

1.0±0.2

L 0.5

0.145±0.05 N 0.08 P

1.0 Q 0.1±0.05

R S 1.1±0.1

T 0.25 U 0.6±0.15

+4

3

−3

P80GK-50-9EU-1

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

16. RECOMMENDED SOLDERING CONDITIONS

The µPD784225 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales representative.

Caution Soldering conditions for the

×××-9EU are undetermined because these products are under development.

Table 16-1. Soldering Conditions for Surface Mount Type

PD784225GC-×××-8BT: 80-pin plastic QFP (14 × 14 mm)

(1)

Soldering Method Soldering Conditions Recommended

Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or IR35-00-2

higher), Count: Two times or less, Exposure limit: 7 days prebake at 125°C for 20 hours)

VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or VP15-00-2

higher), Count: Two times or less, Exposure limit: 7 days prebake at 125°C for 20 hours)

Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, —

Preheating temperature: 120°C max. (package surface temperature) Exposure limit: 7 days

Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) —

PD784224GC-×××-8BT, µPD784225YGC-×××-8BT, and µPD784225YGK-

Condition Symbol

Note

(after that,

Note

(after that,

Note

(after that, prebake at 125°C for 20 hours)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

(2)µPD784224GK-×××-9EU: 80-pin plastic TQFP (fine pitch) (14 × 20 mm)

PD784225GK-×××-9EU: 80-pin plastic TQFP (fine pitch) (14 × 20 mm)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or IR35-103-2

higher), Count: Two times or less, Exposure limit: 7 days prebake at 125°C for 20 hours)

VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or VP15-103-2

higher), Count: Two times or less, Exposure limit: 7 days prebake at 125°C for 20 hours)

Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, —

Preheating temperature: 120°C max. (package surface temperature)

Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) —

Note

(after that,

Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD784225. Also see (5).

(1) Language Processing Software

RA78K4 Assembler package common to 78K/IV Series CC78K4 C compiler package common to 78K/IV Series DF784225 Device file common to µPD784225, 784225Y Subseries CC78K4-L C compiler library source file common to 78K/IV Series

(2) Flash Memory Writing Tools

Flashpro II Dedicated flash programmer for microcontroller incorporating flash memory (Part No.: FL-PR2), Flashpro III (Part No.: FL-PR3, PG-FP3)

FA-80GC Adapter for writing 80-pin plastic QFP (GC-8BT type) flash memory. FA-80GK Adapter for writing 80-pin plastic LQFP (GK-BE9 type) flash memory.

(3) Debugging Tools

• When IE-78K4-NS in-circuit emulator is used

IE-78K4-NS In-circuit emulator common to 78K/IV Series IE-70000-MC-PS-B Power supply unit for IE-78K4-NS IE-70000-98-IF-C Interface adapter used when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported) IE-70000-CD-IF-A PC card and cable when notebook PC is used as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/ATTM or compatible as host machine (ISA bus

supported) IE-70000-PCI-IF Interface adapter when using PC that incorporates PCI bus as host machine IE-784225-NS-EM1 Emulation board to emulate µPD784225, 784225Y Subseries NP-100GF Emulation probe for 100-pin plastic QFP (GF-3BA type) NP-100GC Emulation probe for 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) TGC-100SDW Conversion adapter to connect the NP-100GC and a target system board on which a 100-

pin plastic LQFP (GC-8EU type) can be mounted ID78K4-NS Integrated debugger for IE-78K4-NS SM78K4 System simulator common to 78K/IV Series DF784225 Device file common to µPD784225, 784225Y Subseries

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

• When IE-784000-R in-circuit emulator is used

IE-784000-R In-circuit emulator common to 78K/IV Series IE-70000-98-IF-C Interface adapter used when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-PC-IF-C Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus

supported) IE-70000-PCI-IF Interface adapter when using PC that incorporates PCI bus as host machine IE-78000-R-SV3 Interface adapter and cable used when EWS is used as host machine IE-784225-NS-EM1 Emulation board to emulate µPD784225, 784225Y Subseries

IE-784218-R-EM1 IE-784000-R-EM Emulation board common to 78K/IV Series IE-78K4-R-EX3 Emulation probe conversion board necessary when using IE-784225-NS-EM1 on IE-

784000-R. Not necessary when IE-784216-R-EM1 is used. EP-78064GF-R Emulation probe for 100-pin plastic QFP (GF-3BA type) EP-78064GC-R Emulation probe for 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type) TGC-100SDW Conversion adapter to connect the NP-100GC and a target system board on which a 100-

pin plastic LQFP (GC-8EU type) can be mounted ID78K4 Integrated debugger for IE-784000-R SM78K4 System simulator common to 78K/IV Series DF784225 Device file common to µPD784225, 784225Y Subseries

(4) Real-time OS

RX78K/IV Real-time OS for 78K/IV Series MX78K4 OS for 78K/IV Series

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

(5) Cautions on Using Development Tools

• The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784225.

• The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.

• The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813).

• The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION. For further information, contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (TEL: +81-3-3820-7112) Osaka Electronic Division (TEL: +81-6-6244-6672)

• For third-party development tools, see the 78K/IV Series Selection Guide (U13355E).

• The host machine and OS suitable for each software are as follows:

Host Machine PC EWS

[OS]

Software [Japanese/English Windows] NEWSTM (RISC) [NEWS-OSTM] RA78K4 CC78K4 ID78K4-NS – ID78K4 SM78K4 – RX78K/IV MX78K4

PC-9800 series [Windows] HP9000 series 700TM [HP-UXTM]

IBM PC/AT and compatibles SPARCstationTM [SunOSTM, SolarisTM]

Note

Note DOS-based software

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

APPENDIX B. RELATED DOCUMENTS

Documents related to device

Document Name Document No.

Japanese English

PD784224, 784225, 784224Y, 784225Y Data Sheet U12376J This document

PD78F4225, 78F4225Y Data Sheet U12377J Planned

PD784225, 784225Y Subseries User’s Manual - Hardware Planned Planned

PD784225Y Subseries Special Function Register Table Planned – 78K/IV Series User’s Manual - Instruction U10905J U10905E 78K/IV Series Instruction Table U10594J – 78K/IV Series Instruction Set U10595J – 78K/IV Series Application Note - Software Basics U10095J U10095E

Documents related to development tools (User’s Manuals)

Document Name Document No.

Japanese English

RA78K4 Assembler Package Operation U11334J U11334E

Language U11162J U11162E RA78K Series Structured Assembler Preprocessor U11743J U11743E CC78K4 C Compiler Operation U11572J U11572E

Language U11571J U11571E IE-78K4-NS U13356J U13356E IE-784000-R U12903J U12903E IE-784218-R-EM1 U12155J U12155E IE-784225-NS-EM1 U13742J U13742E EP-78064 EEU-934 EEU-1469 SM78K4 System Simulator - Windows Base Reference U10093J U10093E SM78K Series System Simulator

ID78K4-NS Integrated Debugger - PC Base Reference U12796J U12796E ID78K4 Integrated Debugger - Windows Base Reference U10440J U10440E ID78K4 Integrated Debugger - HP-UX, SunOS, Reference U11960J U11960E

NEWS-OS Base

External component

user open interface

specification

U10092J U10092E

Caution The contents of the above related documents are subject to change without notice. Be sure to

use the latest edition of a document for designing.

Data Sheet U12376EJ1V0DS00

PD784224, 784225, 784224Y, 784225Y

Documents related to embedded software (User’s Manual)

Document Name Document No.

Japanese English

78K/IV Series Real-Time OS Basics U10603J U10603E

Installation U10604J U10604E Debugger U10364J –

78K/IV Series OS MX78K4 Basics U11779J –

NEC PD784224, PD784225, PD784224Y, PD784225Y Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATION FIELD

ORDERING INFORMATION

78K/IV SERIES LINEUP

FUNCTIONS

3. PIN CONFIGURATION (Top View)

4. BLOCK DIAGRAM

5. PIN FUNCTION

5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins

6. CPU ARCHITECTURE

6.1 Memory Space

6.2 CPU Registers

6.2.1 General-purpose registers

6.2.2 Control registers

6.2.3 Special function registers (SFRs)

7. PERIPHERAL HARDWARE FUNCTIONS

7.1 Ports

7.2 Clock Generator

7.3 Real-Time Output Port

7.4 Timer

7.5 A/D Converter

7.6 D/A Converter

7.7 Serial Interface

7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

7.7.2 Clocked serial interface (CSI)

7.8 Clock Output Function

7.9 Buzzer Output Function

7.10 Edge Detection Function

7.11 Watch Timer

7.12 Watchdog Timer

8. INTERRUPT FUNCTION

8.1 Interrupt Sources

8.2 Vectored Interrupt

8.3 Context Switching

8.4 Macro Service

8.5 Application Example of Macro Service

9. LOCAL BUS INTERFACE

9.1 Memory Expansion

9.2 Programmable Wait

9.3 External Access Status Function

10. STANDBY FUNCTION

11. RESET FUNCTION

12. ROM CORRECTION

13. INSTRUCTION SET

14. ELECTRICAL SPECIFICATIONS

15. PACKAGE DRAWINGS

16. RECOMMENDED SOLDERING CONDITIONS

APPENDIX A. DEVELOPMENT TOOLS

APPENDIX B. RELATED DOCUMENTS