NEC PD780031AY, PD780032AY, PD780033AY, PD780034AY Technical data

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PD780031AY, 780032AY, 780033AY, 780034AY

8-BIT SINGLE-CHIP MICROCONTROLLERS

DESCRIPTION

The µPD780031AY, 780032AY, 780033AY, and 780034AY are members of the µPD780034AY Subseries of the 78K/0 Series. This is a µPD780034A Subseries product with an added multimaster-supporting I2C bus interface, and is suitable for AV equipment applications.

A flash memory version, the ROM version, and various development tools, are available.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing.

PD780024A, 780034A, 780024AY, 780034AY Subseries User's Manual: U14046E 78K/0 Series User’s Manual Instructions: U12326E

DATA SHEET

MOS INTEGRATED CIRCUIT

PD78F0034AY, that can operate in the same power supply voltage range as the mask

FEATURES

• Internal ROM and RAM

Item Program Memory Data Memory Package

Part Number (Internal ROM) (Internal High-Speed RAM)

PD780031AY 8 Kbytes 512 bytes • 64-pin plastic shrink DIP (750 mils)

PD780032AY 16 Kbytes

PD780033AY 24 Kbytes 1024 bytes

PD780034AY 32 Kbytes

• External memory expansion space: 64 Kbytes

• Minimum instruction execution time: 0.24 µs (@ fX = 8.38-MHz operation)

• I/O ports: 51 (5-V-tolerant N-ch open-drain: 4)

• 10-bit resolution A/D converter: 8 channels (AV

• Serial interface: 3 channels (multimaster-supporting I2C bus mode, UART mode, 3-wire serial I/O mode)

• Timer: 5 channels

• Power supply voltage: V

DD = 1.8 to 5.5 V

DD = 1.8 to 5.5 V)

• 64-pin plastic QFP (14 × 14 mm)

• 64-pin plastic LQFP (12 × 12 mm)

APPLICATIONS

Telephones, home electric appliances, pagers, AV equipment, car audios, office automation equipment, etc.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U14045EJ1V0DS00 (1st edition) Date Published August 1999 N CP(K) Printed in Japan

1999

PD780031AY, 780032AY, 780033AY, 780034AY

ORDERING INFORMATION

Part Number Package

PD780031AYCW-××× 64-pin plastic shrink DIP (750 mils)

PD780031AYGC-×××-AB8 64-pin plastic QFP (14 × 14 mm)

PD780031AYGK-×××-8A8 64-pin plastic LQFP (12 × 12 mm)

PD780032AYCW-××× 64-pin plastic shrink DIP (750 mils)

PD780032AYGC-×××-AB8 64-pin plastic QFP (14 × 14 mm)

PD780032AYGK-×××-8A8 64-pin plastic LQFP (12 × 12 mm)

PD780033AYCW-××× 64-pin plastic shrink DIP (750 mils)

PD780033AYGC-×××-AB8 64-pin plastic QFP (14 × 14 mm)

PD780033AYGK-×××-8A8 64-pin plastic LQFP (12 × 12 mm)

PD780034AYCW-××× 64-pin plastic shrink DIP (750 mils)

PD780034AYGC-×××-AB8 64-pin plastic QFP (14 × 14 mm)

PD780034AYGK-×××-8A8 64-pin plastic LQFP (12 × 12 mm)

Remark ××× indicates ROM code suffix.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

78K/0 SERIES LINEUP

The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.

Products in mass production Products under development

C bus.

100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin

64-pin 64-pin

64-pin 42/44-pin

Control

PD78075B

PD78078

PD78070A

PD780058

PD78058F

PD78054

PD780065

PD780078

PD780034A

PD780024A

PD78014H

PD78018F

PD78083

PD78078Y PD78070AY

PD780018AY

PD780058Y

PD78058FY

PD78054Y

PD780078Y

PD780034AY

PD780024AY

PD78018FY

Y subseries products are compatible with I

EMI-noise reduced version of the PD78078 PD78054 with added timer and enhanced external interface

ROM-less version of the PD78078

PD78078Y with enhanced serial I/O and limited functions

PD78054 with enhanced serial I/O

EMI-noise reduced version of the PD78054

PD78018F with added UART and D/A converter and enhanced I/O

PD780024A with increased RAM capacity

A PD780034A with added timer and enhanced serial I/O

PD780024A with enhanced A/D converter

PD78018F with enhanced serial I/O

EMI-noise reduced version of the PD78018F Basic subseries for control

On-chip UART, capable of operating at low voltage (1.8 V)

78K/0 Series

64-pin

80-pin 80-pin 80-pin

100-pin 100-pin 100-pin

80-pin

100-pin 80-pin 80-pin

80-pin

Inverter control

PD780988

FIP

drive

PD780208100-pin

PD780208

PD780228100-pin

µµ

PD780232

PD78044H

PD78044F

LCD drive

PD780308

PD78064B

PD78064

Call ID supported

PD780841

Bus interface supported

PD780948

PD78098B

PD780308Y

PD78064Y

µµ

PD780701Y

PD780833Y

On-chip inverter control circuit and UART. EMI-noise reduced.

PD78044F with enhanced I/O and FIP C/D. Display output total: 53

PD78044H with enhanced I/O and FIP C/D. Display output total: 48

For panel control. On-chip FIP C/D. Display output total: 53

PD78044F with added N-ch open drain I/O. Display output total: 34

Basic subseries for driving FIP. Display output total: 34

PD78064 with enhanced SIO, and increased ROM, RAM capacity.

EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, on-chip UART

On-chip Call ID and simple DTMF. EMI-noise reduced.

On-chip D-CAN controller

PD78054 with IEBusTM controller added. EMI-noise reduced.

On-chip D-CAN/IEBus controller

On-chip controller compliant with J1850 (Class 2)

100-pin 80-pin

80-pin 80-pin

Meter control

PD780958

PD780955

PD780973

PD780824

For industrial meter control

Ultra low-power consumption. On-chip UART. On-chip automobile meter controller/driver For automobile meter. On-chip D-CAN controller.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

The major functional differences among the Y subseries are shown below.

Function ROM Capacity Configuration of Serial Interface I/O VDD MIN.

Subseries Name Value ControlµPD78078Y 48 K to 60 K 3-wire/2-wire/I2C: 1 ch 88 1.8 V

PD78070AY —

PD780018AY 48 K to 60 K 3-wire with automatic transmit/receive function: 1 ch 88

PD780058Y 24 K to 60 K 3-wire/2-wire/I2C: 1 ch 68 1.8 V

PD78058FY 48 K to 60 K 3-wire/2-wire/I2C: 1 ch 69 2.7 V

PD78054Y 16 K to 60 K

PD780078Y 48 K to 60 K 3-wire: 1 ch 52 1.8 V

PD780034AY 8 K to 32 K UART: 1 ch 51 1.8 V

PD780024AY

PD78018FY 8 K to 60 K 3-wire/2-wire/I2C: 1 ch 53

LCD drive 3-wire/time-division UART: 1 ch

PD780308Y 48 K to 60 K 3-wire/2-wire/I2C: 1 ch 57 2.0 V

PD78064Y 16 K to 32 K 3-wire/2-wire/I2C: 1 ch

3-wire with automatic transmit/receive function: 1 ch 3-wire/UART: 1 ch

Time-division 3-wire: 1 ch I2C bus (multimaster supported): 1 ch

3-wire with automatic transmit/receive function: 1 ch 3-wire/time-division UART: 1 ch

3-wire with automatic transmit/receive function: 1 ch 3-wire/UART: 1 ch

UART: 1 ch 3-wire/UART: 1 ch I2C bus (multimaster supported): 1 ch

3-wire: 1 ch I2C bus (multimaster supported): 1 ch

3-wire with automatic transmit/receive function: 1 ch

3-wire: 1 ch

3-wire/UART: 1 ch

61 2.7 V

2.0 V

Remark Functions other than the serial interface are common to the non-Y subseries.

Data Sheet U14045EJ1V0DS00

OVERVIEW OF FUNCTIONS

PD780031AY, 780032AY, 780033AY, 780034AY

Part Number

Item Internal ROM 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes memory High-speed RAM 512 bytes 1024 bytes Memory space 64 Kbytes General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution On-chip minimum instruction execution time cycle variable function

time

Instruction set • 16-bit operation

I/O ports Total: 51

A/D converter • 10-bit resolution x 8 channels

Serial interface • 3-wire serial I/O mode: 1 channel

Timer • 16-bit timer/event counter: 1 channel

Timer output 3 (8-bit PWM output capable: 2) Clock output • 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz

Buzzer output 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38-MHz operation with main system clock) Vectored Maskable Internal: 13, external: 5 interrupt Non-maskable Internal: 1 sources Software 1 Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package • 64-pin plastic shrink DIP (750 mils)

When main system 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38-MHz operation) clock selected

When subsystem 122 µs (@ 32.768-kHz operation) clock selected

PD780031AY

• Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjust, etc.

• CMOS input: 8

• CMOS I/O: 39

• 5-V-tolerant N-ch open-drain I/O: 4

• Low-voltage operation available: AVDD = 1.8 to 5.5 V

• UART mode: 1 channel

• I2C bus mode (multimaster supported): 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

(@ 8.38-MHz operation with main system clock )

• 32.768 kHz (@ 32.768-kHz operation with subsystem clock)

• 64-pin plastic QFP (14 × 14 mm)

• 64-pin plastic LQFP (12 × 12 mm)

PD780032AY

PD780033AY

PD780034AY

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

CONTENTS

1. PIN CONFIGURATION (Top View) .....................................................................................................7

2. BLOCK DIAGRAM .............................................................................................................................10

3. PIN FUNCTIONS ................................................................................................................................11

3.1 Port Pins .................................................................................................................................................... 11

3.2 Non-Port Pins............................................................................................................................................ 12

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins..................................................... 14

4. MEMORY SPACE ............................................................................................................................... 16

5. PERIPHERAL HARDWARE FUNCTION FEATURES .......................................................................17

5.1 Ports ........................................................................................................................................................... 17

5.2 Clock Generator ........................................................................................................................................ 18

5.3 Timer/Counter ........................................................................................................................................... 19

5.4 Clock Output/Buzzer Output Control Circuit ....................................................................................... 2 3

5.5 A/D Converter ........................................................................................................................................... 24

5.6 Serial Interface.......................................................................................................................................... 25

6. INTERRUPT FUNCTION....................................................................................................................28

7. EXTERNAL DEVICE EXPANSION FUNCTION ...............................................................................31

8. STANDBY FUNCTION .......................................................................................................................31

9. RESET FUNCTION ............................................................................................................................31

10. MASK OPTION...................................................................................................................................31

11. INSTRUCTION SET ...........................................................................................................................32

12. ELECTRICAL SPECIFICATIONS......................................................................................................34

13. PACKAGE DRAWINGS .....................................................................................................................57

14. RECOMMENDED SOLDERING CONDITIONS ................................................................................60

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................62

APPENDIX B. RELATED DOCUMENTS ...............................................................................................65

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

1. PIN CONFIGURATION (Top View)

• 64-pin plastic shrink DIP (750 mils)

PD780031AYCW-×××, 780032AYCW-×××, 780033AYCW-×××, 780034AYCW-×××

P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7

P50/A8

P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15

SS0

VDD0

P30 P31

P32/SDA0

P33/SCL0

P34 P35 P36

P20/SI30

P21/SO30

P22/SCK30

P23/RxD0

P24/TxD0

P25/ASCK0

DD1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P67/ASTB P66/WAIT P65/WR P64/RD P75/BUZ P74/PCL P73/TI51/TO51 P72/TI50/TO50 P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0

SS1

V X1 X2 IC XT1 XT2 RESET

AV AVREF P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AV

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AV

SS pin to VSS0.

Remark When the µPD780031AY, 780032AY, 780033AY, and 780034AY are used in applications where the

noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to V

DD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

• 64-pin plastic QFP (14 × 14 mm)

PD780031AYGC-×××-AB8, 780032AYGC-×××-AB8, 780033AYGC-×××-AB8, 780034AYGC-×××-AB8

• 64-pin plastic LQFP (12 × 12 mm)

PD780031AYGK-×××-8A8, 780032AYGK-×××-8A8, 780033AYGK-×××-8A8, 780034AYGK-×××-8A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P75/BUZ

P74/PCL

P73/TI51/TO51

P72/TI50/TO50

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P50/A8

P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15

SS0

V V

DD0

P30 P31

P32/SDA0

P33/SCL0

P34 P35

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 V

SS1

X1 X2 IC XT1 XT2 RESET

AV AV

REF

P10/ANI0

P36

P20/SI30

P21/SO30

P24/TxD0

P23/RxD0

P22/SCK30

DD1

P25/ASCK0

P17/ANI7

P16/ANI6

Cautions 1. Connect the IC (Internally Connected) pin directly to V

2. Connect the AVSS pin to VSS0.

Remark When the

PD780031AY, 780032AY, 780033AY, and 780034AY are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to V

DD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

Data Sheet U14045EJ1V0DS00

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

SS0 or VSS1.

PD780031AY, 780032AY, 780033AY, 780034AY

A8 to A15: Address Bus AD0 to AD7: Address/Data Bus ADTRG: AD Trigger Input ANI0 to ANI7: Analog Input ASCK0: Asynchronous Serial Clock ASTB: Address Strobe

DD: Analog Power Supply

AV AVREF: Analog Reference Voltage

SS: Analog Ground

AV BUZ: Buzzer Clock IC: Internally Connected INTP0 to INTP3: External Interrupt Input P00 to P03: Port 0 P10 to P17: Port 1 P20 to P25: Port 2 P30 to P36: Port 3 P40 to P47: Port 4 P50 to P57: Port 5 P64 to P67: Port 6

P70 to P75: Port 7 PCL: Programmable Clock RD: Read Strobe RESET: Reset RxD0: Receive Data SCK30, SCL0: Serial Clock SDA0: Serial Data SI30: Serial Input SO30: Serial Output TI00, TI01, TI50, TI51: Timer Input TO0, TO50, TO51: Timer Output TxD0: Transmit Data

DD0, VDD1: Power Supply

V VSS0, VSS1: Ground WAIT: Wait WR: Write Strobe X1, X2: Crystal (Main System Clock) XT1, XT2: Crystal (Subsystem Clock)

Data Sheet U14045EJ1V0DS00

2. BLOCK DIAGRAM

PD780031AY, 780032AY, 780033AY, 780034AY

TI00/TO0/P70

TI01/P71

TI50/TO50/P72

TI51/TO51/P73

SI30/P20

SO30/P21

SCK30/P22

RxD0/P23

TxD0/P24

ASCK0/P25

SDA0/P32 SCL0/P33

ANI0/P10 to

ANI7/P17

AV AV

REF

INTP0/P00 to

INTP3/P03

BUZ/P75

PCL/P74

16-BIT TIMER/ EVENT COUNTER

8-BIT TIMER/ EVENT COUNTER 50

8-BIT TIMER/ EVENT COUNTER 51

WATCHDOG TIMER

WATCH TIMER

SERIAL INTERFACE 30

UART0

I2C BUS

DD SS

A/D CONVERTER

INTERRUPT CONTROL

BUZZER OUTPUT

CLOCK OUTPUT CONTROL

78K/0

CPU CORE

RAM

DD0VDD1VSS0VSS1

ROM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7 P70 to P75

EXTERNAL ACCESS

SYSTEM CONTROL

P00 to P03

P10 to P17

P20 to P25

P30 to P36

P40 to P47

P50 to P57

P64 to P67

AD0/P40 to AD7/P47

A8/P50 to A15/P57

RD/P64 WR/P65 WAIT/P66 ASTB/P67

RESET X1 X2 XT1 XT2

Remark The internal ROM and RAM capacities differ depending on the product.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin Name I/O Function After Alternate

Reset Function P00 I/O Port 0 Input INTP0 P01 P02 P03 P10 to P17 Input Port 1 Input ANI0 to ANI7

P20 I/O Port 2 Input SI30 P21 P22 P23 P24 TxD0 P25 ASCK0 P30 I/O Port 3 N-ch open-drain input/output port Input — P31 P32 P33 P34 An on-chip pull-up resistor can be — P35 P36 P40 to P47 I/O Port 4 Input AD0 to AD7

P50 to P57 I/O Port 5 Input A8 to A15

P64 I/O Port 6 Input RD P65 P66 P67

4-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

8-bit input-only port

6-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

7-bit input/output port The mask option can be used to specify the Input/output can be specified in 1-bit units. LEDs can be driven directly.

8-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. The interrupt request flag (KRIF) is set to 1 by falling edge detection.

8-bit input/output port LEDs can be driven directly. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

4-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

connection of an on-chip pull-up resistor to P30, P31.

connected by means of software.

INTP1 INTP2 INTP3/ADTRG

SO30 SCK30 RxD0

SDA0 SCL0

WR WAIT ASTB

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

3.1 Port Pins (2/2)

Pin Name I/O Function After Alternate

Reset Function P70 I/O Port 7 Input TI00/TO0 P71 P72 P73 P74 PCL P75 BUZ

6-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

TI01 TI50/TO50 TI51/TO51

3.2 Non-Port Pins (1/2)

Pin Name I/O Function After Alternate

Reset Function INTP0 Input External interrupt request input for which the valid edge (rising edge, Input P00

INTP1 INTP2 P02 INTP3 P03/ADTRG SI30 Input Serial interface serial data input Input P20 SO30 Output Serial interface serial data output Input P21 SDA0 I/O Serial interface serial data input/output Input P32 SCK30 I/O Serial interface serial clock input/output Input P22 SCL0 P33 RxD0 Input Serial data input for asynchronous serial interface Input P23 TxD0 Output Serial data output for asynchronous serial interface Input P24 ASCK0 Input Serial clock input for asynchronous serial interface Input P25 TI00 Input External count clock input to 16-bit timer (TM0) Input P70/TO0

TI01 Capture trigger input to capture register (CR00) of 16-bit timer (TM0) P71 TI50 External count clock input to 8-bit timer (TM50) P72/TO50 TI51 External count clock input to 8-bit timer (TM51) P73/TO51 TO0 Output 16-bit timer (TM0) output Input P70/TI00 TO50 8-bit timer (TM50) output (also used for 8-bit PWM output) Input P72/TI50 TO51 8-bit timer (TM51) output (also used for 8-bit PWM output) P73/TI51 PCL Output Clock output (for trimming of main system clock and subsystem clock) Input P74 BUZ Output Buzzer output Input P75 AD0 to AD7 I/O Lower address/data bus for expanding memory externally Input P40 to P47 A8 to A15 Output Higher address bus for expanding memory externally Input P50 to P57 RD Output Strobe signal output for reading from external memory Input P64 WR Strobe signal output for writing to external memory P65 WAIT Input Wait insertion at external memory access Input P66 ASTB Output Strobe output that externally latches address information output to Input P67

falling edge, or both rising and falling edges) can be specified

Capture trigger input to capture register (CR01) of 16-bit timer (TM0)

ports 4 and 5 to access external memory

P01

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

3.2 Non-Port Pins (2/2)

Pin Name I/O Function After Alternate

Reset Function ANI0 to ANI7 Input A/D converter analog input Input P10 to P17 ADTRG Input A/D converter trigger signal input Input P03/INTP3 AVREF Input A/D converter reference voltage input — — AVDD — A/D converter analog power supply. Set potential to that of VDD0 or VDD1.— — AVSS — A/D converter ground potential. Set potential to that of VSS0 or VSS1.—— RESET Input System reset input — — X1 Input Connecting crystal resonator for main system clock oscillation — — X2 — —— XT1 Input Connecting crystal resonator for subsystem clock oscillation — — XT2 — —— VDD0 — Positive power supply for ports — — VSS0 — Ground potential of ports — — VDD1 — Positive power supply (except ports) — — VSS1 — Ground potential (except ports) — — IC — Internally connected. Connect directly to VSS0 or VSS1.——

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1.

Table 3-1. Types of Pin Input/Output Circuits

Pin Name Input/Output I/O Recommended Connection of Unused Pins

Circuit Type P00/INTP0 to P02/INTP2 8-C Input Independently connect to VSS0 via a resistor. P03/INTP3/ADTRG P10/ANI0 to P17/ANI7 25 Input Independently connect to VDD0 or VSS0 via a resistor. P20/SI30 8-C I/O P21/SO30 5-H P22/SCK30 8-C P23/RxD0 P24/TxD0 5-H P25/ASCK0 8-C P30, P31 13-Q I/O Independently connect to VDD0 via a resistor. P32/SDA0 13-R P33/SCL0 P34 8-C Independently connect to VDD0 or VSS0 via a resistor. P35 5-H P36 8-C P40/AD0 to P47/AD7 5-H I/O Independently connect to VDD0 via a resistor. P50/A8 to P57/A15 I/O Independently connect to VDD0 or VSS0 via a resistor. P64/RD I/O P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 8-C P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL 5-H P75/BUZ RESET 2 Input — XT1 16 Connect to VDD0. XT2 — Leave open. AVDD — Connect to VDD0. AVREF Connect to VSS0. AVSS IC Connect directly to VSS0 or VSS1.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Figure 3-1. Pin Input/Output Circuits

TYPE 2

Schmitt-triggered input with hysteresis characteristics

TYPE 5-H

Pullup

enable

Data

Output

disable

DD0

P-ch

N-ch

SS0

DD0

P-ch

IN/OUT

TYPE 13-R

Data

Output disable

TYPE 16

Feedback cut-off

P-ch

IN/OUT

N-ch

SS0

Input

enable

TYPE 8-C

Pullup

enable

Data

Output

disable

TYPE 13-Q

Data

Output disable

  

DD0

P-ch

N-ch

Mask option

SS0

N-ch

SS0

XT1 XT2

TYPE 25

DD0

P-ch

IN/OUT

Comparator

–

N-ch

SS0

REF

(threshold voltage)

Input

enable

DD0

  

IN/OUT

Input

enable

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

4. MEMORY SPACE

Figure 4-1 shows the memory map of the µPD780031AY, 780032AY, 780033AY, and 780034AY.

Figure 4-1. Memory Map

FFFFH

Special function registers

(SFRs) 256 × 8 bits

FF00H

FEFFH

FEE0H FEDFH

General-purpose

registers

32 × 8 bits

Data memory space

Program memory space

mmmmH

mmmmH – 1

F800H F7FFH

nnnnH + 1

nnnnH

0000H

Internal high-speed

External memory

Internal ROM

Note

RAM

Reserved

Note

nnnnH

Program area

1000H

0FFFH

CALLF entry area

0800H

07FFH

Program area

0080H 007FH

CALLT table area

0040H 003FH

Vector table area

0000H

Note The internal ROM and internal high-speed RAM capacities differ depending on the product (see the

following table).

Part Number Last Address of Internal ROM

nnnnH mmmmH

PD780031AY 1FFFH FD00H

PD780032AY 3FFFH

PD780033AY 5FFFH FB00H

PD780034AY 7FFFH

Data Sheet U14045EJ1V0DS00

Start Address of Internal High-Speed RAM

PD780031AY, 780032AY, 780033AY, 780034AY

5. PERIPHERAL HARDWARE FUNCTION FEATURES

5.1 Ports

The following 3 types of I/O ports are available.

• CMOS input (Port 1): 8

• CMOS input/output (Ports 0, 2 to 7, P34 to P36): 39

• N-ch open-drain input/output (P30 to P33): 4 Total: 51

Table 5-1. Port Functions

Name Pin Name Function

Port 0 P00 to P03 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software. Port 1 P10 to P17 Dedicated input port pins. Port 2 P20 to P25 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software. Port 3 P30 to P33 N-ch open-drain I/O port pins. Input/output can be specified in 1-bit units.

The mask option can be used to specify the connection of an on-chip pull-up resistor to P30, P31.

LEDs can be driven directly.

P34 to P36 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software. Port 4 P40 to P47 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software.

The interrupt request flag (KRIF) is set to 1 by falling edge detection. Port 5 P50 to P57 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software.

LEDs can be driven directly. Port 6 P64 to P67 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software. Port 7 P70 to P75 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

5.2 Clock Generator

A system clock generator is incorporated. The minimum instruction execution time can be changed.

• 0.24

s/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38-MHz operation with main system clock)

• 122 µs (@ 32.768-kHz operation with subsystem clock)

Figure 5-1. Clock Generator Block Diagram

XT1

XT2

Subsystem clock oscillator

Main system clock oscillator

STOP

Watch timer, clock output function

Prescaler

Selector

Standby control circuit

Wait control circuit

Prescaler

Clock to peripheral hardware

CPU clock (f

CPU

)

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

5.3 Timer/Counter

Five timer/counter channels are incorporated.

• 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Table 5-2. Operations of Timer/Event Counters

16-Bit Timer/ 8-Bit Timer/ Watch Timer Watchdog Timer

Event Counter TM0 Event Counters TM50, TM51

Operation mode

Interval timer 1 channel 2 channels 1 channel External event counter 1 channel 2 channels — —

Function

Timer output 1 output 2 outputs — — PPG output 1 output — — — PWM output — 2 outputs — — Pulse width measurement 2 inputs — — — Square wave output 1 output 2 outputs — — One-shot pulse output 1 output — — — Interrupt source 2 2 2 1

Note 1

1 channel

Note 2

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer

by selecting either the watchdog timer function or the interval timer function.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter TM0

Internal bus

TI01/P71

fX/2

TI00/TO0/P70

fX/2 fX/2

2 6

Noise elimination circuit

Selector

Noise elimination circuit

16-bit capture/compare register 00 (CR00)

Selector

16-bit timer counter 0 (TM0)

16-bit capture/compare register 01 (CR01)

Internal bus

Match

Clear

Selector

Output control circuit

INTTM00

TO0/TI00/P70

INTTM01

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter TM50

Internal bus

TI50/TO50/P72

fX/2

fX/2 fX/2 fX/2

fX/2

TCL502 TCL501 TCL500

Timer clock select register 50 (TCL50)

8-bit compare register 50 (CR50)

X 2

4 6 8

8-bit timer counter

Selector

50 (TM50)

Match

OVF

Mask circuit

Selector INTTM50

INV

TO50/TI50/P72

Selector

Clear

Selector

TCE50

TMC506 TMC504

S R

LVS50 LVR50

Invert level

TMC501

TOE50

8-bit timer mode control register 50 (TMC50)

Internal bus

Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter TM51

Internal bus

TI51/TO51/P73

fX/2 fX/2 fX/2 fX/2 fX/2

fX/2

TCL512 TCL511 TCL510

Timer clock select register 51 (TCL51)

8-bit compare register 51 (CR51)

Selector

INTTM51

Match

3 5 7 9

Selector

8-bit timer counter 51 (TM51)

Mask circuit

OVF

INV

TO51/TI51/P73

Selector

Clear

Selector

TCE51

TMC516 TMC514

S R

LVS51 LVR51

Invert level

TMC511

TOE51

8-bit timer mode control register 51 (TMC51)

Internal bus

Data Sheet U14045EJ1V0DS00

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