NEC PD780031AY, PD780032AY, PD780033AY, PD780034AY Technical data

查询UPD780031AYCW供应商查询UPD780031AYCW供应商

PD780031AY, 780032AY, 780033AY, 780034AY

8-BIT SINGLE-CHIP MICROCONTROLLERS

DESCRIPTION

The µPD780031AY, 780032AY, 780033AY, and 780034AY are members of the µPD780034AY Subseries of the 78K/0 Series. This is a µPD780034A Subseries product with an added multimaster-supporting I2C bus interface, and is suitable for AV equipment applications.

A flash memory version, the ROM version, and various development tools, are available.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing.

PD780024A, 780034A, 780024AY, 780034AY Subseries User's Manual: U14046E 78K/0 Series User’s Manual Instructions: U12326E

DATA SHEET

MOS INTEGRATED CIRCUIT

PD78F0034AY, that can operate in the same power supply voltage range as the mask

FEATURES

• Internal ROM and RAM

Item Program Memory Data Memory Package

Part Number (Internal ROM) (Internal High-Speed RAM)

PD780031AY 8 Kbytes 512 bytes • 64-pin plastic shrink DIP (750 mils)

PD780032AY 16 Kbytes

PD780033AY 24 Kbytes 1024 bytes

PD780034AY 32 Kbytes

• External memory expansion space: 64 Kbytes

• Minimum instruction execution time: 0.24 µs (@ fX = 8.38-MHz operation)

• I/O ports: 51 (5-V-tolerant N-ch open-drain: 4)

• 10-bit resolution A/D converter: 8 channels (AV

• Serial interface: 3 channels (multimaster-supporting I2C bus mode, UART mode, 3-wire serial I/O mode)

• Timer: 5 channels

• Power supply voltage: V

DD = 1.8 to 5.5 V

DD = 1.8 to 5.5 V)

• 64-pin plastic QFP (14 × 14 mm)

• 64-pin plastic LQFP (12 × 12 mm)

APPLICATIONS

Telephones, home electric appliances, pagers, AV equipment, car audios, office automation equipment, etc.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U14045EJ1V0DS00 (1st edition) Date Published August 1999 N CP(K) Printed in Japan

1999

PD780031AY, 780032AY, 780033AY, 780034AY

ORDERING INFORMATION

Part Number Package

PD780031AYCW-××× 64-pin plastic shrink DIP (750 mils)

PD780031AYGC-×××-AB8 64-pin plastic QFP (14 × 14 mm)

PD780031AYGK-×××-8A8 64-pin plastic LQFP (12 × 12 mm)

PD780032AYCW-××× 64-pin plastic shrink DIP (750 mils)

PD780032AYGC-×××-AB8 64-pin plastic QFP (14 × 14 mm)

PD780032AYGK-×××-8A8 64-pin plastic LQFP (12 × 12 mm)

PD780033AYCW-××× 64-pin plastic shrink DIP (750 mils)

PD780033AYGC-×××-AB8 64-pin plastic QFP (14 × 14 mm)

PD780033AYGK-×××-8A8 64-pin plastic LQFP (12 × 12 mm)

PD780034AYCW-××× 64-pin plastic shrink DIP (750 mils)

PD780034AYGC-×××-AB8 64-pin plastic QFP (14 × 14 mm)

PD780034AYGK-×××-8A8 64-pin plastic LQFP (12 × 12 mm)

Remark ××× indicates ROM code suffix.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

78K/0 SERIES LINEUP

The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.

Products in mass production Products under development

C bus.

100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin

64-pin 64-pin

64-pin 42/44-pin

Control

PD78075B

PD78078

PD78070A

PD780058

PD78058F

PD78054

PD780065

PD780078

PD780034A

PD780024A

PD78014H

PD78018F

PD78083

PD78078Y PD78070AY

PD780018AY

PD780058Y

PD78058FY

PD78054Y

PD780078Y

PD780034AY

PD780024AY

PD78018FY

Y subseries products are compatible with I

EMI-noise reduced version of the PD78078 PD78054 with added timer and enhanced external interface

ROM-less version of the PD78078

PD78078Y with enhanced serial I/O and limited functions

PD78054 with enhanced serial I/O

EMI-noise reduced version of the PD78054

PD78018F with added UART and D/A converter and enhanced I/O

PD780024A with increased RAM capacity

A PD780034A with added timer and enhanced serial I/O

PD780024A with enhanced A/D converter

PD78018F with enhanced serial I/O

EMI-noise reduced version of the PD78018F Basic subseries for control

On-chip UART, capable of operating at low voltage (1.8 V)

78K/0 Series

64-pin

80-pin 80-pin 80-pin

100-pin 100-pin 100-pin

80-pin

100-pin 80-pin 80-pin

80-pin

Inverter control

PD780988

FIP

drive

PD780208100-pin

PD780208

PD780228100-pin

µµ

PD780232

PD78044H

PD78044F

LCD drive

PD780308

PD78064B

PD78064

Call ID supported

PD780841

Bus interface supported

PD780948

PD78098B

PD780308Y

PD78064Y

µµ

PD780701Y

PD780833Y

On-chip inverter control circuit and UART. EMI-noise reduced.

PD78044F with enhanced I/O and FIP C/D. Display output total: 53

PD78044H with enhanced I/O and FIP C/D. Display output total: 48

For panel control. On-chip FIP C/D. Display output total: 53

PD78044F with added N-ch open drain I/O. Display output total: 34

Basic subseries for driving FIP. Display output total: 34

PD78064 with enhanced SIO, and increased ROM, RAM capacity.

EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, on-chip UART

On-chip Call ID and simple DTMF. EMI-noise reduced.

On-chip D-CAN controller

PD78054 with IEBusTM controller added. EMI-noise reduced.

On-chip D-CAN/IEBus controller

On-chip controller compliant with J1850 (Class 2)

100-pin 80-pin

80-pin 80-pin

Meter control

PD780958

PD780955

PD780973

PD780824

For industrial meter control

Ultra low-power consumption. On-chip UART. On-chip automobile meter controller/driver For automobile meter. On-chip D-CAN controller.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

The major functional differences among the Y subseries are shown below.

Function ROM Capacity Configuration of Serial Interface I/O VDD MIN.

Subseries Name Value ControlµPD78078Y 48 K to 60 K 3-wire/2-wire/I2C: 1 ch 88 1.8 V

PD78070AY —

PD780018AY 48 K to 60 K 3-wire with automatic transmit/receive function: 1 ch 88

PD780058Y 24 K to 60 K 3-wire/2-wire/I2C: 1 ch 68 1.8 V

PD78058FY 48 K to 60 K 3-wire/2-wire/I2C: 1 ch 69 2.7 V

PD78054Y 16 K to 60 K

PD780078Y 48 K to 60 K 3-wire: 1 ch 52 1.8 V

PD780034AY 8 K to 32 K UART: 1 ch 51 1.8 V

PD780024AY

PD78018FY 8 K to 60 K 3-wire/2-wire/I2C: 1 ch 53

LCD drive 3-wire/time-division UART: 1 ch

PD780308Y 48 K to 60 K 3-wire/2-wire/I2C: 1 ch 57 2.0 V

PD78064Y 16 K to 32 K 3-wire/2-wire/I2C: 1 ch

3-wire with automatic transmit/receive function: 1 ch 3-wire/UART: 1 ch

Time-division 3-wire: 1 ch I2C bus (multimaster supported): 1 ch

3-wire with automatic transmit/receive function: 1 ch 3-wire/time-division UART: 1 ch

3-wire with automatic transmit/receive function: 1 ch 3-wire/UART: 1 ch

UART: 1 ch 3-wire/UART: 1 ch I2C bus (multimaster supported): 1 ch

3-wire: 1 ch I2C bus (multimaster supported): 1 ch

3-wire with automatic transmit/receive function: 1 ch

3-wire: 1 ch

3-wire/UART: 1 ch

61 2.7 V

2.0 V

Remark Functions other than the serial interface are common to the non-Y subseries.

Data Sheet U14045EJ1V0DS00

OVERVIEW OF FUNCTIONS

PD780031AY, 780032AY, 780033AY, 780034AY

Part Number

Item Internal ROM 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes memory High-speed RAM 512 bytes 1024 bytes Memory space 64 Kbytes General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution On-chip minimum instruction execution time cycle variable function

time

Instruction set • 16-bit operation

I/O ports Total: 51

A/D converter • 10-bit resolution x 8 channels

Serial interface • 3-wire serial I/O mode: 1 channel

Timer • 16-bit timer/event counter: 1 channel

Timer output 3 (8-bit PWM output capable: 2) Clock output • 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz

Buzzer output 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38-MHz operation with main system clock) Vectored Maskable Internal: 13, external: 5 interrupt Non-maskable Internal: 1 sources Software 1 Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package • 64-pin plastic shrink DIP (750 mils)

When main system 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38-MHz operation) clock selected

When subsystem 122 µs (@ 32.768-kHz operation) clock selected

PD780031AY

• Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjust, etc.

• CMOS input: 8

• CMOS I/O: 39

• 5-V-tolerant N-ch open-drain I/O: 4

• Low-voltage operation available: AVDD = 1.8 to 5.5 V

• UART mode: 1 channel

• I2C bus mode (multimaster supported): 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

(@ 8.38-MHz operation with main system clock )

• 32.768 kHz (@ 32.768-kHz operation with subsystem clock)

• 64-pin plastic QFP (14 × 14 mm)

• 64-pin plastic LQFP (12 × 12 mm)

PD780032AY

PD780033AY

PD780034AY

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

CONTENTS

1. PIN CONFIGURATION (Top View) .....................................................................................................7

2. BLOCK DIAGRAM .............................................................................................................................10

3. PIN FUNCTIONS ................................................................................................................................11

3.1 Port Pins .................................................................................................................................................... 11

3.2 Non-Port Pins............................................................................................................................................ 12

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins..................................................... 14

4. MEMORY SPACE ............................................................................................................................... 16

5. PERIPHERAL HARDWARE FUNCTION FEATURES .......................................................................17

5.1 Ports ........................................................................................................................................................... 17

5.2 Clock Generator ........................................................................................................................................ 18

5.3 Timer/Counter ........................................................................................................................................... 19

5.4 Clock Output/Buzzer Output Control Circuit ....................................................................................... 2 3

5.5 A/D Converter ........................................................................................................................................... 24

5.6 Serial Interface.......................................................................................................................................... 25

6. INTERRUPT FUNCTION....................................................................................................................28

7. EXTERNAL DEVICE EXPANSION FUNCTION ...............................................................................31

8. STANDBY FUNCTION .......................................................................................................................31

9. RESET FUNCTION ............................................................................................................................31

10. MASK OPTION...................................................................................................................................31

11. INSTRUCTION SET ...........................................................................................................................32

12. ELECTRICAL SPECIFICATIONS......................................................................................................34

13. PACKAGE DRAWINGS .....................................................................................................................57

14. RECOMMENDED SOLDERING CONDITIONS ................................................................................60

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................62

APPENDIX B. RELATED DOCUMENTS ...............................................................................................65

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

1. PIN CONFIGURATION (Top View)

• 64-pin plastic shrink DIP (750 mils)

PD780031AYCW-×××, 780032AYCW-×××, 780033AYCW-×××, 780034AYCW-×××

P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7

P50/A8

P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15

SS0

VDD0

P30 P31

P32/SDA0

P33/SCL0

P34 P35 P36

P20/SI30

P21/SO30

P22/SCK30

P23/RxD0

P24/TxD0

P25/ASCK0

DD1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P67/ASTB P66/WAIT P65/WR P64/RD P75/BUZ P74/PCL P73/TI51/TO51 P72/TI50/TO50 P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0

SS1

V X1 X2 IC XT1 XT2 RESET

AV AVREF P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AV

Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.

2. Connect the AV

SS pin to VSS0.

Remark When the µPD780031AY, 780032AY, 780033AY, and 780034AY are used in applications where the

noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to V

DD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

• 64-pin plastic QFP (14 × 14 mm)

PD780031AYGC-×××-AB8, 780032AYGC-×××-AB8, 780033AYGC-×××-AB8, 780034AYGC-×××-AB8

• 64-pin plastic LQFP (12 × 12 mm)

PD780031AYGK-×××-8A8, 780032AYGK-×××-8A8, 780033AYGK-×××-8A8, 780034AYGK-×××-8A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P75/BUZ

P74/PCL

P73/TI51/TO51

P72/TI50/TO50

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P50/A8

P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15

SS0

V V

DD0

P30 P31

P32/SDA0

P33/SCL0

P34 P35

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P71/TI01 P70/TI00/TO0 P03/INTP3/ADTRG P02/INTP2 P01/INTP1 P00/INTP0 V

SS1

X1 X2 IC XT1 XT2 RESET

AV AV

REF

P10/ANI0

P36

P20/SI30

P21/SO30

P24/TxD0

P23/RxD0

P22/SCK30

DD1

P25/ASCK0

P17/ANI7

P16/ANI6

Cautions 1. Connect the IC (Internally Connected) pin directly to V

2. Connect the AVSS pin to VSS0.

Remark When the

PD780031AY, 780032AY, 780033AY, and 780034AY are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to V

DD0 and VDD1 individually and connecting VSS0 and VSS1 to

different ground lines, is recommended.

Data Sheet U14045EJ1V0DS00

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

SS0 or VSS1.

PD780031AY, 780032AY, 780033AY, 780034AY

A8 to A15: Address Bus AD0 to AD7: Address/Data Bus ADTRG: AD Trigger Input ANI0 to ANI7: Analog Input ASCK0: Asynchronous Serial Clock ASTB: Address Strobe

DD: Analog Power Supply

AV AVREF: Analog Reference Voltage

SS: Analog Ground

AV BUZ: Buzzer Clock IC: Internally Connected INTP0 to INTP3: External Interrupt Input P00 to P03: Port 0 P10 to P17: Port 1 P20 to P25: Port 2 P30 to P36: Port 3 P40 to P47: Port 4 P50 to P57: Port 5 P64 to P67: Port 6

P70 to P75: Port 7 PCL: Programmable Clock RD: Read Strobe RESET: Reset RxD0: Receive Data SCK30, SCL0: Serial Clock SDA0: Serial Data SI30: Serial Input SO30: Serial Output TI00, TI01, TI50, TI51: Timer Input TO0, TO50, TO51: Timer Output TxD0: Transmit Data

DD0, VDD1: Power Supply

V VSS0, VSS1: Ground WAIT: Wait WR: Write Strobe X1, X2: Crystal (Main System Clock) XT1, XT2: Crystal (Subsystem Clock)

Data Sheet U14045EJ1V0DS00

2. BLOCK DIAGRAM

PD780031AY, 780032AY, 780033AY, 780034AY

TI00/TO0/P70

TI01/P71

TI50/TO50/P72

TI51/TO51/P73

SI30/P20

SO30/P21

SCK30/P22

RxD0/P23

TxD0/P24

ASCK0/P25

SDA0/P32 SCL0/P33

ANI0/P10 to

ANI7/P17

AV AV

REF

INTP0/P00 to

INTP3/P03

BUZ/P75

PCL/P74

16-BIT TIMER/ EVENT COUNTER

8-BIT TIMER/ EVENT COUNTER 50

8-BIT TIMER/ EVENT COUNTER 51

WATCHDOG TIMER

WATCH TIMER

SERIAL INTERFACE 30

UART0

I2C BUS

DD SS

A/D CONVERTER

INTERRUPT CONTROL

BUZZER OUTPUT

CLOCK OUTPUT CONTROL

78K/0

CPU CORE

RAM

DD0VDD1VSS0VSS1

ROM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7 P70 to P75

EXTERNAL ACCESS

SYSTEM CONTROL

P00 to P03

P10 to P17

P20 to P25

P30 to P36

P40 to P47

P50 to P57

P64 to P67

AD0/P40 to AD7/P47

A8/P50 to A15/P57

RD/P64 WR/P65 WAIT/P66 ASTB/P67

RESET X1 X2 XT1 XT2

Remark The internal ROM and RAM capacities differ depending on the product.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin Name I/O Function After Alternate

Reset Function P00 I/O Port 0 Input INTP0 P01 P02 P03 P10 to P17 Input Port 1 Input ANI0 to ANI7

P20 I/O Port 2 Input SI30 P21 P22 P23 P24 TxD0 P25 ASCK0 P30 I/O Port 3 N-ch open-drain input/output port Input — P31 P32 P33 P34 An on-chip pull-up resistor can be — P35 P36 P40 to P47 I/O Port 4 Input AD0 to AD7

P50 to P57 I/O Port 5 Input A8 to A15

P64 I/O Port 6 Input RD P65 P66 P67

4-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

8-bit input-only port

6-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

7-bit input/output port The mask option can be used to specify the Input/output can be specified in 1-bit units. LEDs can be driven directly.

8-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software. The interrupt request flag (KRIF) is set to 1 by falling edge detection.

8-bit input/output port LEDs can be driven directly. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

4-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

connection of an on-chip pull-up resistor to P30, P31.

connected by means of software.

INTP1 INTP2 INTP3/ADTRG

SO30 SCK30 RxD0

SDA0 SCL0

WR WAIT ASTB

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

3.1 Port Pins (2/2)

Pin Name I/O Function After Alternate

Reset Function P70 I/O Port 7 Input TI00/TO0 P71 P72 P73 P74 PCL P75 BUZ

6-bit input/output port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be connected by means of software.

TI01 TI50/TO50 TI51/TO51

3.2 Non-Port Pins (1/2)

Pin Name I/O Function After Alternate

Reset Function INTP0 Input External interrupt request input for which the valid edge (rising edge, Input P00

INTP1 INTP2 P02 INTP3 P03/ADTRG SI30 Input Serial interface serial data input Input P20 SO30 Output Serial interface serial data output Input P21 SDA0 I/O Serial interface serial data input/output Input P32 SCK30 I/O Serial interface serial clock input/output Input P22 SCL0 P33 RxD0 Input Serial data input for asynchronous serial interface Input P23 TxD0 Output Serial data output for asynchronous serial interface Input P24 ASCK0 Input Serial clock input for asynchronous serial interface Input P25 TI00 Input External count clock input to 16-bit timer (TM0) Input P70/TO0

TI01 Capture trigger input to capture register (CR00) of 16-bit timer (TM0) P71 TI50 External count clock input to 8-bit timer (TM50) P72/TO50 TI51 External count clock input to 8-bit timer (TM51) P73/TO51 TO0 Output 16-bit timer (TM0) output Input P70/TI00 TO50 8-bit timer (TM50) output (also used for 8-bit PWM output) Input P72/TI50 TO51 8-bit timer (TM51) output (also used for 8-bit PWM output) P73/TI51 PCL Output Clock output (for trimming of main system clock and subsystem clock) Input P74 BUZ Output Buzzer output Input P75 AD0 to AD7 I/O Lower address/data bus for expanding memory externally Input P40 to P47 A8 to A15 Output Higher address bus for expanding memory externally Input P50 to P57 RD Output Strobe signal output for reading from external memory Input P64 WR Strobe signal output for writing to external memory P65 WAIT Input Wait insertion at external memory access Input P66 ASTB Output Strobe output that externally latches address information output to Input P67

falling edge, or both rising and falling edges) can be specified

Capture trigger input to capture register (CR01) of 16-bit timer (TM0)

ports 4 and 5 to access external memory

P01

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

3.2 Non-Port Pins (2/2)

Pin Name I/O Function After Alternate

Reset Function ANI0 to ANI7 Input A/D converter analog input Input P10 to P17 ADTRG Input A/D converter trigger signal input Input P03/INTP3 AVREF Input A/D converter reference voltage input — — AVDD — A/D converter analog power supply. Set potential to that of VDD0 or VDD1.— — AVSS — A/D converter ground potential. Set potential to that of VSS0 or VSS1.—— RESET Input System reset input — — X1 Input Connecting crystal resonator for main system clock oscillation — — X2 — —— XT1 Input Connecting crystal resonator for subsystem clock oscillation — — XT2 — —— VDD0 — Positive power supply for ports — — VSS0 — Ground potential of ports — — VDD1 — Positive power supply (except ports) — — VSS1 — Ground potential (except ports) — — IC — Internally connected. Connect directly to VSS0 or VSS1.——

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1.

Table 3-1. Types of Pin Input/Output Circuits

Pin Name Input/Output I/O Recommended Connection of Unused Pins

Circuit Type P00/INTP0 to P02/INTP2 8-C Input Independently connect to VSS0 via a resistor. P03/INTP3/ADTRG P10/ANI0 to P17/ANI7 25 Input Independently connect to VDD0 or VSS0 via a resistor. P20/SI30 8-C I/O P21/SO30 5-H P22/SCK30 8-C P23/RxD0 P24/TxD0 5-H P25/ASCK0 8-C P30, P31 13-Q I/O Independently connect to VDD0 via a resistor. P32/SDA0 13-R P33/SCL0 P34 8-C Independently connect to VDD0 or VSS0 via a resistor. P35 5-H P36 8-C P40/AD0 to P47/AD7 5-H I/O Independently connect to VDD0 via a resistor. P50/A8 to P57/A15 I/O Independently connect to VDD0 or VSS0 via a resistor. P64/RD I/O P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 8-C P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL 5-H P75/BUZ RESET 2 Input — XT1 16 Connect to VDD0. XT2 — Leave open. AVDD — Connect to VDD0. AVREF Connect to VSS0. AVSS IC Connect directly to VSS0 or VSS1.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Figure 3-1. Pin Input/Output Circuits

TYPE 2

Schmitt-triggered input with hysteresis characteristics

TYPE 5-H

Pullup

enable

Data

Output

disable

DD0

P-ch

N-ch

SS0

DD0

P-ch

IN/OUT

TYPE 13-R

Data

Output disable

TYPE 16

Feedback cut-off

P-ch

IN/OUT

N-ch

SS0

Input

enable

TYPE 8-C

Pullup

enable

Data

Output

disable

TYPE 13-Q

Data

Output disable

  

DD0

P-ch

N-ch

Mask option

SS0

N-ch

SS0

XT1 XT2

TYPE 25

DD0

P-ch

IN/OUT

Comparator

–

N-ch

SS0

REF

(threshold voltage)

Input

enable

DD0

  

IN/OUT

Input

enable

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

4. MEMORY SPACE

Figure 4-1 shows the memory map of the µPD780031AY, 780032AY, 780033AY, and 780034AY.

Figure 4-1. Memory Map

FFFFH

Special function registers

(SFRs) 256 × 8 bits

FF00H

FEFFH

FEE0H FEDFH

General-purpose

registers

32 × 8 bits

Data memory space

Program memory space

mmmmH

mmmmH – 1

F800H F7FFH

nnnnH + 1

nnnnH

0000H

Internal high-speed

External memory

Internal ROM

Note

RAM

Reserved

Note

nnnnH

Program area

1000H

0FFFH

CALLF entry area

0800H

07FFH

Program area

0080H 007FH

CALLT table area

0040H 003FH

Vector table area

0000H

Note The internal ROM and internal high-speed RAM capacities differ depending on the product (see the

following table).

Part Number Last Address of Internal ROM

nnnnH mmmmH

PD780031AY 1FFFH FD00H

PD780032AY 3FFFH

PD780033AY 5FFFH FB00H

PD780034AY 7FFFH

Data Sheet U14045EJ1V0DS00

Start Address of Internal High-Speed RAM

PD780031AY, 780032AY, 780033AY, 780034AY

5. PERIPHERAL HARDWARE FUNCTION FEATURES

5.1 Ports

The following 3 types of I/O ports are available.

• CMOS input (Port 1): 8

• CMOS input/output (Ports 0, 2 to 7, P34 to P36): 39

• N-ch open-drain input/output (P30 to P33): 4 Total: 51

Table 5-1. Port Functions

Name Pin Name Function

Port 0 P00 to P03 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software. Port 1 P10 to P17 Dedicated input port pins. Port 2 P20 to P25 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software. Port 3 P30 to P33 N-ch open-drain I/O port pins. Input/output can be specified in 1-bit units.

The mask option can be used to specify the connection of an on-chip pull-up resistor to P30, P31.

LEDs can be driven directly.

P34 to P36 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software. Port 4 P40 to P47 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software.

The interrupt request flag (KRIF) is set to 1 by falling edge detection. Port 5 P50 to P57 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software.

LEDs can be driven directly. Port 6 P64 to P67 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software. Port 7 P70 to P75 I/O port pins. Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be connected by means of software.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

5.2 Clock Generator

A system clock generator is incorporated. The minimum instruction execution time can be changed.

• 0.24

s/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38-MHz operation with main system clock)

• 122 µs (@ 32.768-kHz operation with subsystem clock)

Figure 5-1. Clock Generator Block Diagram

XT1

XT2

Subsystem clock oscillator

Main system clock oscillator

STOP

Watch timer, clock output function

Prescaler

Selector

Standby control circuit

Wait control circuit

Prescaler

Clock to peripheral hardware

CPU clock (f

CPU

)

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

5.3 Timer/Counter

Five timer/counter channels are incorporated.

• 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Table 5-2. Operations of Timer/Event Counters

16-Bit Timer/ 8-Bit Timer/ Watch Timer Watchdog Timer

Event Counter TM0 Event Counters TM50, TM51

Operation mode

Interval timer 1 channel 2 channels 1 channel External event counter 1 channel 2 channels — —

Function

Timer output 1 output 2 outputs — — PPG output 1 output — — — PWM output — 2 outputs — — Pulse width measurement 2 inputs — — — Square wave output 1 output 2 outputs — — One-shot pulse output 1 output — — — Interrupt source 2 2 2 1

Note 1

1 channel

Note 2

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer

by selecting either the watchdog timer function or the interval timer function.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter TM0

Internal bus

TI01/P71

fX/2

TI00/TO0/P70

fX/2 fX/2

2 6

Noise elimination circuit

Selector

Noise elimination circuit

16-bit capture/compare register 00 (CR00)

Selector

16-bit timer counter 0 (TM0)

16-bit capture/compare register 01 (CR01)

Internal bus

Match

Clear

Selector

Output control circuit

INTTM00

TO0/TI00/P70

INTTM01

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter TM50

Internal bus

TI50/TO50/P72

fX/2

fX/2 fX/2 fX/2

fX/2

TCL502 TCL501 TCL500

Timer clock select register 50 (TCL50)

8-bit compare register 50 (CR50)

X 2

4 6 8

8-bit timer counter

Selector

50 (TM50)

Match

OVF

Mask circuit

Selector INTTM50

INV

TO50/TI50/P72

Selector

Clear

Selector

TCE50

TMC506 TMC504

S R

LVS50 LVR50

Invert level

TMC501

TOE50

8-bit timer mode control register 50 (TMC50)

Internal bus

Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter TM51

Internal bus

TI51/TO51/P73

fX/2 fX/2 fX/2 fX/2 fX/2

fX/2

TCL512 TCL511 TCL510

Timer clock select register 51 (TCL51)

8-bit compare register 51 (CR51)

Selector

INTTM51

Match

3 5 7 9

Selector

8-bit timer counter 51 (TM51)

Mask circuit

OVF

INV

TO51/TI51/P73

Selector

Clear

Selector

TCE51

TMC516 TMC514

S R

LVS51 LVR51

Invert level

TMC511

TOE51

8-bit timer mode control register 51 (TMC51)

Internal bus

Data Sheet U14045EJ1V0DS00

fX/2

PD780031AY, 780032AY, 780033AY, 780034AY

Figure 5-5. Watch Timer Block Diagram

Clear

Selector

9-bit prescaler

Selector

WTM7 WTM6 WTM5 WTM4 WTM1 WTM0

Watch timer operation mode register (WTM)

Internal bus

5-bit counter INTWT

Clear

INTWTI

fX/2

OSTS2 OSTS1 OSTS0 WDCS2 WDCS1 WDCS0

Oscillation stabilization time select register (OSTS)

Figure 5-6. Watchdog Timer Block Diagram

Clock input control circuit

RUN

Division circuit

Division mode selection circuit

Watchdog timer clock select register (WDCS)

Divided clock selection circuit

Internal bus

RUN WDTM4 WDTM3

Watchdog timer mode register (WDTM)

Output control circuit

INTWDT

RESET

WDT mode signal

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

5.4 Clock Output/Buzzer Output Control Circuit

A clock output/buzzer output control circuit (CKU) is incorporated. Clocks with the following frequencies can be output as clock output.

• 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (@ 8.38-MHz operation with main system clock)

• 32.768 kHz (@ 32.768-kHz operation with subsystem clock)

Clocks with the following frequencies can be output as buzzer output.

• 1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (@ 8.38-MHz operation with main system clock)

Figure 5-7. Block Diagram of Clock Output/Buzzer Output Control Circuit CKU

fXT

BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0

Prescaler

Clock output select register (CKS)

Internal bus

fX to fX/2

fX/210 to fX/2

Selector

BZOE

Clock

control

circuit

CLOE

BUZ/P75

BCS0, BCS1

PCL/P74

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

5.5 A/D Converter

An A/D converter consisting of eight 10-bit resolution channels is incorporated. The following two A/D conversion operation start-up methods are available.

• Hardware start

• Software start

Figure 5-8. A/D Converter Block Diagram

ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17

Selector

Sample & hold circuit

Voltage comparator

Succesive approximation register (SAR)

Series resistor string

Tap selector

AV AV

REF

ADTRG/INTP3/P03

Edge detection circuit

Control circuit

A/D conversion result register 0 (ADCR0)

Internal bus

INTAD

INTP3

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

5.6 Serial Interface

Three serial interface channels are incorporated.

• Serial interface UART0: 1 channel

• Serial interface SIO30: 1 channel

• Serial interface IIC0: 1 channel

(1) Serial interface UART0

The serial interface UART0 has two modes: asynchronous serial interface (UART) mode and infrared data transfer mode.

• Asynchronous serial interface (UART) mode

This mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted and received. The on-chip UART-dedicated baud-rate generator enables communication using a wide range of selectable baud rates. In addition, a baud rate can be also defined by dividing the clock input to the ASCK0 pin. The UART-dedicated baud-rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps).

RxD0/P23

TxD0/P24

• Infrared data transfer mode

This mode enables pulse output and pulse reception in data format. This mode can be used for office equipment applications such as personal computers.

Figure 5-9. Block Diagram of Serial Interface UART0

Internal bus

Receive buffer

RXB0

RX0

Receive shift register 0

Receive control circuit (parity check)

PE0 FE0

INTSR0

Asynchronous serial interface status register 0 (ASIS0)

OVE0

TXS0

INTSER0

Transmit shift register 0

Transmit control circuit (parity addition)

TXE0 RXE0

INTST0

PS01 PS00

CL0 SL0

Asynchronous serial interface mode register 0 (ASIM0)

ISRM0

IRDAM0

Data Sheet U14045EJ1V0DS00

Baud rate generator

ASCK0/P25

/2 to fX/2

PD780031AY, 780032AY, 780033AY, 780034AY

(2) Serial interface SIO30

The serial interface SIO30 has one mode: 3-wire serial I/O mode.

• 3-wire serial I/O mode (fixed as MSB first)

This is an 8-bit data transfer mode using three lines: a serial clock line (SCK30), serial output line (SO30), and serial input line (SI30). Since simultaneous transmit and receive operations are enabled in the 3-wire serial I/O mode, the processing time for data transfer is reduced. The first bit in 8-bit data in the serial transfer is fixed as MSB. The 3-wire serial I/O mode is useful for connection to peripheral I/O devices, display controllers, etc. that include a clocked serial interface.

Figure 5-10. Block Diagram of Serial Interface SIO30

Internal bus

SI30/P20

Serial I/O shift register 30 (SIO30)

SO30/P21

SCK30/P22

Serial clock counter

Serial clock control circuit

Interrupt request signal generator

Selector

INTCSI30

fX/2

Data Sheet U14045EJ1V0DS00

(3) Serial interface IIC0

The serial interface IIC0 has the I2C (Inter IC) bus mode (multimaster supported).

C bus mode (multimaster supported)

•I

This is an 8-bit data transfer mode using two lines: a serial clock line (SCL0) and serial data bus line (SDA0). This mode complies with the I during transmission via the serial data bus. This data is automatically detected by hardware during reception. Since the SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the serial data bus line are required.

SDA0/P32

Noise elimination circuit

PD780031AY, 780032AY, 780033AY, 780034AY

C bus format, and can output "start condition", "data", and "stop condition"

Figure 5-11. Block Diagram of Serial Interface IIC0

Internal bus

IIC control register 0

Slave address register 0 (SVA0)

Matched signal

IIC shift register 0 (IIC0)

IICE0

CLEAR

(IICC0)

LREL0

SET

SO0 latch

CL00

WREL0

SPIE0

WTIM0

ACKE0

IIC status register 0

(IICS0)

MSTS0

ALD0 EXC0 COI0 TRC0

STT0 SPT0

ACKD0

STD0 SPD0

SCL0/P33

N-ch opendrain output

Noise elimination circuit

N-ch open-drain output

Acknowledge

detection circuit

Start condition detection circuit

Stop condition detection circuit

Serial clock counter

Serial clock control circuit

DAD0 SMC0 DFC0

CLD0

Data hold time correction circuit

Prescaler

Serial clock wait control circuit

IIC transfer clock select

CL00

Acknowledge detection circuit

Wake-up control circuit

Interrupt request signal generator

INTIIC0

Internal bus

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

6. INTERRUPT FUNCTION

A total of 20 interrupt sources are provided, divided into the following three types.

• Non-maskable: 1

• Maskable: 18

• Software: 1

Table 6-1. Interrupt Source List

Interrupt Default Interrupt Source Internal/ Vector Table

Type Priority

Non- — INTWDT Watchdog timer overflow (with watchdog timer Internal 0004H (A) maskable mode 1 selected)

Maskable 0 INTWDT Watchdog timer overflow (with interval timer (B)

Software — BRK Execution of BRK instruction — 003EH (E)

Note 1

1 INTP0 Pin input edge detection External 0006H (C) 2 INTP1 0008H 3 INTP2 000AH 4 INTP3 000CH 5 INTSER0 Generation of serial interface UART0 Internal 000EH (B)

6 INTSR0 End of serial interface UART0 reception 0010H 7 INTST0 End of serial interface UART0 transmission 0012H 8 INTCSI30 End of serial interface SIO30 transfer 0014H

9 INTIIC0 End of serial interface IIC0 transfer 0016H 10 INTWTI Reference time interval signal from watch timer 001AH 11 INTTM00 Matching of TM0 and CR00 (when CR00 is 001CH

12 INTTM01 Matching of TM0 and CR01 (when CR01 is 001EH

13 INTTM50 Matching of TM50 and CR50 0020H 14 INTTM51 Matching of TM51 and CR51 0022H 15 INTAD0 End of conversion by A/D converter 0024H 16 INTWT Watch timer overflow 0026H 17 INTKR Detection of port 4 falling edge External 0028H (D)

Name Trigger External Address

mode selected)

reception error

specified as a compare register) Detection of TI01 pin valid edge (when CR00 is specified as a capture register)

specified as a compare register) Detection of TI00 pin valid edge (when CR00 is specified as a capture register)

Basic

Configuration

Type

Note 2

Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same

time. 0 is the highest and 17 is the lowest.

2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.

Data Sheet U14045EJ1V0DS00

Figure 6-1. Basic Configuration of Interrupt Function (1/2)

(A) Internal non-maskable interrupt

PD780031AY, 780032AY, 780033AY, 780034AY

Internal bus

Interrupt request

(B) Internal maskable interrupt

Interrupt request

Priority control circuit

Internal bus

Priority control circuit

Vector table address generator

PR ISP

Standby release signal

Vector table address generator

Standby release signal

Internal bus

External interrupt edge enable register (EGP, EGN)

Interrupt request

Edge detection circuit

Data Sheet U14045EJ1V0DS00

MK IE

PR ISP

Priority control circuit

Vector table address generator

Standby release signal

Figure 6-1. Basic Configuration of Interrupt Function (2/2)

(D) External maskable interrupt (INTKR)

PD780031AY, 780032AY, 780033AY, 780034AY

Internal bus

Interrupt request

1 when MEM = 01H

(E) Software interrupt

IF: Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag MEM: Memory expansion mode register

Falling edge detection circuit

Interrupt request

MK IE

Priority control circuit

Internal bus

PR ISP

Priority control circuit

Vector table address generator

Standby release signal

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

7. EXTERNAL DEVICE EXPANSION FUNCTION

The external device expansion function is for connecting external devices to areas other than the internal ROM,

RAM, and SFR. Ports 4 to 6 are used for external device connection.

8. STANDBY FUNCTION

The following two standby modes are available for further reduction of system current consumption.

• HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode.

• STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. This can be used only when the main system clock is operating (the subsystem clock oscillation cannot be stopped).

Figure 8-1. Standby Function

Main system clock operation

STOP

Interrupt

request

STOP mode

Main system clock

operation is stopped

instruction

Interrupt request

CSS = 1

CSS = 0

HALT instruction

HALT mode HALT mode

Clock supply for CPU is stopped,

oscillation is maintained

9. RESET FUNCTION

The following two reset methods are available.

• External reset by RESET signal input

• Internal reset by watchdog timer runaway time detection

10. MASK OPTION

Table 10.1 Pin Mask Option Selection

Subsystem clock operation

HALT instruction

Interrupt request

Clock supply for CPU is stopped,

oscillation is maintained

Pins Mask Option

P30, P31 An on-chip pull-up resistor can be specified in 1-bit units.

The mask option can be used to specify the connection of an on-chip pull-up resistor to P30, P31, in 1-bit units.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

11. INSTRUCTION SET

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ

2nd Operand

1st Operand

B, C sfr

saddr

!addr16 PSW

[DE] [HL]

[HL + byte] [HL + B]

[HL + C]

X C

#byte A r

ADD ADDC SUB SUBC

AND OR XOR

CMP

MOV MOV

ADD ADDC SUB SUBC

AND OR XOR

CMP

MOV MOV MOV

ADD ADDC SUB SUBC

AND

XOR CMP

MOV DBNZ INC

MOV MOVMOV PUSH

MOV MOV

MOV

[HL + byte]

Note

MOV MOV MOV MOV MOV MOV MOV MOV ROR

XCH XCH XCH XCH XCH XCH XCH ROL ADD ADDC ADDC ADDC ADDC ADDC SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBC SUBC AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMPCMP CMP CMP

sfr saddr !addr16 PSW [DE] [HL]

ADD ADD ADD ADD

[HL + B] [HL + C]

$addr16 1

RORC ROLC

DBNZ

None

INC

DEC

POP

ROR4 ROL4

MULU

DIVUW

Note Except r = A

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand

1st Operand

sfrp saddrp

!addr16 SP

#word

ADDW SUBW

CMPW MOVW

MOVW MOVW

MOVW

MOVW MOVW MOVW

MOVW

Note Only when rp = BC, DE or HL

(3) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

2nd Operand

1st Operand

A.bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

A.bit sfr.bit

MOV1 AND1 OR1 XOR1

Note

MOVW XCHW

Note

saddr.bit PSW.bit [HL].bit CY $addr16 None

MOV1 AND1 OR1 XOR1

MOVW

MOV1 AND1 OR1 XOR1

sfrp

saddrp

MOVW

MOV1 AND1 OR1 XOR1

!addr16 MOVW

MOV1

MOVW

BT BF BTCLR

None

INCW, DECW PUSH, POP

SET1 CLR1

SET1 CLR1 NOT1

(4) Call instructions/branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

2nd Operand

1st Operand Basic instruction

Compound instruction

AX !addr16 !addr11 [addr5] $addr16

BR CALL

CALLF CALLT BR, BC, BNC

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

Data Sheet U14045EJ1V0DS00

BZ, BNZ BT, BF

BTCLR DBNZ

PD780031AY, 780032AY, 780033AY, 780034AY

12. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter Symbol Test Conditions Ratings Unit

Supply voltage VDD –0.3 to +6.5 V

AVDD –0.3 to VDD + 0.3 AVREF –0.3 to VDD + 0.3 AVSS –0.3 to +0.3 V

Input voltage VI1

VI2 P30 to P33 N-ch open-drain Without pull-up resistor –0.3 to +6.5 V

Output voltage VO –0.3 to VDD + 0.3 Analog input voltage

Output current, IOH Per pin –10 mA high

Output current, IOL Per pin for P00 to P03, P20 to P25, P34 to 20 mA low P36, P40 to P47, P64 to P67, P70 to P75

Operating ambient TA –40 to +85 °C temperature

Storage Tstg –65 to +150 °C temperature

VAN P10 to P17 Analog input pin

P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2, RESET

With pull-up resistor –0.3 to VDD + 0.3

Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75 Total for P20 to P25, P30 to P36 –15 mA

Per pin for P30 to P33, P50 to P57 30 mA Total for P00 to P03, P40 to P47, 50 mA

P64 to P67, P70 to P75 Total for P20 to P25 20 mA Total for P30 to P36 100 mA Total for P50 to P57 100 mA

–0.3 to VDD + 0.3

AVSS – 0.3 to AVREF + 0.3

and –0.3 to VDD + 0.3

–15 mA

Note

V V

V V V

Note 6.5 V or below

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Capacitance (TA = 25°C, VDD = VSS = 0 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Input CIN f = 1 MHz 15 pF capacitance Unmeasured pins returned to 0 V.

I/O CIO f = 1 MHz P00 to P03, P20 to P25, 15 pF capacitance Unmeasured pins P34 to P36, P40 to P47,

returned to 0 V. P50 to P57, P64 to P67,

P70 to P75 P30 to P33 20 pF

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.

Main System Clock Oscillator Characteristics (TA = –40 to 85°C, VDD = 1.8 to 5.5 V)

Resonator

Ceramic Oscillation VDD = 4.0 to 5.5 V 1.0 8.38 MHz resonator frequency (fX)

Recommended

Circuit

X1 X2

Parameter Test Conditions MIN. TYP. MAX. Unit

Note 1

1.0 5.0

Oscillation After VDD reaches 4 ms stabilization time

Note 2

oscillation voltage range MIN.

Crystal Oscillation VDD = 4.0 to 5.5 V 1.0 8.38 MHz resonator frequency (fX)

X1 X2

Oscillation VDD = 4.0 to 5.5 V 10 ms stabilization time

Note 1

Note 2

1.0 5.0

External X1 input VDD = 4.0 to 5.5 V 1.0 8.38 MHz clock frequency (fX)

X2X1

Note 1

1.0 5.0

X1 input VDD = 4.0 to 5.5 V 50 500 ns

PD74HCU04

high-/low-level width

85 500

(tXH, tXL)

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release.

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V

SS1.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator

Crystal resonator

External clock

Recommended Circuit

XT2 XT1

PD74HCU04

XT1XT2

Parameter

Oscillation frequency (fXT)

Oscillation stabilization time

XT1 input frequency (fXT)

XT1 input high-/low-level width (tXTH , tXTL)

Note 1

Note 2

Note 1

Test Conditions

VDD = 4.0 to 5.5 V

MIN.

TYP.

32.768

1.2

515

MAX.

38.5

Unit

kHz

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V

SS1.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used.

Data Sheet U14045EJ1V0DS00

Recommended Oscillator Constant

PD780031AY, 780032AY, 780033AY, 780034AY

Main system clock: Ceramic resonator (T

Manufacturer Part Number Frequency Recommended Circuit Constant Oscillation Voltage Range

Murata Mfg. CSB1000J 1.00 100 100 1.8 5.5 Co., Ltd.

TDK CCR3.58MC3 3.58 On-chip On-chip 1.8 5.5

CSA2.00MG040 2.00 100 100 1.8 5.5 CST2.00MG040 2.00 On-chip On-chip 1.8 5.5 CSA3.58MG 3.58 30 30 1.8 5.5 CST3.58MGW 3.58 On-chip On-chip 1.8 5.5 CSA4.19MG 4.19 30 30 1.8 5.5 CST4.19MGW 4.19 On-chip On-chip 1.8 5.5 CSA5.00MG 5.00 30 30 1.8 5.5 CST5.00MGW 5.00 On-chip On-chip 1.8 5.5 CSA8.00MTZ 8.00 30 30 4.0 5.5 CST8.00MTW 8.00 On-chip On-chip 4.0 5.5 CSA8.00MTZ093 8.00 30 30 4.0 5.5 CST8.00MTW093 8.00 On-chip On-chip 4.0 5.5 CSA8.38MTZ 8.38 30 30 4.0 5.5 CST8.38MTW 8.38 On-chip On-chip 4.0 5.5 CSA8.38MTZ093 8.38 30 30 4.0 5.5 CST8.38MTW093 8.38 On-chip On-chip 4.0 5.5

CCR4.19MC3 4.19 On-chip On-chip 1.8 5.5 CCR5.0MC3 5.00 On-chip On-chip 1.8 5.5 CCR8.0MC5 8.00 On-chip On-chip 4.0 5.5 CCR8.38MC5 8.38 On-chip On-chip 4.0 5.5

A = –40 to +85°C)

(MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V)

Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.

Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Output current, IOH Per pin –1 mA high

Output current, IOL Per pin for P00 to P03, P20 to P25, P34 to P36, 10 mA low P40 to P47, P64 to P67, P70 to P75

Input voltage, VIH1 high P40 to P47, P50 to P57,

VIH2

VIH3 P30 to P33 VDD = 2.7 to 5.5 V 0.7VDD 5.5 V

VIH4 X1, X2 VDD = 2.7 to 5.5 V

VIH5 XT1, XT2 VDD = 4.0 to 5.5 V 0.8VDD VDD V

Input voltage, VIL1 P10 to P17, P21, P24, P35, VDD = 2.7 to 5.5 V 0 0.3VDD V low

VIL2

VIL3 P30 to P33 4.0 V ≤ VDD ≤ 5.5 V 0 0.3VDD V

VIL4 X1, X2 VDD = 2.7 to 5.5 V 0 0.4 V

VIL5 XT1, XT2 VDD = 4.0 to 5.5 V 0 0.2V DD V

Output voltage, VOH1 VDD = 4.0 to 5.5 V, IOH = –1 mA high

Output voltage, VOL1 P30 to P33 VDD = 4.0 to 5.5 V, 2.0 V low

VOL2 IOL = 400 µA 0.5 V

All pins –15 mA

Per pin for P30 to P33, P50 to P57 15 mA Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 Total for P20 to P25 10 mA Total for P30 to P36 70 mA Total for P50 to P57 70 mA P10 to P17, P21, P24, P35,

P64 to P67, P74, P75 P00 to P03, P20, P22, P23, P25,

P34, P36, P70 to P73, RESET

(N-ch open-drain)

P40 to P47, P50 to P57, P64 to P67,

P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET

IOH = –100 µA

P50 to P57 P00 to P03, P20 to P25, P34 to P36,

P40 to P47, P64 to P67, P70 to P75

P74, P75

VDD = 2.7 to 5.5 V 0.7VDD VDD V

0.8VDD VDD V

VDD = 2.7 to 5.5 V 0.8VDD VDD V

0.85VDD VDD V

0.8VDD 5.5 V VDD – 0.5 VDD – 0.2

0.9VDD VDD V

VDD = 2.7 to 5.5 V 0 0.2VDD V

0 0.15VDD V

2.7 V ≤ VDD < 4.0 V 0 0.2VDD V

1.8 V ≤ VDD < 2.7 V 0 0.1VDD V

0 0.2 V

0 0.1VDD V VDD – 1.0 VDD – 0.5

IOL = 15 mA VDD = 4.0 to 5.5 V, 0.4 V

IOL = 1.6 mA

0.4 2.0 V

20 mA

VDD V VDD V

0.2VDD V

VDD V VDD V

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Input leakage ILIH1 VIN = VDD current, high

ILIH2 X1, X2, XT1, XT2 20 ILIH3 VIN = 5.5 V P30 to P33

Input leakage ILIL1 VIN = 0 V current, low

ILIL2 X1, X2, XT1, XT2 –20 ILIL3 P30 to P33

Output leakage ILOH VOUT = VDD 3 current, high

Output leakage ILOL VOUT = 0 V –3 current, low

Mask option pull-up resistance

Software pull- R2 VIN = 0 V, 15 30 90 kΩ up resistance P00 to P03, P20 to P25, P34 to P36, P40 to P47,

R1 VIN = 0 V, 15 30 90 kΩ

P30, P31

P50 to P57, P64 to P67, P70 to P75

P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET

Note

P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET

Note

–3

Note When pull-up resistors are not connected to P30, P31 (specified by the mask option).

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Power supply IDD1 8.38-MHz

Note 1

current

crystal oscillation operating mode

5.00-MHz crystal oscillation operating mode

IDD2 8.38-MHz

crystal oscillation HALT mode

5.00-MHz crystal oscillation HALT mode

IDD3 32.768-kHz crystal oscillation VDD = 5.0 V ±10% 40 80

operating mode

IDD4 32.768-kHz crystal oscillation VDD = 5.0 V ±10% 30 60

HALT mode

IDD5 XT1 = 0V STOP mode VDD = 5.0 V ±10% 0.1 30

When feedback resistor is not used

VDD = 5.0V±10%

VDD = 3.0V±10%

VDD = 2.0V±10%

VDD = 5.0V±10%

VDD = 3.0V±10%

VDD = 2.0V±10%

Note 4

Note 2

When A/D converter is 5.5 11 mA stopped

When A/D converter is 6.5 13 mA operating

Note 2

When A/D converter is 2 4 mA stopped

When A/D converter is 3 6 mA operating

Note 3

When A/D converter is 0.4 1.5 mA stopped

When A/D converter is 1.4 4.2 mA operating

Note 2

When peripheral functions

1.1 2.2 mA

are stopped When peripheral functions

are operating

Note 2

When peripheral functions

0.35 0.7 mA

are stopped When peripheral functions

are operating

Note 3

When peripheral functions 0.15 0.4 mA are stopped

When peripheral functions are operating

VDD = 3.0 V ±10% 20 40 VDD = 2.0 V ±10% 10 20

VDD = 3.0 V ±10% 6 18 VDD = 2.0 V ±10% 2 10

VDD = 3.0 V ±10% 0.05 10 VDD = 2.0 V ±10% 0.05 10

4.7 mA

1.7 mA

1.1 mA

Notes 1. Total current through the internal power supply (VDD0, VDD1), including the peripheral operation current

(except the current through pull-up resistors of ports and the AVREF pin).

2. When the processor clock control register (PCC) is set to 00H.

3. When PCC is set to 02H.

4. When main system clock operation is stopped.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

AC Characteristics

(1) Basic Operation

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Cycle time TCY Operating with 4.0 V ≤ VDD ≤ 5.5 V 0.24 16 (Min. instruction main system clock execution time)

TI00, TI01 input tTIH0, tTIL0 4.0 V ≤ VDD ≤ 5.5 V high-/low-level width

TI50, TI51 input fTI5 VDD = 2.7 to 5.5 V 0 4 MHz frequency

TI50, TI51 input tTIH5, tTIL5 VDD = 2.7 to 5.5 V 100 ns high-/low-level width

Interrupt request tINTH, tINTL INTP0 to INTP3, VDD = 2.7 to 5.5 V 1 input high-/low P40 to P47

-level width RESET tRSL VDD = 2.7 to 5.5 V 10

low-level width

(TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

2.7 V ≤ VDD < 4.0 V 0.4 16

Operating with subsystem clock

2.7 V ≤ VDD < 4.0 V

1.6 16

Note 1

103.9 2/fsam + 0.1 2/fsam + 0.2 2/fsam + 0.5

0 275 kHz

1.8 ns

122 125

Note2

Notes 1. Value when an external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).

2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register

0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes f

sam = fX/8.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

TCY vs. VDD (main system clock operation)

16.0

10.0

[ s]

5.0

2.0

1.6

Cycle time T

1.0

0.4

0.24

0.1 0

Operation guaranteed range

1.0 2.0 3.0 4.0 5.0 6.0

1.8

2.7

Supply voltage V

[V]

5.5

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

(2) Read/Write Operation (TA = –40 to + 85°C, VDD = 4.0 to 5.5 V)

(1/3)

Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.3tCY ns Address setup time tADS 20 ns Address hold time tADH 6ns Data input time from address tADD1 (2 + 2n)tCY – 54 ns

tADD2 (3 + 2n)tCY – 60 ns Address output time from RD↓ t RDAD 0 100 ns Data input time from RD↓ tRDD1 (2 + 2n)tCY – 87 ns

tRDD2 (3 + 2n)tCY – 93 ns Read data hold time tRDH 0ns RD low-level width tRDL1 (1.5 + 2n)tCY – 33 ns

tRDL2 (2.5 + 2n)tCY – 33 ns

WAIT↓ input time from RD↓ tRDWT1 tCY – 43 ns

tRDWT2 tCY – 43 ns WAIT↓ input time from WR↓ tWRWT tCY – 25 ns WAIT low-level width tWTL (0.5 + n)tCY + 10 (2 + 2n)tCY ns Write data setup time tWDS 60 ns Write data hold time tWDH 6ns WR low-level width tWRL1 (1.5 + 2n)tCY – 15 ns RD↓ delay time from ASTB↓ tASTRD 6ns WR↓ delay time from ASTB↓ tASTWR 2tCY – 15 ns ASTB↑ delay time from tRDAST 0.8tCY – 15 1.2tCY ns

RD↑ at external fetch Address hold time from tRDADH 0.8tCY – 15 1.2tCY + 30 ns

RD↑ at external fetch Write data output time from RD↑ tRDWD 40 ns Write data output time from WR↓ tWRWD 10 60 ns Address hold time from WR↑ tWRADH 0.8tCY – 15 1.2tCY + 30 ns RD↑ delay time from WAIT↑ tWTRD 0.8tCY 2.5tCY + 25 ns WR↑ delay time from WAIT↑ tWTWR 0.8tCY 2.5tCY + 25 ns

Remarks 1. tCY = TCY/4

2. n indicates the number of waits.

L = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and

3.C ASTB pins.)

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

(2) Read/Write Operation (TA = –40 to + 85°C, VDD = 2.7 to 4.0 V)

(2/3)

Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.3tCY ns Address setup time tADS 30 ns Address hold time tADH 10 ns Data input time from address tADD1 (2 + 2n)tCY – 108 ns

tADD2 (3 + 2n)tCY – 120 ns Address output time from RD↓ t RDAD 0 200 ns Data input time from RD↓ tRDD1 (2 + 2n)tCY – 148 ns

tRDD2 (3 + 2n)tCY – 162 ns Read data hold time tRDH 0ns RD low-level width tRDL1 (1.5 + 2n)tCY – 40 ns

tRDL2 (2.5 + 2n)tCY – 40 ns WAIT↓ input time from RD↓ tRDWT1 tCY – 75 ns

tRDWT2 tCY – 60 ns WAIT↓ input time from WR↓ tWRWT tCY – 50 ns WAIT low-level width tWTL (0.5 + 2n)tCY + 10 (2 + 2n)tCY ns Write data setup time tWDS 60 ns Write data hold time tWDH 10 ns WR low-level width tWRL1 (1.5 + 2n)tCY – 30 ns RD↓ delay time from ASTB↓ tASTRD 10 ns WR↓ delay time from ASTB↓ tASTWR 2tCY – 30 ns ASTB↑ delay time from tRDAST 0.8tCY – 30 1.2tCY ns

RD↑ at external fetch Address hold time from tRDADH 0.8tCY – 30 1.2tCY + 60 ns

RD↑ at external fetch Write data output time from RD↑ tRDWD 40 ns Write data output time from WR↓ tWRWD 20 120 ns Address hold time from WR↑ tWRADH 0.8tCY – 30 1.2tCY + 60 ns RD↑ delay time from WAIT↑ tWTRD 0.5tCY 2.5tCY + 50 ns WR↑ delay time from WAIT↑ tWTWR 0.5tCY 2.5tCY + 50 ns

Remarks 1. tCY = TCY/4

2. n indicates the number of waits.

3. CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,

and ASTB pins.)

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

(2) Read/Write Operation (TA = –40 to + 85°C, VDD = 1.8 to 2.7 V)

(3/3)

Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.3tCY ns Address setup time tADS 120 ns Address hold time tADH 20 ns Data input time from address tADD1 (2 + 2n)tCY – 233 ns

tADD2 (3 + 2n)tCY – 240 ns Address output time from RD↓ t RDAD 0 400 ns Data input time from RD↓ tRDD1 (2 + 2n)tCY – 325 ns

tRDD2 (3 + 2n)tCY – 332 ns Read data hold time tRDH 0ns RD low-level width tRDL1 (1.5 + 2n)tCY – 92 ns

tRDL2 (2.5 + 2n)tCY – 92 ns WAIT↓ input time from RD↓ tRDWT1 tCY – 350 ns

tRDWT2 tCY – 132 ns WAIT↓ input time from WR↓ tWRWT tCY – 100 ns WAIT low-level width tWTL (0.5 + 2n)tCY + 10 (2 + 2n)tCY ns Write data setup time tWDS 60 ns Write data hold time tWDH 20 ns WR low-level width tWRL1 (1.5 + 2n)tCY – 60 ns RD↓ delay time from ASTB↓ tASTRD 20 ns WR↓ delay time from ASTB↓ tASTWR 2tCY – 60 ns ASTB↑ delay time from tRDAST 0.8tCY – 60 1.2tCY ns

RD↑ at external fetch Address hold time from tRDADH 0.8tCY – 60 1.2tCY + 120 ns

RD↑ at external fetch Write data output time from RD↑ tRDWD 40 ns Write data output time from WR↓ tWRWD 40 240 ns Address hold time from WR↑ tWRADH 0.8tCY – 60 1.2tCY + 120 ns RD↑ delay time from WAIT↑ tWTRD 0.5tCY 2.5tCY + 100 ns WR↑ delay time from WAIT↑ tWTWR 0.5tCY 2.5tCY + 100 ns

Remarks 1. tCY = TCY/4

2. n indicates the number of waits.

L = 100pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and

3. C ASTB pins.)

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

(3) Serial Interface (TA = –40 to + 85°C, VDD = 1.8 to 5.5 V)

(a) 3-wire serial I/O mode (SCK30 ... Internal clock output)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

SCK30 cycle time tKCY1 4.0 V ≤ VDD ≤ 5.5 V 954 ns

2.7 V ≤ VDD < 4.0 V 1600 ns 3200 ns

SCK30 high-/low-level tKH1, tKL1 VDD = 4.0 to 5.5 V tKCY1/2 – 50 ns width

SI30 setup time tSIK1 4.0 V ≤ VDD ≤ 5.5V 100 ns (to SCK30↑)

SI30 hold time tKSI1 400 ns (from SCK30↑)

SO30 output tKSO1 C = 100 pF delay time from SCK30↓

2.7 V ≤ VDD < 4.0V 150 ns

Note

tKCY1/2 – 100 ns

300 ns

Note C is the load capacitance of the SCK30 and SO30 output lines.

(b) 3-wire serial I/O mode (SCK30 ... External clock input)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

SCK30 cycle time tKCY2 4.0 V ≤ VDD ≤ 5.5 V 800 ns

2.7 V ≤ VDD < 4.0 V 1600 ns

3200 ns

SCK30 high-/low-level tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V 400 ns width

SI30 setup time tSIK2 100 ns (to SCK30↑)

SI30 hold time tKSI2 400 ns (from SCK30↑)

SO30 output tKSO2 C = 100 pF delay time from SCK30↓

2.7 V ≤ VDD < 4.0 V 800 ns

1600 ns

Note

300 ns

Note C is the load capacitance of the SO30 output line.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Transfer rate 4.0 V ≤ VDD ≤ 5.5 V 131031 bps

2.7 V ≤ VDD < 4.0 V 78125 bps 39063 bps

(d) UART mode (External clock input)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

ASCK0 cycle time tKCY3 4.0 V ≤ VDD ≤ 5.5 V 800 ns

2.7 V ≤ VDD < 4.0 V 1600 ns

3200 ns

ASCK0 high-/low-level width tKH3, 4.0 V ≤ VDD ≤ 5.5 V 400 ns

tKL3

Transfer rate 4.0 V ≤ VDD ≤ 5.5 V 39063 bps

2.7 V ≤ VDD < 4.0 V 800 ns

1600 ns

2.7 V ≤ VDD < 4.0 V 19531 bps

9766 bps

(e) UART mode (Infrared ray data transfer mode)

Parameter Symbol Test Conditions MIN. MAX. Unit Transfer rate VDD = 4.0 to 5.5 V 131031 bps Bit rate allowable error VDD = 4.0 to 5.5 V ±0.87 % Output pulse width VDD = 4.0 to 5.5 V 1.2 Input pulse width VDD = 4.0 to 5.5 V 4/fX

0.24/fbr

Note

Note fbr: Specified baud rate

Data Sheet U14045EJ1V0DS00

(f) I2C bus Mode

PD780031AY, 780032AY, 780033AY, 780034AY

Parameter Symbol

SCL0 clock frequency fCLK 0 100 0 400 kHz Bus-free time tBUF 4.7 — 1.3 —

(between stop and start condition) Hold time SCL0 clock low-level width tLOW 4.7 — 1.3 — SCL0 clock high-level width tHIGH 4.0 — 0.6 — Start/restart condition setup time tSU:STA 4.7 — 0.6 — Data hold time CBUS compatible master tHD:DAT 5.0 — — —

Data setup time tSU:DAT 250 — 100 SDA0 and SCL0 signal rise time tR — 1000 20 + 0.1Cb SDA0 and SCL0 signal fall time tF — 300 20 + 0.1Cb Stop condition setup time tSU:STO 4.0 — 0.6 — Spike pulse width controlled by input filter tSP —— 050ns Capacitive load per bus line Cb — 400 — 400 pF

Note 1

I2C bus 0

tHD:STA 4.0 — 0.6 —

Standard Mode High-Speed Mode

MIN. MAX. MIN. MAX.

Note 2

—0

Note 2

Note 4

Note 5

Note 3

0.9 —ns

300 ns 300 ns

Unit

µ µ µ µ µ µ

s s s s s s

Notes 1. In the start condition, the first clock pulse is generated after this hold time.

2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide

at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal).

3. If the device does not extend the SCL0 signal low hold time (t

LOW), only maximum data hold time tHD:DAT

needs to be fulfilled.

4. The high-speed mode I

C bus is available in a standard mode I2C bus system. At this time, the conditions

described below must be satisfied.

• If the device does not extend the SCL0 signal low state hold time

SU:DAT ≥ 250 ns

• If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns by standard mode I2C bus specification).

5. Cb: Total capacitance per bus line (unit: pF)

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

AC Timing Test Points (Excluding X1, XT1 Inputs)

0.8V

0.2V

DD DD

Test points

Clock Timing

X1 Input

1/f

0.8V

0.2V

IH4

(MIN.)

IL4

(MAX.)

TI Timing

XT1 Input

TI00, TI01

1/f

XTL

TIL0

TIL5

1/f

XTH

IH5

(MIN.)

IL5

(MAX.)

TIH0

TI5

TIH5

TI50, TI51

Data Sheet U14045EJ1V0DS00

Read/Write Operation

External fetch (no wait):

PD780031AY, 780032AY, 780033AY, 780034AY

A8 to A15

AD0 to AD7

ASTB

External fetch (wait insertion):

A8 to A15

Lower-8-bit address

ADS

ADH

ASTH

ASTRD

Higher 8-bit address

ADD1

Hi-Z

RDAD

RDD1

Higher 8-bit address

Instruction code

RDL1

RDH

RDADH

RDAST

AD0 to AD7

ASTB

WAIT

Lower 8-bit address

ADS

ADH

ASTH

ASTRD

RDWT1

RDAD

ADD1

Hi-Z

RDD1

WTL

RDL1

Instruction code

WTRD

RDH

RDADH

RDAST

Data Sheet U14045EJ1V0DS00

External data access (no wait):

PD780031AY, 780032AY, 780033AY, 780034AY

A8 to A15

ADD2

AD0 to AD7

Lower 8-bit address

ADS

ADH

ASTH

ASTB

ASTRD

External data access (wait insertion):

Hi-Z

RDAD

RDD2

Higher 8-bit address

Read data

RDL2

ASTWR

RDH

RDWD

WRWD

Write data

WDS

WRL1

WDH

Hi-Z

WRADH

A8 to A15

AD0 to AD7

ASTB

WAIT

Lower 8-bit

address

ADH

ADS

ASTH

RDWT2

RDAD

ASTRD

ADD2

Hi-Z

RDD2

Higher 8-bit address

WDH

WRADH

Hi-Z

Read data

RDH

RDL2

ASTWR

WTL

WTRD

RDWD

WRWD

WRWT

Write data

WDS

WRL1

WTL

WTWR

Data Sheet U14045EJ1V0DS00

Serial Transfer Timing

3-wire serial I/O mode:

SCK30

PD780031AY, 780032AY, 780033AY, 780034AY

KCYm

KLm

SIKm

KSIm

KHm

SI30

SO30

m = 1, 2

UART mode (external clock input):

ASCK0

KSOm

Input data

Output data

KCY3

KL3

KH3

Data Sheet U14045EJ1V0DS00

I2C Bus Mode:

SCL0

SDA0

Stop condition

BUF

HD:STA

Start condition

LOW

HD:DAT

PD780031AY, 780032AY, 780033AY, 780034AY

HIGH

SU:DAT

SU:STA

Restart condition

HD:STA

Stop condition

SU:STO

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF = 1.8 to 5.5 V, AVSS = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 10 10 10 bit Overall error

Conversion time tCONV 4.0 V ≤ AVREF ≤ 5.5 V 14 96

Zero-scale offset

Full-scale offset

Integral linearity error

Differential linearity error

Analog input voltage VIAN 0AVREF V Reference voltage AVREF 1.8 AVDD V Resistance between AVREF and AVSS RREF

Notes 1, 2

Note 1

4.0 V ≤ AVREF ≤ 5.5 V ±0.2 ±0.4 %FSR

2.7 V ≤ AVREF < 4.0 V ±0.3 ±0.6 %FSR

1.8 V ≤ AVREF < 2.7 V ±0.6 ±1.2 %FSR

2.7 V ≤ AVREF < 4.0 V 19 96

1.8 V ≤ AVREF < 2.7 V 28 96

4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR

2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR

1.8 V ≤ AVREF < 2.7 V ±1.2 %FSR

4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR

2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR

1.8 V ≤ AVREF < 2.7 V ±1.2 %FSR

4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB

2.7 V ≤ AVREF < 4.0 V ±4.5 LSB

1.8 V ≤ AVREF < 2.7 V ±8.5 LSB

4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB

2.7 V ≤ AVREF < 4.0 V ±2.0 LSB

1.8 V ≤ AVREF < 2.7 V ±3.5 LSB

When A/D conversion is not performed

20 40 kΩ

Notes 1. Excludes quantization error (±1/2 LSB).

2. Shown as a percentage of the full scale value.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Data retention power VDDDR 1.6 5.5 V supply voltage

Data retention IDDDR VDDDR = 1.6 V 0.1 30 power supply Subsystem clock stop (XT1 = VDD) and current feed-back resistor disconnected

Release signal set time Oscillation stabilization tWAIT Release by RESET 217/fx ms

time

tSREL 0

Release by interrupt request Note ms

Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation

stabilization time select register (OSTS).

Data Retention Timing (STOP mode release by RESET)

Internal reset operation

HALT mode

STOP mode

Operating mode

RESET

STOP instruction execution

Data retention mode

DDDR

SREL

WAIT

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal)

HALT mode

STOP mode

Data retention mode

Operating mode

VDD

STOP Instruction execution

Standby release signal (interrupt request)

Interrupt Request Input Timing

INTP0 to INTP2

INTP3

VDDDR

INTL

tSREL

tWAIT

INTH

RESET Input Timing

RESET

RSL

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

13. PACKAGE DRAWINGS

64 PIN PLASTIC SHRINK DIP (750 mil)

64 33

321

NOTES

1. Controlling dimension millimeter.

2. Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition.

3. Item "K" to center of leads when formed parallel.

ITEM MILLIMETERS INCHES

A 58.0 2.283 B

C D

F G H

I 4.05 0.159

J K

M N

+0.68 –0.20

1.78 MAX.

1.778 (T.P.)

0.50±0.10

0.9 MIN.

3.2±0.3

0.51 MIN. +0.26

–0.20

5.08 MAX.

19.05 (T.P.)

17.0±0.2 +0.10

0.25

–0.05

0.17

0 to 15°

+0.028 –0.008

0.070 MAX.

0.070 (T.P.) +0.004

0.020

–0.005

0.035 MIN.

0.126±0.012

0.020 MIN. +0.011

–0.008

0.200 MAX.

0.750 (T.P.) +0.009

0.669

–0.008 +0.004

0.010

–0.003

0.007

0 to 15°

P64C-70-750A,C-3

Remark The external dimensions and materials of the ES version are the same as those of the mass-produced

version.

Data Sheet U14045EJ1V0DS00

64 PIN PLASTIC QFP ( 14)

PD780031AY, 780032AY, 780033AY, 780034AY

NOTE

1. Controlling dimension millimeter.

2. Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.

detail of lead end S

ITEM MILLIMETERS INCHES

A 17.6±0.4 0.693±0.016 B 14.0±0.2 0.551

C 14.0±0.2 0.551 D 17.6±0.4 0.693±0.016

1.0

G 1.0

0.15

5°±5°

+0.08 –0.07

H 0.37 0.015

I J 0.8 (T.P.)

K 1.8±0.2 0.071±0.008 L 0.8±0.2 0.031

M 0.17 0.007

N 0.10 0.004 P 2.55±0.1 0.100±0.004 Q 0.1±0.1 0.004±0.004 R S 2.85 MAX.

+0.009 –0.008

0.039

0.039 +0.003

–0.004

0.006

0.031 (T.P.)

+0.009 –0.008

+0.003 –0.004

5°±5°

0.113 MAX.

P64GC-80-AB8-4

Remark The external dimensions and materials of the ES version are the same as those of the mass-produced

version.

Data Sheet U14045EJ1V0DS00

64 PIN PLASTIC LQFP (12x12)

PD780031AY, 780032AY, 780033AY, 780034AY

NOTES

1. Controlling dimension millimeter.

2. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.

detail of lead end

ITEM MILLIMETERS INCHES

A 14.8±0.4 0.583±0.016 B 12.0±0.2 0.472

C 12.0±0.2 0.472

14.8±0.4D 0.583±0.016

1.125

H 0.32±0.08 0.013

0.13I 0.005

0.65 (T.P.)J 0.026

K 1.4±0.2 0.055±0.008 L 0.6±0.2 0.024

M 0.17 0.007

P 1.4±0.1 0.055

S 1.7 MAX. 0.067 MAX.

+0.08

−0.07

0.10N 0.004

0.125±0.075Q 0.005±0.003 5°±5°R5°±5°

+0.009

−0.008 +0.009

−0.008

0.044

+0.003

−0.004

+0.008

−0.009 +0.003

−0.004

+0.004

−0.005

P64GK-65-8A8-2

Remark The external dimensions and materials of the ES version are the same as those of the mass-produced

version.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

14. RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales represen-

tative.

Table 14-1. Surface Mounting Type Soldering Conditions

PD780031AYGC-×××-AB8: 64-pin plastic QFP (14 × 14 mm)

(1)

PD780032AYGC-×××-AB8: 64-pin plastic QFP (14 × 14 mm)

PD780033AYGC-×××-AB8: 64-pin plastic QFP (14 × 14 mm)

PD780034AYGC-×××-AB8: 64-pin plastic QFP (14 × 14 mm)

Soldering Method Soldering Conditions

Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-00-3

(at 210°C or higher), Count: three times or less

VPS Package peak temperature: 215°C, Time: 40 seconds max. VP15-00-3

(at 200°C or higher), Count: three times or less

Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., WS60-00-1

Count: once, Preheating temperature: 120°C max. (package surface temperature)

Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) ––

Caution Do not use different soldering methods together (except for partial heating).

Recommended

Condition Symbol

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

(2)µPD780031AYGK-×××-8A8: 64-pin plastic LQFP (12 × 12 mm)

PD780032AYGK-×××-8A8: 64-pin plastic LQFP (12 × 12 mm)

PD780033AYGK-×××-8A8: 64-pin plastic LQFP (12 × 12 mm)

PD780034AYGK-×××-8A8: 64-pin plastic LQFP (12 × 12 mm)

Soldering Method Soldering Conditions

Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-107-2

(at 210°C or higher), Count: two times or less, prebake at 125°C for 10 hours)

VPS Package peak temperature: 215°C, Time: 40 seconds max. VP15-107-2

(at 200°C or higher), Count: two times or less, prebake at 125°C for 10 hours)

Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., WS60-107-1

Count: once, Preheating temperature: 120°C max. (package surface temperature), Exposure limit: 7 days at 125

°C for 10 hours

Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) ––

Exposure limit: 7 days

)

Note

(after that,

Note

(after that,

Note

(after that, prebake

Recommended

Condition Symbol

Note After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage

period.

Caution Do not use different soldering methods together (except for partial heating).

Table 14-2. Insertion Type Soldering Conditions

PD780031AYCW-×××: 64-pin plastic shrink DIP (750mils)

PD780032AYCW-×××: 64-pin plastic shrink DIP (750mils)

PD780033AYCW-×××: 64-pin plastic shrink DIP (750mils)

PD780034AYCW-×××: 64-pin plastic shrink DIP (750mils)

Soldering Method Soldering Conditions

Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max. (only for pins)

Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with

the package.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD780034AY Subseries. Also refer to (5) Cautions on Using Development Tools.

(1) Language Processing Software

RA78K/0 Assembler package common to 78K/0 Series CC78K/0 C compiler package common to 78K/0 Series DF780034 Device file common to µPD780034A Subseries CC78K/0-L C compiler library source file common to 78K/0 Series

(2) Flash Memory Writing Tools

Flashpro II (FL-PR2) Flash programmer dedicated to microcontrollers with on-chip flash memory Flashpro III (FL-PR3, PG-FP3)

FA-64CW Adapter for flash memory writing FA-64GC FA-64GK

(3) Debugging Tools

• When using in-circuit emulator IE-78K0-NS

IE-78K0-NS In-circuit emulator common to 78K/0 Series IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-78K0-NS-PA IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C Interface adapter when using IBM PC/ATTM or compatible as host machine (ISA bus supported) IE-70000-PCI-IF Adapter required when using PC in which PCI bus is embedded as host machine IE-780034-NS-EM1 Emulation board to emulate µPD780034AY Subseries NP-64CW Emulation probe for 64-pin plastic shrink DIP (CW type) NP-64GC Emulation probe for 64-pin plastic QFP (GC-AB8 type)

NP-64GC-TQ NP-64GK Emulation probe for 64-pin plastic LQFP (GK-8A8 type) TGK-064SBW Conversion adapter to connect NP-64GK and target system board on which a 64-pin plastic LQFP

EV-9200GC-64 Socket to be mounted on target system board made for 64-pin plastic QFP (GC-AB8 type) ID78K0-NS Integrated debugger for IE-78K0-NS SM78K0 System simulator common to 78K/0 Series DF780034 Device file common to µPD780034A Subseries

Note

Performance board to enhance and expand the functions of IE-78K0-NS Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported)

(GK-8A8 type) can be mounted.

Note Under development

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

• When using in-circuit emulator IE-78001-R-A

IE-78001-R-A In-circuit emulator common to 78K/0 Series IE-70000-98-IF-C IE-70000-PC-IF-C Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported) IE-70000-PCI-IF Adapter required when using PC in which PCI bus is embedded as host machine IE-78000-R-SV3 Interface adapter and cable when using EWS as host machine IE-780034-NS-EM1 Emulation board to emulate µPD780034AY Subseries IE-78K0-R-EX1 Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A EP-78240CW-R Emulation probe for 64-pin plastic shrink DIP (CW type) EP-78240GC-R Emulation probe for 64-pin plastic QFP (GC-AB8 type) EP-78012GK-R Emulation probe for 64-pin plastic LQFP (GK-8A8 type) TGK-064SBW

EV-9200GC-64 ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator common to 78K/0 Series DF780034 Device file common to µPD780034A Subseries

Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)

Conversion adapter to connect LQFP (GK-8A8 type) can be mounted.

Socket to be mounted on target system board made for 64-pin plastic QFP (GC-AB8 type)

EP-78012GK-R a

nd target system board on which a 64-pin plastic

(4) Real-time OS

RX78K/0 Real-time OS for 78K/0 Series MX78K0 OS for 78K/0 Series

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

(5) Cautions on Using Development Tools

• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034.

• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and the DF780034.

• FL-PR2, FL-PR3, FA-64CW, FA-64GC, FA-64GK, NP-64CW, NP-64GC, NP-64GC-TQ, and NP-64GK are products made by Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813).

Contact an NEC distributor regarding the purchase of these products.

• The TGK-064SBW is a product made by TOKYO ELETECH CORPORATION. Refer to: Daimaru Kogyo, Ltd.

Tokyo Electronic Division (+81-3-3820-7112) Osaka Electronic Division (+81-6-6244-6672)

• For third-party development tools, see the 78K/0 Series Selection Guide (U11126E).

• The host machines and OSs supporting each software are as follows.

Host Machine PC EWS

[OS] PC-9800 series [WindowsTM] HP9000 series 700TM [HP-UXTM]

IBM PC/AT and compatibles SPARCstationTM [SunOSTM, SolarisTM]

Software [Japanese/English Windows] NEWSTM (RISC) [NEWS-OSTM]

Note

RA78K/0 CC78K/0 ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0

√

Note

√

√ √√ √

Note

√

Note

√

√ √

–

√ √

Note DOS-based software

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

APPENDIX B. RELATED DOCUMENTS

Documents Related to Devices

Document Name Document No. Document No.

(English) (Japanese)

PD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual U14046E U14046J

PD780031AY, 780032AY, 780033AY, 780034AY Data Sheet This document U14045J

PD78F0034AY Data Sheet U14041E U14041J 78K/0 Series User’s Manual Instructions U12326E U12326J 78K/0 Series Instruction Table — U10903J 78K/0 Series Instruction Set — U10904J

Documents Related to Development Tools (User’s Manuals)

Document Name Document No. Document No.

(English) (Japanese)

RA78K0 Assembler Package Operation U11802E U11802J

Assembly Language U11801E U11801J

Structured Assembly Language U11789E U11789J RA78K Series Structured Assembler Preprocessor EEU-1402 U12323J CC78K0 C Compiler Operation U11517E U11517J

Language U11518E U11518J CC78K0 C Compiler Application Note Programming Know-how U13034E U13034J IE-78K0-NS To be prepared To be prepared IE-78001-R-A To be prepared To be prepared IE-780034-NS-EM1 To be prepared To be prepared EP-78240 U10332E EEU-986 EP-78012GK-R EEU-1538 EEU-5012 SM78K0 System Simulator Windows based Reference U10181E U10181J SM78K Series System Simulator External Part User Open U10092E U10092J

Interface Specifications ID78K0-NS Integrated Debugger Windows based ID78K0 Integrated Debugger EWS based Reference — U11151J ID78K0 Integrated Debugger PC based Reference U11539E U11539J ID78K0 Integrated Debugger Windows based Guide U11649E U11649J

Reference U12900E U12900J

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

Data Sheet U14045EJ1V0DS00

PD780031AY, 780032AY, 780033AY, 780034AY

Documents Related to Embedded Software (User’s Manuals)

Document Name Document No. Document No.

(English) (Japanese)

78K/0 Series Real-time OS Basics U11537E U11537J

Installation U11536E U11536J

78K/0 Series OS MX78K0 Basics U12257E U12257J

NEC PD780031AY, PD780032AY, PD780033AY, PD780034AY Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual