NEC PD75P238 Technical data

UPD75P238GJ-5BG	DATA SHEET

MOS INTEGRATED CIRCUIT

μPD75P238

4-BIT SINGLE CHIP MICROCOMPUTER

DESCRIPTION

The μPD75P238 is a version of the μPD75238 in which the on-chip mask ROM is replaced by one-time PROM or EPROM.

The one-time PROM version can be written to once only, and is useful for short-run and multiple deviceproduction of sets and early start-up. Also, the EPROM version allows programs to be written and rewritten, and is thus ideal for system evaluation.

Functions are described in detail in the following User's Manual, which should be read when carrying out design

work.

μPD75238 User's Manual : IEU-731

The μPD75P238 EPROM product does not provide a level of reliability suitable for use as a volume production product for users' devices. The EPROM product should be used solely for function evaluation in experiments of preproduction.

FEATURES

o μPD75238 pin compatible		o High-voltage display outputs
o On-chip PROM: 32640 × 8		. S0 to S8 & T0 to T9	: Internal pull-down resistors
o On-chip RAM: 1024 × 4		. S9, S16 to S23 & T10 to T15: Open-drain
o Drive capability in same supply voltage range as mask version μPD75238 (2.7 to 6.0 V)
o Ports	4 & 5: No pull-up resistor
o Port 7: No pull-down resistor
Note	No internal pull-up and pull-down resistor function by mask option.
USE
VCR,	Audio-visual, ECR, Microwave oven

ORDERING INFORMATION

Ordering Code	Package	On-Chip ROM	Quality Grade
μPD75P238GJ-5BG	94-pin plastic QFP(■20 mm)	One-time PROM	Standard
μPD75P238KF	94-pin ceramic WQFN	EPROM	Standard

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

This manual describes common parts of One-time PROM and EPROM products as PROM.

	The information in this document is subject to change without notice.
Document No. IC-2596A	The mark shows major revised points.
(O.D. No. IC-8014A)
Date Published February 1994 P
Printed in Japan	© NEC Corporation 1992

μPD75P238

PIN CONFIGURATION (TOP VIEW)

			AN1	AN2	AN3 AN4/P90 AN5/P91 AN6/P92	AN7/P93 AVSS RESET P00/INT4 P01/SCK0 P02/SO0/SB0	P03/SI0/SB1 P10 /INT0 P11/INT1 P12/INT2	P13/TI0 P20/PTO0 P21	P22/PCL	P23/BUZ	P30/MD0	P31/MD1
			94 93		92919089	8887 868584838281807978777675747372						71	P32/MD2
	AN0	1
												70	P33/MD3
	AVREF	2
												69	P40
	AVDD	3
												68	P41
	VDD	4
												67	P42
	VPP	5										66	P43
	X2	6
												65	VSS
	X1	7										64	P50
	IC	8				PD75P238KFμ	-PD75P238GJμ					63	P51
	XT2	9										57	P63
	S18/P102	14
	XT1	10										62	P52
												61	P53
	VSS	11										60	P60
	S16/P100	12										59	P61
	S17/P101	13										58	P62
	S19/P103	15					5BG					56	P70
	S20/P110	16										55	P71
	S21/P111	17										54	P72
	S22/P112	18										53	P73
	S23/P113	19
												52	P80/PPO
	S0/P120	20										51	P81/SCK1
	S1/P121	21										50	P82/SO1
	S2/P122	22										49	P83/SI1
	S3/P123	23										48	VDD
		24 25262728 293031323334353637383940414243							44 45 4647
		S4/P130	S5/P131	S6/P132	S7/P133 S8/P140 S9/P141 VDD	VLOAD T15/S10/P142 T14/S11/P143 PH0/T13/S12/P150 PH1/T12/S13/P151 PH2/T11/S14/P152	PH3/T10/S15/P153 T9 T8 T7	T6 T5 T4	T3	T2	T1	T0
Note	Ensure that power is supplied to the VDD and VSS pins (pins 4, 11, 30, 48, and 65).
Remarks IC (Internally Connected) pins should be connected directly to VSS.

2

μPD75P238

PIN NAME

P00 to P03	:	Port0	SCK0, SCK1		: Serial Clock I/O 0, 1
P10 to P13	:	Port1	SO0, SO1		: Serial Data Output 0, 1
P20 to P23	:	Port2	SI0, SI1		: Serial Data Input 0, 1
P30 to P33	:	Port3	SB0, SB1		: Serial Bus I/O 0, 1
P40 to P43	:	Port4	INT0, INT1, INT4		: External Vectored Interrupt Input 0, 1, 4
P50 to P53	:	Port5	INT2		: External Test Input 2
P60 to P63	:	Port6	PPO		: Programmable Pulse Output
P70 to P73	:	Port7	TI0		: Timer Input 0
P80 to P83	:	Port8	PTO0		: Programmable Timer Output 0
P90 to P93	:	Port9	BUZ		: Buzzer Clock
P100 to P103	:	Port10	PCL		: Programmable Clock Output
P110 to P113	:	Port11	AN0 to AN7		: Analog Input 0 to 7
P120 to P123	:	Port12	AVREF		: Analog Reference Voltage
P130 to P133	:	Port13	AVDD		: Analog VDD
P140 to P143	:	Port14	AVSS		: Analog VSS
P150 to P153	:	Port15	X1, X2		: Main System Clock Oscillation 1, 2
PH0 to PH3	:	PortH	XT1, XT2		: Subsystem Clock Oscillation 1, 2
T0 to T15	:	Digit Output	RESET		: Reset
S0 to S23	:	Segment Output	VPP		: Programming Power Supply
VDD	:	Positive Power Supply	MD0 to MD3		: Mode Selection 0 to 3
VSS	:	Ground	IC		: Internally Connected
VLOAD	:	Power Supply for FIP Driver

3

4

		BASIC
		INTERVAL
		TIMER
		TIO
		INTBT
	TI0/P13	TIMER/EVENT
		COUNTER
	PTO0/P20
		#0
		INTT0
	BUZ/P23	WATCH
		TIMER
		INTW

TIMER/

PPO/P80 PULSE

GENELATOR

INTTPG

SI0/SB1/P03

SO0/SB0/P02

SERIAL

INTERFACE

SCK0/P01

INTCSI

SI1/P83 SERIAL

SO1/P82 INTERFACE

SCK1/P81

INT0/P10

INT1/P11 INTERRUPT

INT2/P12 CONTROL

INT4/P00

	TI0			EVENT
				COUNTER
AN0-AN3	8
AN4/P90-AN7/P93				A/D
AVDD
				CONVERTER
AVREF
AVSS
				BIT SEQ.
				BUFFER(16)

PORT 0	4	P00-P03
PORT 1	4	P10-P13

SP (8)

PROGRAM		CY
COUNTER (15)	ALU
		SBS (2)	PORT 2	4	P20-P23
		BANK	PORT 3	4	P30/MD0
					-P33/MD3
			PORT 4	4	P40-P43

						PORT 5	4	P50-P53
ROM					GENERAL REG.
						PORT 6	4	P60-P63
PROGRAM
MEMORY		DECODE
32640 × 8						PORT 7	4	P70-P73
			AND
		CONTROL			RAM
					DATA	PORT 8	4	P80-P83
					MEMORY
					1024 × 4		4
						PORT 9		P90-P93
							10		T0-T9
							4		T10/S15/PH3/P153-
									T13/S12/PH0/P150
	fX / 2N					FIP			T14/S11/ P143-
		CLOCK				CONTROLLER/ 2
CLOCK									T15/S10/P142
	CLOCK			STAND BY		DRIVER
		GENERATOR			CPU CLOCK
OUTPUT
	DIVIDER			CONTROL					S0/P120-S9/P141
CONTROL		SUB	MAIN		Φ		10
		XT1 XT2	X1 X2				8		S16/P100-S23/P113
PCL/P22									VLOAD
						PORT 10-15	24		P100-P153
					RESET VDD VSS	VPP

DIAGRAM BLOCK

PD75P238μ

μPD75P238

1. PIN FUNCTIONS

1.1 PORT PINS (1/2)

	Pin Name	Input/Output	Dual-Function				Function	8-Bit I/O	After Reset	Input/Output
				Pin						Circuit Type*1
	P00			INT4							B
						4-bit input port (PORT0).
	P01			SCK0		Internal pull-up resistor specification by		×		F	– A
		Input				software is possible for P01 to P03 as a 3-			Input
	P02		SO0/SB0			bit unit.				F	– B
	P03		SI0/SB1							M	– C
	P10			INT0			With noise elimination
							function
	P11			INT1		4-bit input port (PORT1).		×
		Input				Internal pull-up resistor specification by			Input	B	– C
	P12			INT2		software is possible as a 4-bit unit.
	P13			TI0
	P20			PTO0
	P21			—		4-bit input/output port (PORT2).		×
		Input/output				Internal pull-up resistor specification by			Input	E – B
	P22			PCL		software is possible as a 4-bit unit.
	P23			BUZ
						Programmable 4-bit input/output port (PORT3).
	P30 to P33 *2	Input/output	MD0 to MD3			Input/output settable bit-wise.		×	Input	E – C
						Internal pull-up resistor specification by
						software is possible as a 4-bit unit.
						N-ch open-drain 4-bit input/output port
	P40 to P43 *2	Input/output		—		(PORT4).			Input	M – A
						Data input/output pins for program memory
						write/verify (low-order 4 bits).
						N-ch open-drain 4-bit input/output port
	P50 to P53 *2	Input/output		—		(PORT5).			Input	M – A
						Data input/output pins for program memory
						write/verify (high-order 4 bits).
						Programmable 4-bit input/output port (PORT6).
	P60 to P63	Input/output		—		Input/output settable bit-wise.			Input	E – C
						Internal pull-up resistor specification by
						software is possible as a 4-bit unit.
	P70 to P73	Input/output		—		4-bit input/output port (PORT7).			Input		E

*1. A circle denotes Schmitt-triggerd input.

2. Direct LED drive capability

5

μPD75P238

1.1 PORT		PINS (2/2)
	Pin Name		Input/Output	Dual-			Function	8-Bit I/O	After Reset		Input/Output
				Function Pin							Circuit Type*1
	P80		Input/output		PPO						A
											F
	P81		Input/output	SCK1				×	Input
							4-bit input port (PORT8).
	P82		Input/output		SO1						E
	P83		Input		SI1						B
	P90 to P93		Input	AN4 to AN7			4-bit input port (PORT9).	×	Input		Y – A
	P100 to P103		Output	S16 to S19			P-ch open-drain 4-bit high-voltage output port.		High		I – D
	P110 to P113		Output	S20 to S23			P-ch open-drain 4-bit high-voltage output port.		impedance
							P-ch open-drain 4-bit high-voltage output port.				I – E
	P120 to P123		Output	S0 to S3			Internal pull-down resistors.		VLOAD
									level
							P-ch open-drain 4-bit high-voltage output port.
											I – E
	P130 to P133		Output	S4 to S7			Internal pull-down resistors.
	P140				S8				VLOAD		I – E
									level
							P-ch open-drain 4-bit high-voltage output port.
	P141		Output		S9		Internal pull-down resistor on P140 only.
											I – D
	P142*2			S10/T15
	P143*2			S11/T14					High
	P150*2
				S12/T13/PH0					impedance
	P151*2			S13/T12/PH1
			Output				P-ch open-drain 4-bit high-voltage output port.				I – D
	P152*2			S14/T11/PH2
	P153*2			S15/T10/PH3
	PH0			S12/T13/P150
	PH1		Output	S13/T12/P151				×	High
							P-ch open-drain 4-bit high-voltage output port.				I – D
									impedance
	PH2			S14/T11/P152
	PH3			S15/T10/P153

*1. A circle denotes Schmitt-triggerd input.

2. Direct LED drive capability.

6

μPD75P238

1.2 NON-PORT PINS (1/2)

Pin Name

Input/Output

Dual-

Function

After Reset

Input/Output

Function Pin

Circuit Type*

PPO

Output

P80

Timer/pulse generator pulse output pin.

Input

A

TI0

Input

P13

External event pulse input pin for timer/event counter #0

B

– C

or event counter #1.

PTO0

Output

P20

Timer/event counter output pin.

Input

E – B

PCL

Output

P22

Clock output pin.

Input

E – B

BUZ

Output

P23

Fixed-frequency output pin (for buzzer or system clock

Input

E – B

trimming use).

SCK0

Input/output

P01

Serial clock input/output pin.

Input

F

– A

SO0/SB0

Input/output

P02

Serial data output pin.

Input

F

– B

Serial bus input/output pin.

SI0/SB1

Input/output

P03

Serial data input pin.

Input

M

– C

Serial bus input/output pin.

INT4

Input

P00

Edge-detected vectored interrupt input pin (either rising

B

or falling edge detection).

INT0

P10

Edge-detected vectored

Clocked

B

– C

Input

interrupt input pin (detected

edge selectable).

INT1

P11

Asynchronous

INT2

Input

P12

Edge-detection testable input

Asynchronous

B

– C

pin (rising edge detection).

F

SCK1

Input/output

P81

Serial clock input/output pin.

Input

SO1

Output

P82

Serial data output pin.

Input

E

SI1

Input

P83

Serial data input pin.

Input

B

AN0 to AN3

Input

A/D converter analog input pin.

Y

AN4 to AN7

P90 to P93

Y – A

AVREF

Input

A/D converter reference voltage input pin.

Z

AVDD

A/D converter power supply pin.

AVSS

A/D converter reference GND potential pin.

Main system clock oscillation crystal/ceramic resonator

X1, X2

Input

input. When an external clock is used, the clock is input

to X1 and the inverted clock to X2.

XT1

Input

Subsystem clock oscillation crystal resonator input.

When an external clock is used,

the clock is input to XT1

XT2

and XT2 is left open.

RESET

Input

System reset input pin.

B

MD0 to MD3

Input

P30 to P33

Mode selection pin for program memory write/verify.

E – C

IC

Internally Connected . Connect to VSS directly.

Program voltage application pin for program memory

VPP

write/verify . Connected to VDD in normal operation.

Applies +12.5 V in program memory write/verify.

*A circle denotes Schmitt-triggerd input.

7

μPD75P238

1.2NON-PORT PINS (2/2)

Pin Name

Input/Output

Dual-

Function

After Reset

Input/Output

Function Pin

Circuit Type

VDD

Positive power supply pins. Apply +6 V in PROM

(3 pins)

write/verify.

VSS

Ground potential pin.

(2 pins)

VLOAD

FIP controller/driver pull-down resistor connection/ power

I – D

supply pin.

T0 to T9 *

Digit output high-voltage large large-current output pins.

VLOAD

I – E

level

T10/S15 to

PH3/P153 to

Digit/segment output dual-function high-voltage large-

High

current output pins. Unused pins usable as Port H.

I – D

T13/S12

PH0/P150

impedance

Usable as Port 15 in static mode.

T14/S11

P143

Digit/segment output dual-function high-voltage large-

High

I – D

current output pin.

impedance

T15/S10

P142

Usable as Port 14 in static mode.

S0 to S3 *

P120 to P123

VLOAD

I – E

level

Output

S4 to S7 *

P130 to P133

VLOAD

I – E

level

Segment high-voltage output pins. Usable as Port 12 to

S8 *

P140

Port 14 in static mode.

VLOAD

I – E

level

S9

P141

High

I – D

impedance

S16 to S19

P100 to P103

High

I – D

impedance

Segment high-voltage output pins. Usable as Port 10 &

S20 to S23

P110 to P113

Port 11 in static mode.

High

I – D

impedance

*Internal pull-down resistor

8

μPD75P238

1.3PIN INPUT/OUTPUT CIRCUITS

The input/output circuits for each of the pins are shown in Fig. 1-1 in partially simplified form.

Fig. 1-1 Pin Input/Output Circuits (1/3)

TYPE A	TYPE D
		VDD
VDD	data
		P-ch
P-ch		OUT
IN
N-ch	output	N-ch
	disable
	Push-Pull Output with High Impedance Output
CMOS Standard Input Buffer	Capability (P-ch and N-ch both OFF)
TYPE B	TYPE E

data	IN/OUT

Type D

IN	output
	disable

Type A

Schmitt-Triggered Input with Hysteresis		Input/Output Circuit Composed of Type D Push-Pull
Characteristics		Output and Type A Input Buffer
TYPE B-C		TYPE E-B		VDD
VDD				P.U.R.
	P.U.R.		output	P-ch
			disable
P-ch	P.U.R.
	enable	data		IN/OUT
			Type D
		output
		disable
IN
			Type A
P.U.R. : Pull-Up Resistor
Schmitt-Triggered Input with Hysteresis			P.U.R. : Pull-Up Resistor
Characteristics

9

						μPD75P238
		Fig. 1-1 Pin Input/Output Circuits (2/3)
	TYPE E-C	VDD	TYPE F-B			VDD
		P.U.R.				P.U.R.
	P.U.R.				P.U.R.	P-ch
		P-ch			enable
	enable					VDD
			output
			disable
	data	IN/OUT	(P-ch)			P-ch
						IN/OUT
	Type D		data
	output		output
	disable					N-ch
			disable
			output
			disable
		Type A	(N-ch)
						Type B
	P.U.R. :	Pull-Up Resistor	P.U.R. : Pull-Up Resistor
	TYPE F		TYPE F-C
						VDD
	data	IN/OUT				P.U.R.
	output	Type D	P.U.R.
						P-ch
	disable		enable
			data			IN/OUT
		Type B		Type D
			output
			disable
					Type B
	Input /Output Circuit Composed of Type D Push-		P.U.R.	:	Pull-Up Resistor
	Pull Output and Type B Schmitt-Triggered Input
	TYPE F-A		TYPE I-D
		VDD
		P.U.R.		VDD		VDD
	P.U.R.	P-ch
	enable
			data		P-ch	P-ch
	data	IN/OUT				OUT
	Type D
	output
	disable
					N-ch
		Type B
	P.U.R. : Pull-Up Resistor
	10

						μPD75P238
		Fig. 1-1 Pin Input/Output Circuits (3/3)
TYPE I-E			TYPE Y
	VDD	VDD
				P-ch		AVDD
data	P-ch	P-ch	IN			+
					Sam-
						-
		OUT	AVDD		pling
				N-ch	C
	N-ch	P.D.R			AVSS	AVSS
		VLOAD
			AVSS		Reference Voltage
					(From Series Resistance
	P.D.R: Pull-Down Resistor				String Voltage Tap)
TYPE M-A			TYPE Y-A
		IN/OUT
data		N-ch
output				P-ch		AVDD
			IN
disable						+
					Sam-
						-
			AVDD		pling
				N-ch	C
					AVSS	AVSS
	Middle-High Voltage Input Buffer		AVSS
					Reference Voltage
	P.U.R. :	Pull-Up Resistor			(From Series Resistance
	P.U.R: Pull-Up Resistor				String Voltage Tap)
TYPE M-C		VDD	TYPE Z
		P.U.R.
	P.U.R.	P-ch
	enable
		IN/OUT
data		N-ch
output
disable
	Type B
				AVSS
	P.U.R:P.UPull.R. -Up: PullResistor-Up Resistor
						11

μPD75P238

1.4 DISPOSITION OF UNUSED PIN
					Table 1-2	Recommended Commection of Unused Pins (1/2)
					Pin				Recommended Connection
	P00/INT4						Connect to VSS.
	P01/SCK0
	P02/SO0/SB0						Connect	to VSS or VDD.
	P03/SI1/SB1
	P10/INT0 to P12/INT2
							Connect to VSS.
	P13/TI0
	P20/PTO0
	P21
	P22/PCL
	P23/BUZ
							Input state		:	Connect to VSS or VDD.
	P30 to P33						Output	state	:	Leave open.
	P40 to P43
	P50 to P53
	P60 to P63
	P70 to P73
	P80 to PPO
	P81 to SCK1
							Connect	to VSS or VDD.
	P82/SO1
	P83/SI1
	P90/AN4 to P93/AN7						Connect to VSS.

12

μPD75P238

Table 1-2	Recommended Commection of Unused Pins (2/2)
Pin		Recommended Connection
P100/S16 to P103/S19
P110/S20 to P113/S23
P120 to P123		Leave open.
P130 to P133
P140 to P143
P150 to P153
AN0 to AN3
		Connect to VSS.
AVREF
AVDD		Connect to VDD.
AVSS		Connect to VSS.
XT1		Connect to VSS or VDD.
XT2		Leave open.
VLOAD		Connect to VSS or leave open.
IC		Connect to VSS.

13

μPD75P238

2. DIFFERENCES BETWEEN μPD75P238 AND μPD75238

The μPD75P238 is a product with the program memory of the μPD75238 using on-chip mask ROM replaced by one-time PROM or EPROM. Table 2-1 shows differences between μPD75P238 and μPD75238. The differences between these products must be thoroughly checked when, for example, switching from use of PROM for application system debugging and reproduction to use of a mask ROM product for volume production.

For details of CPU function and on-chip hardware, refer to the document "μPD75238 User's Manual" (IEU-731).

Table 2-1 Differences between μPD75P238 and μPD75238

		Parameter	Product Name	μPD75238		μPD75P238
		ROM		Mask ROM		One-time PROM, EPROM
				32K × 8		32K × 8
		RAM			1K × 4
		FIP controller/	No. of segments		9 to 24
		driver
			No. of digits		9 to16
		Pull-up resistors	Ports 4 & 5			No
			Port 7			No
			S0 to S8			On-chip
			S9	Mask option		No
		Pull-down
			S16 to S23			No
		resistors
			T0 to T9			On-chip
			T10 to T15			No
		Pin connection	Pin 5	VDD		VPP
			Pins 70 to 73	P30 to P33		P30/MD0 to P33/MD3
				The mask ROM products and PROM products have different consumption
		Electrical specifications		currents, operating temperature range etc. See the Electrical Specifications
				section in the relevant Data Sheet for details.
		Operating supply voltage range			2.7 to 6.0 V
		Subsystem clock feedback resistor		Mask option		On-chip
		Package		94-pin plastic QFP (■20 mm)		94-pin plastic QFP (■20 mm)
						94-pin ceramic WQFN
				The mask ROM products and PROM products have different circuit scales and
		Others		mask layouts, and therefore differ in terms of noise resistance and noise
				radiation.

Note Noise resistance and noise radiation differs between the PROM products and mask ROM products.

When investigating a switch from preproduction to volume production, throughout evaluation should be carried out with the mask ROM CS product (not the ES product).

14

μPD75P238

3. PROGRAM MEMORY (PROM)

The program memory is PROM with a 32640 × 8-bit configuration wich stores program and table tata etc. The program memory is addressed by the program counter. In addition, table data can be referenced by a table

referencing instruction (MOVT).

The rage of address to which branch instructions and subroutine call instructions and subroutine call instructions and subroutine call instructions can branch is shown in Fig. 3-1. The entire space comprising 0000H to 7F7FH can be directly branched to by the entire-space branch instruction (BRA !addr1) and the entire-space call instruction (CALLA !addr1). The relative branch instruction (BR $addr) allows branching to addresses [PC contents –15 to –1 and +2 to +16] irrespective of block boundaries.

In addition, the following addresses are specially allocated (except for 0000H and 0001H, the entire area can be used as ordinary program memory).

•Addresses 0000H & 0001H

Vector table to which the program start address and MBE & RBE set value upon RESET input are written. Reset servicing can be started from any address in the 16K (000H to 3FFFH).

•Addresses 0002H to 000FH

Vector table to which the program start address and MBE & RBE set value for the various vectore interrupts are written. Interrupt servicing can be started from any address in the 16K space (0000H to 3FFFH).

•Addresses 0020H to 007FH

Table area referenced by GETI instruction*.

*The GETI instruction allows any 2- or 3-byte instruction or any two 1-byte instructions to be implemented as 1 byte, and is used to reduce the number of program steps.

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