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UPD75P238GJ-5BG |
DATA SHEET |
MOS INTEGRATED CIRCUIT
μPD75P238
4-BIT SINGLE CHIP MICROCOMPUTER
DESCRIPTION
The μPD75P238 is a version of the μPD75238 in which the on-chip mask ROM is replaced by one-time PROM or EPROM.
The one-time PROM version can be written to once only, and is useful for short-run and multiple deviceproduction of sets and early start-up. Also, the EPROM version allows programs to be written and rewritten, and is thus ideal for system evaluation.
Functions are described in detail in the following User's Manual, which should be read when carrying out design
work.
μPD75238 User's Manual : IEU-731
The μPD75P238 EPROM product does not provide a level of reliability suitable for use as a volume production product for users' devices. The EPROM product should be used solely for function evaluation in experiments of preproduction.
FEATURES
o μPD75238 pin compatible |
o High-voltage display outputs |
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o On-chip PROM: 32640 × 8 |
. S0 to S8 & T0 to T9 |
: Internal pull-down resistors |
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o On-chip RAM: 1024 × 4 |
. S9, S16 to S23 & T10 to T15: Open-drain |
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o Drive capability in same supply voltage range as mask version μPD75238 (2.7 to 6.0 V) |
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o Ports |
4 & 5: No pull-up resistor |
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o Port 7: No pull-down resistor |
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Note |
No internal pull-up and pull-down resistor function by mask option. |
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USE |
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VCR, |
Audio-visual, ECR, Microwave oven |
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ORDERING INFORMATION
Ordering Code |
Package |
On-Chip ROM |
Quality Grade |
μPD75P238GJ-5BG |
94-pin plastic QFP(■20 mm) |
One-time PROM |
Standard |
μPD75P238KF |
94-pin ceramic WQFN |
EPROM |
Standard |
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
This manual describes common parts of One-time PROM and EPROM products as PROM.
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The information in this document is subject to change without notice. |
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Document No. IC-2596A |
The mark shows major revised points. |
(O.D. No. IC-8014A) |
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Date Published February 1994 P |
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Printed in Japan |
© NEC Corporation 1992 |
μPD75P238
PIN CONFIGURATION (TOP VIEW)
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AN1 |
AN2 |
AN3 AN4/P90 AN5/P91 AN6/P92 |
AN7/P93 AVSS RESET P00/INT4 P01/SCK0 P02/SO0/SB0 |
P03/SI0/SB1 P10 /INT0 P11/INT1 P12/INT2 |
P13/TI0 P20/PTO0 P21 |
P22/PCL |
P23/BUZ |
P30/MD0 |
P31/MD1 |
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94 93 |
92919089 |
8887 868584838281807978777675747372 |
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71 |
P32/MD2 |
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AN0 |
1 |
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70 |
P33/MD3 |
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AVREF |
2 |
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69 |
P40 |
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AVDD |
3 |
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68 |
P41 |
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VDD |
4 |
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67 |
P42 |
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VPP |
5 |
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66 |
P43 |
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X2 |
6 |
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65 |
VSS |
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X1 |
7 |
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64 |
P50 |
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IC |
8 |
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PD75P238KFμ |
-PD75P238GJμ |
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63 |
P51 |
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XT2 |
9 |
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57 |
P63 |
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S18/P102 |
14 |
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XT1 |
10 |
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62 |
P52 |
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61 |
P53 |
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VSS |
11 |
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60 |
P60 |
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S16/P100 |
12 |
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59 |
P61 |
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S17/P101 |
13 |
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58 |
P62 |
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S19/P103 |
15 |
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5BG |
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56 |
P70 |
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S20/P110 |
16 |
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55 |
P71 |
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S21/P111 |
17 |
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54 |
P72 |
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S22/P112 |
18 |
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53 |
P73 |
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S23/P113 |
19 |
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52 |
P80/PPO |
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S0/P120 |
20 |
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51 |
P81/SCK1 |
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S1/P121 |
21 |
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50 |
P82/SO1 |
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S2/P122 |
22 |
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49 |
P83/SI1 |
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S3/P123 |
23 |
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48 |
VDD |
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24 25262728 293031323334353637383940414243 |
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44 45 4647 |
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S4/P130 |
S5/P131 |
S6/P132 |
S7/P133 S8/P140 S9/P141 VDD |
VLOAD T15/S10/P142 T14/S11/P143 PH0/T13/S12/P150 PH1/T12/S13/P151 PH2/T11/S14/P152 |
PH3/T10/S15/P153 T9 T8 T7 |
T6 T5 T4 |
T3 |
T2 |
T1 |
T0 |
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Note |
Ensure that power is supplied to the VDD and VSS pins (pins 4, 11, 30, 48, and 65). |
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Remarks IC (Internally Connected) pins should be connected directly to VSS. |
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2
μPD75P238
PIN NAME
P00 to P03 |
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Port0 |
SCK0, SCK1 |
: Serial Clock I/O 0, 1 |
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P10 to P13 |
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Port1 |
SO0, SO1 |
: Serial Data Output 0, 1 |
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P20 to P23 |
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Port2 |
SI0, SI1 |
: Serial Data Input 0, 1 |
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P30 to P33 |
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Port3 |
SB0, SB1 |
: Serial Bus I/O 0, 1 |
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P40 to P43 |
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Port4 |
INT0, INT1, INT4 |
: External Vectored Interrupt Input 0, 1, 4 |
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P50 to P53 |
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Port5 |
INT2 |
: External Test Input 2 |
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P60 to P63 |
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Port6 |
PPO |
: Programmable Pulse Output |
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P70 to P73 |
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Port7 |
TI0 |
: Timer Input 0 |
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P80 to P83 |
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Port8 |
PTO0 |
: Programmable Timer Output 0 |
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P90 to P93 |
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Port9 |
BUZ |
: Buzzer Clock |
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P100 to P103 |
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Port10 |
PCL |
: Programmable Clock Output |
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P110 to P113 |
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Port11 |
AN0 to AN7 |
: Analog Input 0 to 7 |
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P120 to P123 |
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Port12 |
AVREF |
: Analog Reference Voltage |
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P130 to P133 |
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Port13 |
AVDD |
: Analog VDD |
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P140 to P143 |
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Port14 |
AVSS |
: Analog VSS |
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P150 to P153 |
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Port15 |
X1, X2 |
: Main System Clock Oscillation 1, 2 |
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PH0 to PH3 |
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PortH |
XT1, XT2 |
: Subsystem Clock Oscillation 1, 2 |
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T0 to T15 |
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Digit Output |
RESET |
: Reset |
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S0 to S23 |
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Segment Output |
VPP |
: Programming Power Supply |
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VDD |
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Positive Power Supply |
MD0 to MD3 |
: Mode Selection 0 to 3 |
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VSS |
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Ground |
IC |
: Internally Connected |
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VLOAD |
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Power Supply for FIP Driver |
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3
4
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BASIC |
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INTERVAL |
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TIMER |
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TIO |
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INTBT |
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TI0/P13 |
TIMER/EVENT |
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COUNTER |
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PTO0/P20 |
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#0 |
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INTT0 |
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BUZ/P23 |
WATCH |
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TIMER |
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INTW |
TIMER/
PPO/P80 PULSE
GENELATOR
INTTPG
SI0/SB1/P03
SO0/SB0/P02
SERIAL
INTERFACE
SCK0/P01
INTCSI
SI1/P83 SERIAL
SO1/P82 INTERFACE
SCK1/P81
INT0/P10
INT1/P11 INTERRUPT
INT2/P12 CONTROL
INT4/P00
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TI0 |
EVENT |
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COUNTER |
AN0-AN3 |
8 |
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AN4/P90-AN7/P93 |
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A/D |
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AVDD |
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CONVERTER |
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AVREF |
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AVSS |
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BIT SEQ. |
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BUFFER(16) |
PORT 0 |
4 |
P00-P03 |
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PORT 1 |
4 |
P10-P13 |
SP (8)
PROGRAM |
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CY |
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COUNTER (15) |
ALU |
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SBS (2) |
PORT 2 |
4 |
P20-P23 |
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BANK |
PORT 3 |
4 |
P30/MD0 |
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-P33/MD3 |
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PORT 4 |
4 |
P40-P43 |
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PORT 5 |
4 |
P50-P53 |
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ROM |
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GENERAL REG. |
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PORT 6 |
4 |
P60-P63 |
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PROGRAM |
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MEMORY |
DECODE |
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32640 × 8 |
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PORT 7 |
4 |
P70-P73 |
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AND |
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CONTROL |
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RAM |
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DATA |
PORT 8 |
4 |
P80-P83 |
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MEMORY |
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1024 × 4 |
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4 |
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PORT 9 |
P90-P93 |
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10 |
T0-T9 |
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4 |
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T10/S15/PH3/P153- |
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T13/S12/PH0/P150 |
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fX / 2N |
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FIP |
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T14/S11/ P143- |
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CLOCK |
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CONTROLLER/ 2 |
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CLOCK |
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T15/S10/P142 |
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CLOCK |
STAND BY |
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DRIVER |
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GENERATOR |
CPU CLOCK |
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OUTPUT |
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DIVIDER |
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CONTROL |
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S0/P120-S9/P141 |
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CONTROL |
SUB |
MAIN |
Φ |
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10 |
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XT1 XT2 |
X1 X2 |
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8 |
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S16/P100-S23/P113 |
PCL/P22 |
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VLOAD |
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PORT 10-15 |
24 |
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P100-P153 |
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RESET VDD VSS |
VPP |
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DIAGRAM BLOCK
PD75P238μ
μPD75P238
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
Pin Name |
Input/Output |
Dual-Function |
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Function |
8-Bit I/O |
After Reset |
Input/Output |
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Pin |
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Circuit Type*1 |
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P00 |
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INT4 |
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B |
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4-bit input port (PORT0). |
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P01 |
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SCK0 |
Internal pull-up resistor specification by |
× |
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F |
– A |
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Input |
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software is possible for P01 to P03 as a 3- |
Input |
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P02 |
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SO0/SB0 |
bit unit. |
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F |
– B |
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P03 |
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SI0/SB1 |
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M |
– C |
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P10 |
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INT0 |
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With noise elimination |
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function |
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P11 |
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INT1 |
4-bit input port (PORT1). |
× |
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Input |
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Internal pull-up resistor specification by |
Input |
B |
– C |
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P12 |
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INT2 |
software is possible as a 4-bit unit. |
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P13 |
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TI0 |
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P20 |
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PTO0 |
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P21 |
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— |
4-bit input/output port (PORT2). |
× |
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Input/output |
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Internal pull-up resistor specification by |
Input |
E – B |
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P22 |
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PCL |
software is possible as a 4-bit unit. |
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P23 |
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BUZ |
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Programmable 4-bit input/output port (PORT3). |
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P30 to P33 *2 |
Input/output |
MD0 to MD3 |
Input/output settable bit-wise. |
× |
Input |
E – C |
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Internal pull-up resistor specification by |
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software is possible as a 4-bit unit. |
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N-ch open-drain 4-bit input/output port |
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P40 to P43 *2 |
Input/output |
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— |
(PORT4). |
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Input |
M – A |
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Data input/output pins for program memory |
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write/verify (low-order 4 bits). |
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N-ch open-drain 4-bit input/output port |
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P50 to P53 *2 |
Input/output |
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— |
(PORT5). |
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Input |
M – A |
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Data input/output pins for program memory |
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write/verify (high-order 4 bits). |
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Programmable 4-bit input/output port (PORT6). |
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P60 to P63 |
Input/output |
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Input/output settable bit-wise. |
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Input |
E – C |
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Internal pull-up resistor specification by |
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software is possible as a 4-bit unit. |
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P70 to P73 |
Input/output |
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4-bit input/output port (PORT7). |
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Input |
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E |
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*1. A circle denotes Schmitt-triggerd input.
2. Direct LED drive capability
5
μPD75P238
1.1 PORT |
PINS (2/2) |
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Pin Name |
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Input/Output |
Dual- |
Function |
8-Bit I/O |
After Reset |
Input/Output |
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Function Pin |
Circuit Type*1 |
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P80 |
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Input/output |
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PPO |
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A |
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F |
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P81 |
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Input/output |
SCK1 |
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× |
Input |
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4-bit input port (PORT8). |
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P82 |
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Input/output |
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SO1 |
E |
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P83 |
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Input |
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SI1 |
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B |
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P90 to P93 |
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Input |
AN4 to AN7 |
4-bit input port (PORT9). |
× |
Input |
Y – A |
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P100 to P103 |
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Output |
S16 to S19 |
P-ch open-drain 4-bit high-voltage output port. |
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High |
I – D |
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P110 to P113 |
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Output |
S20 to S23 |
P-ch open-drain 4-bit high-voltage output port. |
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impedance |
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P-ch open-drain 4-bit high-voltage output port. |
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I – E |
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P120 to P123 |
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Output |
S0 to S3 |
Internal pull-down resistors. |
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VLOAD |
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level |
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P-ch open-drain 4-bit high-voltage output port. |
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I – E |
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P130 to P133 |
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Output |
S4 to S7 |
Internal pull-down resistors. |
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P140 |
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S8 |
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VLOAD |
I – E |
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level |
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P-ch open-drain 4-bit high-voltage output port. |
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P141 |
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Output |
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S9 |
Internal pull-down resistor on P140 only. |
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I – D |
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P142*2 |
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S10/T15 |
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P143*2 |
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S11/T14 |
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High |
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P150*2 |
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S12/T13/PH0 |
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impedance |
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P151*2 |
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S13/T12/PH1 |
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Output |
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P-ch open-drain 4-bit high-voltage output port. |
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I – D |
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P152*2 |
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S14/T11/PH2 |
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P153*2 |
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S15/T10/PH3 |
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PH0 |
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S12/T13/P150 |
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PH1 |
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Output |
S13/T12/P151 |
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× |
High |
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P-ch open-drain 4-bit high-voltage output port. |
I – D |
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impedance |
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PH2 |
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S14/T11/P152 |
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PH3 |
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S15/T10/P153 |
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*1. A circle denotes Schmitt-triggerd input.
2. Direct LED drive capability.
6
μPD75P238
1.2 NON-PORT PINS (1/2)
Pin Name |
Input/Output |
Dual- |
Function |
After Reset |
Input/Output |
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Function Pin |
Circuit Type* |
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PPO |
Output |
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P80 |
Timer/pulse generator pulse output pin. |
Input |
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A |
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TI0 |
Input |
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P13 |
External event pulse input pin for timer/event counter #0 |
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B |
– C |
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or event counter #1. |
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PTO0 |
Output |
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P20 |
Timer/event counter output pin. |
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Input |
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E – B |
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PCL |
Output |
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P22 |
Clock output pin. |
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Input |
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E – B |
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BUZ |
Output |
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P23 |
Fixed-frequency output pin (for buzzer or system clock |
Input |
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E – B |
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trimming use). |
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SCK0 |
Input/output |
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P01 |
Serial clock input/output pin. |
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Input |
F |
– A |
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SO0/SB0 |
Input/output |
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P02 |
Serial data output pin. |
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Input |
F |
– B |
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Serial bus input/output pin. |
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SI0/SB1 |
Input/output |
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P03 |
Serial data input pin. |
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Input |
M |
– C |
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Serial bus input/output pin. |
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INT4 |
Input |
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P00 |
Edge-detected vectored interrupt input pin (either rising |
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B |
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or falling edge detection). |
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INT0 |
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P10 |
Edge-detected vectored |
Clocked |
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B |
– C |
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Input |
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interrupt input pin (detected |
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edge selectable). |
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INT1 |
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P11 |
Asynchronous |
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INT2 |
Input |
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P12 |
Edge-detection testable input |
Asynchronous |
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B |
– C |
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pin (rising edge detection). |
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F |
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SCK1 |
Input/output |
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P81 |
Serial clock input/output pin. |
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Input |
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SO1 |
Output |
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P82 |
Serial data output pin. |
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Input |
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E |
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SI1 |
Input |
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P83 |
Serial data input pin. |
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Input |
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B |
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AN0 to AN3 |
Input |
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A/D converter analog input pin. |
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Y |
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AN4 to AN7 |
P90 to P93 |
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Y – A |
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AVREF |
Input |
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A/D converter reference voltage input pin. |
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Z |
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AVDD |
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A/D converter power supply pin. |
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AVSS |
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A/D converter reference GND potential pin. |
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Main system clock oscillation crystal/ceramic resonator |
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X1, X2 |
Input |
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input. When an external clock is used, the clock is input |
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to X1 and the inverted clock to X2. |
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XT1 |
Input |
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Subsystem clock oscillation crystal resonator input. |
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When an external clock is used, |
the clock is input to XT1 |
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XT2 |
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and XT2 is left open. |
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RESET |
Input |
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System reset input pin. |
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B |
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MD0 to MD3 |
Input |
P30 to P33 |
Mode selection pin for program memory write/verify. |
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E – C |
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IC |
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Internally Connected . Connect to VSS directly. |
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Program voltage application pin for program memory |
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VPP |
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write/verify . Connected to VDD in normal operation. |
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Applies +12.5 V in program memory write/verify. |
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*A circle denotes Schmitt-triggerd input.
7
μPD75P238
1.2NON-PORT PINS (2/2)
Pin Name |
Input/Output |
Dual- |
Function |
After Reset |
Input/Output |
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Function Pin |
Circuit Type |
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VDD |
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Positive power supply pins. Apply +6 V in PROM |
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(3 pins) |
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write/verify. |
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VSS |
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Ground potential pin. |
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(2 pins) |
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VLOAD |
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FIP controller/driver pull-down resistor connection/ power |
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I – D |
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supply pin. |
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T0 to T9 * |
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Digit output high-voltage large large-current output pins. |
VLOAD |
I – E |
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level |
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T10/S15 to |
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PH3/P153 to |
Digit/segment output dual-function high-voltage large- |
High |
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current output pins. Unused pins usable as Port H. |
I – D |
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T13/S12 |
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PH0/P150 |
impedance |
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Usable as Port 15 in static mode. |
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T14/S11 |
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P143 |
Digit/segment output dual-function high-voltage large- |
High |
I – D |
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current output pin. |
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impedance |
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T15/S10 |
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P142 |
Usable as Port 14 in static mode. |
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S0 to S3 * |
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P120 to P123 |
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VLOAD |
I – E |
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level |
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Output |
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S4 to S7 * |
P130 to P133 |
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VLOAD |
I – E |
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level |
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Segment high-voltage output pins. Usable as Port 12 to |
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S8 * |
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P140 |
Port 14 in static mode. |
VLOAD |
I – E |
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level |
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S9 |
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P141 |
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High |
I – D |
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impedance |
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S16 to S19 |
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P100 to P103 |
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High |
I – D |
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impedance |
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Segment high-voltage output pins. Usable as Port 10 & |
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S20 to S23 |
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P110 to P113 |
Port 11 in static mode. |
High |
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I – D |
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impedance |
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*Internal pull-down resistor
8
μPD75P238
1.3PIN INPUT/OUTPUT CIRCUITS
The input/output circuits for each of the pins are shown in Fig. 1-1 in partially simplified form.
Fig. 1-1 Pin Input/Output Circuits (1/3)
TYPE A |
TYPE D |
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VDD |
VDD |
data |
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P-ch |
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P-ch |
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OUT |
IN |
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N-ch |
output |
N-ch |
disable |
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Push-Pull Output with High Impedance Output |
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CMOS Standard Input Buffer |
Capability (P-ch and N-ch both OFF) |
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TYPE B |
TYPE E |
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data |
IN/OUT |
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Type D
IN |
output |
disable |
Type A
Schmitt-Triggered Input with Hysteresis |
Input/Output Circuit Composed of Type D Push-Pull |
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Characteristics |
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Output and Type A Input Buffer |
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TYPE B-C |
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TYPE E-B |
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VDD |
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VDD |
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P.U.R. |
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P.U.R. |
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output |
P-ch |
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disable |
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P-ch |
P.U.R. |
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enable |
data |
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IN/OUT |
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Type D |
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output |
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disable |
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IN |
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Type A |
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P.U.R. : Pull-Up Resistor |
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Schmitt-Triggered Input with Hysteresis |
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P.U.R. : Pull-Up Resistor |
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Characteristics |
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9
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μPD75P238 |
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Fig. 1-1 Pin Input/Output Circuits (2/3) |
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TYPE E-C |
VDD |
TYPE F-B |
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VDD |
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P.U.R. |
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P.U.R. |
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P.U.R. |
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P.U.R. |
P-ch |
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P-ch |
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enable |
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enable |
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VDD |
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output |
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disable |
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data |
IN/OUT |
(P-ch) |
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P-ch |
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IN/OUT |
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Type D |
data |
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output |
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output |
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disable |
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N-ch |
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disable |
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output |
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disable |
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Type A |
(N-ch) |
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Type B |
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P.U.R. : |
Pull-Up Resistor |
P.U.R. : Pull-Up Resistor |
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TYPE F |
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TYPE F-C |
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VDD |
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data |
IN/OUT |
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P.U.R. |
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output |
Type D |
P.U.R. |
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P-ch |
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disable |
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enable |
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data |
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IN/OUT |
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Type B |
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Type D |
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output |
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disable |
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Type B |
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Input /Output Circuit Composed of Type D Push- |
P.U.R. |
: |
Pull-Up Resistor |
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Pull Output and Type B Schmitt-Triggered Input |
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TYPE F-A |
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TYPE I-D |
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VDD |
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P.U.R. |
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VDD |
VDD |
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P.U.R. |
P-ch |
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enable |
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data |
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P-ch |
P-ch |
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data |
IN/OUT |
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OUT |
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Type D |
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output |
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disable |
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N-ch |
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Type B |
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P.U.R. : Pull-Up Resistor |
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10 |
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μPD75P238 |
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Fig. 1-1 Pin Input/Output Circuits (3/3) |
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TYPE I-E |
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TYPE Y |
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VDD |
VDD |
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P-ch |
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AVDD |
data |
P-ch |
P-ch |
IN |
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+ |
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Sam- |
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- |
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OUT |
AVDD |
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pling |
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N-ch |
C |
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N-ch |
P.D.R |
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AVSS |
AVSS |
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VLOAD |
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AVSS |
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Reference Voltage |
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(From Series Resistance |
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P.D.R: Pull-Down Resistor |
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String Voltage Tap) |
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TYPE M-A |
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TYPE Y-A |
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IN/OUT |
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data |
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N-ch |
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output |
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P-ch |
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AVDD |
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IN |
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disable |
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+ |
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Sam- |
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- |
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AVDD |
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pling |
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N-ch |
C |
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AVSS |
AVSS |
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Middle-High Voltage Input Buffer |
AVSS |
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Reference Voltage |
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P.U.R. : |
Pull-Up Resistor |
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(From Series Resistance |
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P.U.R: Pull-Up Resistor |
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String Voltage Tap) |
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TYPE M-C |
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VDD |
TYPE Z |
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P.U.R. |
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P.U.R. |
P-ch |
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enable |
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IN/OUT |
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data |
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N-ch |
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output |
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disable |
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Type B |
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AVSS |
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P.U.R:P.UPull.R. -Up: PullResistor-Up Resistor |
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11 |
μPD75P238
1.4 DISPOSITION OF UNUSED PIN |
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Table 1-2 |
Recommended Commection of Unused Pins (1/2) |
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Pin |
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Recommended Connection |
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P00/INT4 |
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Connect to VSS. |
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P01/SCK0 |
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P02/SO0/SB0 |
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Connect |
to VSS or VDD. |
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P03/SI1/SB1 |
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P10/INT0 to P12/INT2 |
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Connect to VSS. |
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P13/TI0 |
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P20/PTO0 |
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P21 |
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P22/PCL |
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P23/BUZ |
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Input state |
: |
Connect to VSS or VDD. |
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P30 to P33 |
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Output |
state |
: |
Leave open. |
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P40 to P43 |
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P50 to P53 |
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P60 to P63 |
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P70 to P73 |
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P80 to PPO |
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P81 to SCK1 |
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Connect |
to VSS or VDD. |
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P82/SO1 |
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P83/SI1 |
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P90/AN4 to P93/AN7 |
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Connect to VSS. |
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12
μPD75P238
Table 1-2 |
Recommended Commection of Unused Pins (2/2) |
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Pin |
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Recommended Connection |
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P100/S16 to P103/S19 |
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P110/S20 to P113/S23 |
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P120 to P123 |
|
Leave open. |
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P130 to P133 |
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P140 to P143 |
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P150 to P153 |
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AN0 to AN3 |
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Connect to VSS. |
|
AVREF |
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AVDD |
|
Connect to VDD. |
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AVSS |
|
Connect to VSS. |
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XT1 |
|
Connect to VSS or VDD. |
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|
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XT2 |
|
Leave open. |
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VLOAD |
|
Connect to VSS or leave open. |
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|
IC |
|
Connect to VSS. |
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|
13
μPD75P238
2. DIFFERENCES BETWEEN μPD75P238 AND μPD75238
The μPD75P238 is a product with the program memory of the μPD75238 using on-chip mask ROM replaced by one-time PROM or EPROM. Table 2-1 shows differences between μPD75P238 and μPD75238. The differences between these products must be thoroughly checked when, for example, switching from use of PROM for application system debugging and reproduction to use of a mask ROM product for volume production.
For details of CPU function and on-chip hardware, refer to the document "μPD75238 User's Manual" (IEU-731).
Table 2-1 Differences between μPD75P238 and μPD75238
|
Parameter |
Product Name |
μPD75238 |
|
μPD75P238 |
|
|
|
|
|
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||
|
|
|
|
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|
|
|
ROM |
|
Mask ROM |
|
One-time PROM, EPROM |
|
|
|
32K × 8 |
|
32K × 8 |
||
|
|
|
|
|||
|
|
|
|
|
|
|
|
RAM |
|
|
1K × 4 |
||
|
|
|
|
|
|
|
|
FIP controller/ |
No. of segments |
|
9 to 24 |
||
|
|
|
|
|
||
|
driver |
|
|
|
|
|
|
No. of digits |
|
9 to16 |
|||
|
|
|
||||
|
|
|
|
|
|
|
|
Pull-up resistors |
Ports 4 & 5 |
|
|
No |
|
|
|
|
|
|
|
|
|
|
Port 7 |
|
|
No |
|
|
|
|
|
|
|
|
|
|
S0 to S8 |
|
|
On-chip |
|
|
|
|
|
|
|
|
|
|
S9 |
Mask option |
|
No |
|
|
Pull-down |
|
|
|
|
|
|
S16 to S23 |
|
|
No |
||
|
resistors |
|
|
|||
|
|
|
|
|
|
|
|
|
T0 to T9 |
|
|
On-chip |
|
|
|
|
|
|
|
|
|
|
T10 to T15 |
|
|
No |
|
|
|
|
|
|
|
|
|
Pin connection |
Pin 5 |
VDD |
|
VPP |
|
|
|
|
|
|
||
|
Pins 70 to 73 |
P30 to P33 |
|
P30/MD0 to P33/MD3 |
||
|
|
|
||||
|
|
|
|
|
||
|
|
|
The mask ROM products and PROM products have different consumption |
|||
Electrical specifications |
currents, operating temperature range etc. See the Electrical Specifications |
|||||
|
||||||
|
|
|
section in the relevant Data Sheet for details. |
|||
|
|
|
|
|
||
|
Operating supply voltage range |
|
2.7 to 6.0 V |
|||
|
|
|
|
|
||
|
Subsystem clock feedback resistor |
Mask option |
|
On-chip |
||
|
|
|
|
|
|
|
|
Package |
|
94-pin plastic QFP (■20 mm) |
|
94-pin plastic QFP (■20 mm) |
|
|
|
|
94-pin ceramic WQFN |
|||
|
|
|
|
|
||
|
|
|
|
|
||
|
|
|
The mask ROM products and PROM products have different circuit scales and |
|||
Others |
|
mask layouts, and therefore differ in terms of noise resistance and noise |
||||
|
|
|||||
|
|
|
radiation. |
|
|
|
|
|
|
|
|
|
Note Noise resistance and noise radiation differs between the PROM products and mask ROM products.
When investigating a switch from preproduction to volume production, throughout evaluation should be carried out with the mask ROM CS product (not the ES product).
14
μPD75P238
3. PROGRAM MEMORY (PROM)
The program memory is PROM with a 32640 × 8-bit configuration wich stores program and table tata etc. The program memory is addressed by the program counter. In addition, table data can be referenced by a table
referencing instruction (MOVT).
The rage of address to which branch instructions and subroutine call instructions and subroutine call instructions and subroutine call instructions can branch is shown in Fig. 3-1. The entire space comprising 0000H to 7F7FH can be directly branched to by the entire-space branch instruction (BRA !addr1) and the entire-space call instruction (CALLA !addr1). The relative branch instruction (BR $addr) allows branching to addresses [PC contents –15 to –1 and +2 to +16] irrespective of block boundaries.
In addition, the following addresses are specially allocated (except for 0000H and 0001H, the entire area can be used as ordinary program memory).
•Addresses 0000H & 0001H
Vector table to which the program start address and MBE & RBE set value upon RESET input are written. Reset servicing can be started from any address in the 16K (000H to 3FFFH).
•Addresses 0002H to 000FH
Vector table to which the program start address and MBE & RBE set value for the various vectore interrupts are written. Interrupt servicing can be started from any address in the 16K space (0000H to 3FFFH).
•Addresses 0020H to 007FH
Table area referenced by GETI instruction*.
*The GETI instruction allows any 2- or 3-byte instruction or any two 1-byte instructions to be implemented as 1 byte, and is used to reduce the number of program steps.
15