NEC PD70732 DATA SHEET

DATA SHEET

MOS Integrated Circuit

PD70732

V810

32-BIT MICROPROCESSOR

The µPD70732 (a.k.a. V810) microprocessor is NEC’s first microprocessor of the V810 familyTM for embedded

control applications.

The V810 employs a RISC architecture for embedded control applications. This product has high-speed real time response, high-speed integer operation instruction, bit string instruction, floating-point operation instruction, and significantly high cost performance is realized for applications such as facsimile, digital PPC, word processor, image processor, real time control device, etc.

The functions are described in detail in the following User’s Manuals, which should be read before starting design work.

• V805

• V810 Family User’s Manual Architecture : U10082E

Features

, V810 User’s Manual Hardware : U10661E

High-performance 32-bit architecture for embedded control application

• 32-bit separate address/data bus

• 1-Kbyte cache memory

• Pipeline structure of 1 clock pitch

• 16-bit fixed instructions (with some exceptions)

• 32-bit general-purpose registers: 32

• 4-Gbyte linear address space

• Register/flag hazard interlocked by hardware Dynamic bus sizing function (16 bits) 16-bit bus fixing function 16-bit bus system can be configured. Instructions ideal for various application fields

• Floating-point operation instructions (based upon IEEE754 data format)

• Bit string instructions 16 levels of high-speed interrupt responses Clock can be stopped by internal static operation Maximum operating frequency: 16/20/25 MHz Low voltage: VDD = 2.7 to 3.6 V (Max. 16 MHz)

DD = 2.2 to 3.6 V (Max. 10 MHz)

Small package versions available (14 x 14 mm fine-pitch TQFP)

★

The information in this document is subject to change without notice.

Document No. U10691EJ3V0DS00 (3rd edition) Date Published September 1996 P Printed in Japan

The mark ★ shows major revised points.

1993

Ordering Information

µ µ µ

★

µ µ

Pin Outline

µPD70732

Part Number Package Max. operating freq. (MHz)

PD70732GD-16-LBB 120-pin plastic QFP (28 x 28 mm) 16 PD70732GD-20-LBB 120-pin plastic QFP (28 x 28 mm) 20 PD70732GD-25-LBB 120-pin plastic QFP (28 x 28 mm) 25 PD70732GC-25-9EV 120-pin plastic TQFP (Fine pitch) (14 x 14 mm) 25 PD70732R-25 176-pin ceramic PGA (Seam weld) 25

A31 to A1

CLK

RESET

INT

INTV3 to INTV0

NMI

HLDRQ

HLDAK

V810

D31 to D0

BE3 to BE0

ST1, ST0

MRQ

R/W

BCYST

BLOCK

READY

SZRQ

SIZ16B

ICHEEN

ADRSERR

Pin Configuration

• 120-pin plastic QFP (28 x 28 mm) (Top View)

PD70732GD-xx-LBB

µPD70732

IC1

IC2

ICHEEN

NMI

INT

INTV0

INTV1

INTV2

120

119

118

117

116

115

114

113

112

INTV3

BLOCK

111

110

GND

108

109

CLK

107

2IC1 3IC1 4IC1 5RESET 6D0 7D1 8D2

9GND 10D3 11D4 12GND 13D5 14D6 15D7

DD DD

16V 17V 18D8 19D9 20D10 21D11 22D12 23GND 24D13 25D14 26D15 27D16 28D17 29D18 30GND

35GND

36D22

37D23

38D24

40D26

41D27

43D29

31VDD32D19

33D20

34D21

39D25

42D28

44D30

GND

SIZ16B

106

105

45V

46GND

104 DA

47V

BCYST

103

102

48D31

49A31

HLDAK

ADRSERR

BE098BE197A196BE295BE394R/W93MRQ92ST1

101

100

50A30

51A29

52A28

54A26

55A25

53A27

56A24

57A23

58GND

GND

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

60V

ST0 HLDRQ SZRQ READY A2 A3 A4 A5 A6 A7 A8 GND A9 V

GND A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND

Cautions 1. Leave the IC1 pin open.

2. Connect the IC2 pin to GND.

Remark IC: Internally Connected

A22

µPD70732

★

• 120-pin plastic TQFP (Fine pitch) (14 x 14 mm) (Top View)

PD70732GC-25-9EV

109

108

107

106

105

104

GNDD4D3

103

102

101

100

V D19 D20 D21

GND

D22 D23 D24 D25 D26 D27 D28 D29 D30

GND

V D31 A31 A30 A29 A28 A27 A26 A25 A24 A23

GND

A22

GND

D18

D17

D16

D15

D14

D13

GND

D11

D10D8VDDV

D12

120

119

118

117

116

115

114

113

112

111

110

2 3 4 5 6 7 8

9 10 11 12 13 14

15 16

17 18 19 20 21 22 23 24 25 26 27 28 29

GNDD1D0

97A196

RESET

IC1

90 89

78 77 76 75 74

65 64 63 62 61

IC1 IC2 IC2 ICHEEN NMI INT INTV0 INTV1 INTV2 INTV3 BLOCK GND V

CLK GND SIZ16B DA V

BCYST HLDAK ADRSERR BE0 BE1

BE2 BE3 R/W MRQ ST1 GND

A2188A20

A1986A1885A1784A1683A1582A1481A1380A1279A11

GND

A10

GND73GND

A871A770A669A568A467A366A2

READY

SZRQ

HLDRQ

ST0

Cautions 1. VDD is power supply pin. All VDD pins should be connected to a +5V power supply (the

same power supply).

2. GND is ground pin. All GND pins should be connected to the same GND.

3. Leave the IC1 pin open.

4. Connect the IC2 pin to GND.

Remark IC: Internally Connected

• 176-pin ceramic PGA (Seam weld)

PD70732R-25

Bottom View Top View

Insertion guide pin

QPNML KJHGFEDCB A

15 14 13 12

11 10

µPD70732

9 8 7 6 5 4 3 2 1

BCDEFGHJKLMNPQ

No. 1 pin index

Remark The insertion guide pin is not included in the number of pins.

No. Signal No. Signal No. Signal No. Signal

A1 IC2 B3 GND C5 VDD D7 VDD A2 D12 B4 D11 C6 D8 D8 VDD A3 D13 B5 GND C7 VDD D9 GND A4 D10 B6 D7 C8 D4 D10 IC3 A5 GND B7 VDD C9 D2 D11 IC2 A6 D6 B8 D3 C10 IC3 D12 GND A7 IC2 B9 GND C11 VDD D13 INT A8 D5 B10 D0 C12 IC1 D14 INTV1

A9 IC2 B11 GND C13 IC2 D15 GND A10 D1 B12 IC1 C14 VDD E1 D27 A11 VDD B13 GND C15 NMI E2 D25 A12 RESET B14 IC1 D1 D23 E3 D21 A13 IC1 B15 ICHEEN D2 D22 E4 D19 A14 IC1 C1 VDD D3 D20 E12 IC3 A15 IC2 C2 VDD D4 GND E13 INTV0

B1 D17 C3 D16 D5 D15 E14 IC3

B2 D18 C4 D14 D6 D9 E15 IC1

No. Signal No. Signal No. Signal No. Signal

F1 VDD J4 VDD M7 VDD P4 A12 F2 D26 J12 IC2 M8 A5 P5 GND F3 D24 J13 IC2 M9 VDD P6 A8

F4 GND J14 IC1 M10 ST1 P7 GND F12 INTV2 J15 IC1 M11 A1 P8 A6 F13 INTV3 K1 IC2 M12 GND P9 GND F14 VDD K2 A27 M13 BCYST P10 SZRQ F15 GND K3 A25 M14 DA P11 GND

G1 D29 K4 A24 M15 SIZ16B P12 MRQ G2 D28 K12 GND N1 VDD P13 GND G3 IC2 K13 BLOCK N2 VDD P14 ADRSERR

G4 IC2 K14 VDD N3 A17 P15 BE0 G12 VDD K15 VDD N4 A15 Q1 IC2 G13 IC2 L1 A28 N5 VDD Q2 A13

µPD70732

G14 IC1 L2 A26 N6 A9 Q3 A14 G15 IC1 L3 A22 N7 VDD Q4 A11

H1 A31 L4 A20 N8 VDD Q5 GND

H2 D30 L12 HLDAK N9 A3 Q6 A7

H3 GND L13 VDD N10 HLDRQ Q7 IC2

H4 D31 L14 IC1 N11 VDD Q8 A4 H12 GND L15 IC1 N12 BE2 Q9 IC2 H13 CLK M1 GND N13 BE1 Q10 A2 H14 IC1 M2 A23 N14 VDD Q11 READY H15 IC2 M3 A21 N15 IC1 Q12 ST0

J1 A30 M4 GND P1 A18 Q13 BE3 J2 A29 M5 A16 P2 A19 Q14 R/W J3 IC2 M6 A10 P3 GND Q15 IC2

Cautions 1. Leave the IC1 pin open.

2. Connect the IC2 pin to GND.

3. Connect the IC3 pin to power supply.

Remark IC: Internally Connected

µPD70732

CONTENTS

1. PIN FUNCTIONS.............................................................................................................................. 8

1.1 Pin Function List................................................................................................................... 8

1.2 Pin I/O Circuits and Recommended Connection of Unused Pins................................. 10

★

2. REGISTER SET ............................................................................................................................... 12

2.1 Program Register Set ........................................................................................................... 13

2.2 System Register Set ............................................................................................................. 14

3. DATA TYPES ................................................................................................................................... 15

3.1 Data Types ............................................................................................................................. 15

3.1.1 Data type and addressing ......................................................................................................... 15

3.1.2 Integer ........................................................................................................................................ 16

3.1.3 Unsigned integer ....................................................................................................................... 16

3.1.4 Bit string ..................................................................................................................................... 16

3.1.5 Single-precision floating-point data .......................................................................................... 17

3.2 Data Alignment ...................................................................................................................... 17

4. ADDRESS SPACE........................................................................................................................... 18

5. BUS INTERFACE FUNCTION ......................................................................................................... 21

6. INTERRUPT AND EXCEPTION.......................................................................................................22

7. CACHE ............................................................................................................................................. 23

★

8. RESET .............................................................................................................................................. 24

9. INSTRUCTION SET ......................................................................................................................... 25

9.1 Instruction Format ................................................................................................................ 25

9.2 Instruction Mnemonic (in alphabetical order)................................................................... 27

10. ELECTRICAL SPECIFICATIONS ....................................................................................................37

10.1 Specifications When VDD = +5 V ± 10%.............................................................................. 38

10.2 Specifications When VDD = 2.7 to 3.6 V ............................................................................. 47

10.3 Specifications When VDD = 2.2 to 3.6 V ............................................................................. 51

11. PACKAGE DRAWINGS ................................................................................................................... 59

12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 62

★

1. PIN FUNCTIONS

1.1 Pin Function List

µPD70732

Bus hold

Name I/O Function status status

A31 to A1 3-state Address bus Hi-Z Hi-Z H (Address Bus) output

D31 to D0 3-state Bidirectional data bus Hi-Z Hi-Z Hi-Z (Data Bus) I/O

BE3 to BE0 3-state Indicates valid data bus when data is accessed Hi-Z Hi-Z H (Byte Enable) output

ST1, ST0 3-state Indicates type of bus cycle Hi-Z Hi-Z H (Status) output

DA 3-state Strobe signal for bus cycle Hi-Z Hi-Z H (Data Access) output

MRQ 3-state Indicates memory access Hi-Z Hi-Z H (Memory Request) output

R/W 3-state Distinguishes between read access and write access Hi-Z Hi-Z H (Read/Write) output

BCYST 3-state Indicates start of bus cycle Hi-Z Hi-Z H (Bus Cycle Start) output

status during

operation

Bus hold Bus idle

at reset at reset

Note

READY Input Extends bus cycle — — — (Ready)

HLDRQ Input Requests bus mastership — — — (Hold Request)

HLDAK Output Acknowledges HLDRQ L L H (Hold Acknowledge)

SZRQ Input Requests bus sizing — — — (Bus Sizing Request)

SIZ16B Input Fixes external data bus width to 16 bits — — — (Bus Size 16 Bit)

BLOCK Output Requests to inhibit use of bus L L L (Bus Lock)

ICHEEN Input Operates instruction cache — — — (Instruction Cache Enable)

INT Input Interrupt request — — — (Maskable Interrupt)

INTV3 to INTV0 Input Interrupt level — — — (Interrupt Level)

Note A1 pin is “H” in the 16-bit bus fixed mode; otherwise, it is “L”.

µPD70732

Bus hold

Name I/O Function status status

NMI Input Non-maskable interrupt request — — — (Non-Maskable Interrupt)

CLK Input CPU clock input — — —

RESET Input Resets internal status — — — (Reset)

ADRSERR Output Indicates that data alignment is illegal Not H H (Address Error) affected

DD — Positive power supply — — —

V (Power Supply)

GND — Ground potential (0 V) — — — (Ground)

IC1 — Internally connected (Leave this pin open.) — — — (Internally Connected 1)

IC2 — Internally connected (Ground this pin.) — — — (Internally Connected 2)

status during

operation

Bus hold Bus idle

at reset at reset

IC3 — Internally connected (Connect this pin to power supply.) — — — (Internally Connected 3)

★

1.2 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 1-1. Figure

1-1 shows the I/O circuit of each type.

Table 1-1. Pin I/O Circuit Types and Recommended Connection Method of Unused Pins

Pin I/O Circuit Type Recommended Connection Method D31 to D0 5 Open A31 to A1 4 BE3 to BE0 ST1, ST0 DA MRQ R/W BCYST READY 1 Connect to GND via resistor HLDRQ Connect to VDD via resistor HLDAK 4 Open SZRQ 1 Connect to VDD via resistor SIZ16B Connect to GND via resistor BLOCK 4 Open ICHEEN 1 Connect to VDD via resistor INT Connect to GND via resistor INTV3 to INTV0 Connect to VDD via resistor NMI CLK — RESET ADRSERR 4 Open IC1 — IC2 — Connect to GND IC3 — Connect to VDD

µPD70732

Figure 1-1. Pin I/O Circuit

µPD70732

Type 1

P-ch

N-ch

Type 4

data

output

disable

Push-pull output that can be output high impedance (both P-ch and N-ch are off).

P-ch

N-ch

OUT

Type 5

output

disable

enable

data

input

P-ch

N-ch

IN/OUT

★

2. REGISTER SET

The registers of the V810 can be classified into two types: general-purpose program register set and dedicated

system register set. All registers are 32 bits wide.

Program register sets System register sets

31 0 31 0

r0 Zero Register EIPC Exception/Interrupt PC r1 Reserved for Address Generation EIPSW Exception/Interrupt PSW r2 Handler Stack Pointer (hp) r3 Stack Pointer (sp) 31 0 r4 Global Pointer (gp) FEPC Fatal Error PC r5 Text Pointer (tp) FEPSW Fatal Error PSW r6 r7 31 0 r8 ECR Exception Cause Register r9 r10 31 0 r11 PSW Program Status Word r12 r13 31 0 r14 PIR Processor ID Register r15 r16 31 0 r17 TKCW Task Control Word r18 r19 31 0 r20 CHCW Cache Control Word r21 r22 31 0 r23 ADTRE Address Trap Register r24 r25 r26 String Destination Bit Offset r27 String Source Bit Offset r28 String Length r29 String Destination r30 String Source r31 Link Pointer (lp)

µPD70732

31 0

PC Program Counter

µPD70732

2.1 Program Register Set

The program register set is composed of general-purpose registers and a program counter.

(1) General-purpose registers

Thirty-two general-purpose registers, r0 to r31, are available. All these registers can be used as data registers or address registers. Of these registers, r0 and r26 through r30 are implicitly used by some instructions, and r1 through r5 and r31 are implicitly used by the assembler and C compiler. Therefore, when using these registers, it is necessary to take special care such as saving these registers’ contents to different areas before using these registers and restoring the contents after using them.

Table 2-1. Program Registers

Register Application Operation r0 Zero register Always holds zeros. r1 Register reserved for assembler Used as a working register to generate a 32-bit immediate data. r2 Handler stack pointer Used as the stack pointer for the handler. r3 Stack pointer Used to generate a stack frame at a function call. r4 Global pointer Used to access a global variable in the data area. r5 Text pointer Points the start address of the text area. r6 to r25 — Stores address or data variables. r26 String destination bit offset Used in a bit-string instruction execution. r27 String source bit offset r28 String length register r29 String destination address register r30 String address register

r31 Link pointer Stores the return address at execution of a JAL instruction.

(2) Program Counter

The program counter (PC) indicates the address of the instruction currently executed by the program. Bit 0 of the PC is fixed to 0, and execution cannot branch to an odd address. The contents of the PC are initialized to FFFFFFF0H at reset.

µPD70732

2.2 System Register Set

The system register set is composed of the following registers that perform operations such as CPU-status

control and interrupt information holding.

Table 2-2. System Register Number

Number Register Name Application Operation 0 EIPC Status saving registers The EIPC and EIPSW registers save the PC and PSW,

for exception/interrupt respectively, when an exception or interrupt occurs. Because in

the V810 the registers incorporated for this purpose are

1 EIPSW these registers only, save the contents of these registers by means

of programming if your application set can cause multiple interrupt

requests to be issued in the V810. 2 FEPC Status saving registers for The FEPC and FEPSW registers save the PC and PSW, 3 FEPSW 4 ECR Exception cause register This register, when an exception, maskable interrupt, or NMI

5 PSW Program status word This register, also called the program status word, is a set of flags

6 PIR Processor ID register This register identifies the CPU type number. 7 TKCW Task control word This register controls floating-point operations. 8 to 23 Reserved 24 CHCW Cache control word This register controls the on-chip instruction cache. 25 ADTRE Address trap register This register holds an address and is used for address trapping.

26 to 31 Reserved

NMI/duplexed exception respectively, when an NMI or duplexed exception occurs.

occurs, holds its cause. This register consists of 32 bits. Its higher

16 bits, called FECC, hold the exception code for an NMI or

duplexed exception, while the lower 16 bits, called EICC, hold the

exception code for an exception or maskable interrupt.

indicating the statuses of the CPU and program (instruction execution

results).

When the address in this register matches the PC value, the

execution jumps to a predefined address.

To read or write one of the registers shown above, specify a system register number with the system register

load (LDSR) or system register store (STSR) instruction.

µPD70732

3. DATA TYPES

3.1 Data Types

The data types supported by the V810 are as follows:

• Integer (8, 16, 32 bits)

• Unsigned integer (8, 16, 32 bits)

• Bit string

• Single-precision floating-point data (32 bits)

3.1.1 Data type and addressing

The V810 uses the little-endian data addressing. In this addressing, if a fixed-length data is located in a memory

area, the data must be either of the data types shown below.

(1) Byte

A byte is a consecutive 8-bit data whose first-bit address is aligned to a byte boundary. Each bit in a byte is numbered from 0 to 7: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 7. To access a byte, specify address A. (See diagram below.)

★

(2) Halfword

A halfword is a consecutive 16-bit (= 2 bytes) data whose first-bit address is aligned to a halfword boundary. Each bit in a halfword is numbered from 0 to 15: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 15. To access a halfword, specify the address A only (lowest bit must be 0).

15 8 7

A + 1

(3) Word/short real

A word, also called short real, is a consecutive 32-bit (= 4 bytes) data whose first-bit address is aligned to a word boundary. Each bit in a word is numbered from 0 to 31: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 31. To access a word or short real, specify the address A only (lower two bits must be 0).

31 24 23

A + 3

16 15

A + 2

A + 1

µPD70732

3.1.2 Integer

In the V810, all integers are expressed in the two’s-complement binary notation, and are composed of either 8 bits, 16 bits, or 32 bits. Regardless of the data length, bit 0 is the least significant bit, and higher-numbered bits express higher digits of the integer with the highest bit expressing its sign.

Data Length Range

Byte 8 bits –128 to +127 Halfword 16 bits –32768 to +32767 Word 32 bits –2147483648 to +2147483647

3.1.3 Unsigned integer

An unsigned integer is either zero or a positive integer unlike the integer explained in section 3.1.2 which can be negative as well as zero and positive. Unsigned integers are expressed in the binary notation in the same way as integers, and are either 8 bits, 16 bits, or 32 bits long. Regardless of the data length, the bit assignments are the same as in the case of integers except that unsigned integers do not include a sign bit; the highest bit is also a part of the integer.

Data Length Range

Byte 8 bits 0 to 255 Halfword 16 bits 0 to 65535 Word 32 bits 0 to 4294967295

3.1.4 Bit string

A bit string is a type of data whose bit length is variable from 0 to 2

– 1. To specify a bit-string data, define

the following three attributes.

• A : address of the string data’s first word (lower two bits must be 0.)

• B : in-word bit offset in the string data (0 to 31)

• M: bit length of the string data (0 to 2

– 1)

The above three attributes may vary depending on the bit-string data manipulation direction: upward or downward, as shown below. The former is the direction from lower addresses to higher addresses while the latter is the direction from higher to lower addresses.

M– 1 0

A + 8

Attribute Upward Downward First-word address (0s in bits 1 and 0) A A + 4 In-word bit offset (0 to 31) B D Bit length (0 to 2

– 1) M M

A + 4 A (Word boundary)

µPD70732

3.1.5 Single-precision floating-point data

This data type is 32 bits long and its bit allocation complies with the IEEE single format. A single-precision floating-point data consists of 1-bit mantissa sign bit, 8-bit exponent, and 23-bit mantissa. The exponent is offsetexpressed from the bias value – 127, and the mantissa is binary-expressed with the integer part omitted.

31 2330

s exp (8) mantissa (23)

3.2 Data Alignment

In the V810, a word data must be aligned to a word boundary (with the lowest two bits of the address fixed to 0s), and a halfword data to a halfword boundary (with the lowest bit of the address fixed to 0). If a data is not aligned as specified, the lowest one bit (in the case of word) or two bits (in the case of halfword) of its address will forcibly be masked with 0s when the data is accessed.

22 0

4. ADDRESS SPACE

★

The V810 supports 4 Gbytes of linear memory space and I/O space. The CPU outputs 32-bit addresses to

the memory and I/Os; therefore, the addresses are from 0 to 2

– 1.

Bit number 0 of each byte data is defined as the LSB (Least Significant Bit), and bit number 7 is the MSB (Most Significant Bit). Unless otherwise specified, the byte data at the lower address side of data consisting of two or more bytes is the LSB, and the byte data at the higher address side is the MSB (little endian).

Data consisting of 2 bytes is called a halfword, and data consisting of 4 bytes is called a word. The lower address of memory or I/O data of two or more bytes, here, is shown on the right, and the higher address is shown on the left, as follows:

µPD70732

Byte of address A

Halfword of address A

Word/short real of address A

A (address)

7015 8

A (address)A + 1

7015 823 1631 24

AA + 1A + 2A + 3

Figure 4-1 shows the memory map of the V810, and Figure 4-2 shows the I/O map.

Figure 4-1. Memory Map

FFFFFFFFH

µPD70732

FFFFFE00H

FFFFFDFFH

Interrupt handler table

General use

Note

00000000H

Note For the details, refer to Table 6-1 Exception Codes.

FFFFFFFFH

µPD70732

Figure 4-2. I/O Map

General use

00000000H

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