PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD4664312-X
64M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Description
The PD4664312-X is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) CMOS Mobile Specified RAM featuring Low Power Static RAM compatible function and pin configuration.
The PD4664312-X is fabricated with advanced CMOS technology using one-transistor memory cell. The PD4664312-X is packed in 93-pin TAPE FBGA.
• 4,194,304 words by 16 bits organization
• Fast access time: 65, 75 ns (MAX.)
• Fast page access time: 18, 25 ns (MAX.)
• Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)
• Low voltage operation: 2.7 to 3.1 V (-B65X)
2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X)
•Operating ambient temperature: TA = –25 to +85 °C
•Output Enable input for easy application
•Chip Enable input: /CS pin
•Standby Mode input: MODE pin
•Standby Mode1: Normal standby (Memory cell data hold valid)
•Standby Mode2: Density of memory cell data hold is variable
PD4664312 |
Access |
Operating supply |
Operating |
|
|
Supply current |
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
time |
voltage |
ambient |
At operating |
|
|
At standby A (MAX.) |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ns (MAX.) |
|
V |
temperature |
mA (MAX.) |
|
|
Density of data hold |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Chip |
|
I/O |
°C |
|
64M bits |
16M bits |
8M bits |
4M bits |
0M bit |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-B65X |
65 |
2.7 to 3.1 |
|
– |
–25 to +85 |
45 |
100 |
|
60 |
50 |
45 |
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
-BE75X Note |
75 |
2.7 to 3.1 |
|
1.65 to 2.1 |
|
40 |
|
|
|
|
|
|
Note Under development
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M15867EJ5V0DS00 (5th edition) Date Published August 2002 NS CP (K) Printed in Japan
The mark shows major revised points. |
© |
2001 |
|
PD4664312-X
Part number |
Package |
Access time |
Operating supply voltage |
Operating |
||
|
|
ns (MAX.) |
|
V |
temperature |
|
|
|
|
|
|
|
|
|
|
|
Chip |
|
I/O |
°C |
|
|
|
|
|
|
|
PD4664312F9-B65X-CR2 |
93-pin TAPE FBGA (12 x 9) |
65 |
2.7 to 3.1 |
|
– |
–25 to +85 |
|
|
|
|
|
|
|
PD4664312F9-BE75X-CR2 Note |
|
75 |
2.7 to 3.1 |
|
1.65 to 2.1 |
|
Note Under development
2 |
Preliminary Data Sheet M15867EJ5V0DS |
PD4664312-X
/xxx indicates active low signal.
93-pin TAPE FBGA (12 x 9)
[ PD4664312F9-B65X-CR2 ]
Top View |
Bottom View |
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P P N M L K J H G F E D C B A
Top View
|
A |
B |
C |
D |
E |
F |
G |
H |
J |
K |
L |
M |
N |
P |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
10 |
NC |
NC |
NC |
|
|
|
NC |
NC |
|
|
|
NC |
NC |
NC |
9 |
|
NC |
NC |
|
A15 |
A21 |
NC |
A16 |
NC |
GND |
|
NC |
NC |
|
8 |
|
|
NC |
A11 |
A12 |
A13 |
A14 |
NC |
I/O15 |
I/O7 |
I/O14 |
NC |
|
|
7 |
|
|
|
A8 |
A19 |
A9 |
A10 |
I/O6 |
I/O13 |
I/O12 |
I/O5 |
|
|
|
6 |
|
|
NC |
/WE |
MODE |
A20 |
NC |
NC |
I/O4 |
VCC |
NC |
NC |
|
|
5 |
|
|
NC |
NC |
NC |
NC |
NC |
NC |
I/O3 |
NC |
I/O11 |
NC |
|
|
4 |
|
|
|
/LB |
/UB |
A18 |
A17 |
I/O1 |
I/O9 |
I/O10 |
I/O2 |
|
|
|
3 |
|
|
NC |
A7 |
A6 |
A5 |
A4 |
GND |
/OE |
I/O0 |
I/O8 |
NC |
|
|
2 |
|
NC |
NC |
NC |
A3 |
A2 |
A1 |
A0 |
NC |
/CS |
|
NC |
NC |
|
1 |
NC |
NC |
NC |
|
|
|
NC |
NC |
|
|
|
NC |
NC |
NC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A0 to A21 |
: Address inputs |
/LB, /UB |
: Byte data select |
I/O0 to I/O15 |
: Data inputs / outputs |
VCC |
: Power supply |
/CS |
: Chip Select |
GND |
: Ground |
MODE |
: Standby mode |
NC Note |
: No Connection |
/WE |
: Write enable |
|
|
/OE |
: Output enable |
|
|
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
Preliminary Data Sheet M15867EJ5V0DS |
3 |
PD4664312-X
93-pin TAPE FBGA (12 x 9)
[ PD4664312F9-BE75X-CR2 ]
Top View |
Bottom View |
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P P N M L K J H G F E D C B A
Top View
|
A |
B |
C |
D |
E |
F |
G |
H |
J |
K |
L |
M |
N |
P |
10 |
NC |
NC |
NC |
|
|
|
NC |
NC |
|
|
|
NC |
NC |
NC |
9 |
|
NC |
NC |
|
A15 |
A21 |
NC |
A16 |
NC |
GND |
|
NC |
NC |
|
8 |
|
|
NC |
A11 |
A12 |
A13 |
A14 |
NC |
I/O15 |
I/O7 |
I/O14 |
NC |
|
|
7 |
|
|
|
A8 |
A19 |
A9 |
A10 |
I/O6 |
I/O13 |
I/O12 |
I/O5 |
|
|
|
6 |
|
|
NC |
/WE |
MODE |
A20 |
NC |
NC |
I/O4 |
VCC |
VCCQ |
NC |
|
|
5 |
|
|
NC |
NC |
NC |
NC |
NC |
NC |
I/O3 |
NC |
I/O11 |
NC |
|
|
4 |
|
|
|
/LB |
/UB |
A18 |
A17 |
I/O1 |
I/O9 |
I/O10 |
I/O2 |
|
|
|
3 |
|
|
NC |
A7 |
A6 |
A5 |
A4 |
GND |
/OE |
I/O0 |
I/O8 |
NC |
|
|
2 |
|
NC |
NC |
NC |
A3 |
A2 |
A1 |
A0 |
NC |
/CS |
|
NC |
NC |
|
1 |
NC |
NC |
NC |
|
|
|
NC |
NC |
|
|
|
NC |
NC |
NC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A0 to A21 |
: Address inputs |
/LB, /UB |
: Byte data select |
I/O0 to I/O15 |
: Data inputs / outputs |
VCC |
: Power supply |
/CS |
: Chip Select |
VCCQ |
: Input / Output power supply |
MODE |
: Standby mode |
GND |
: Ground |
/WE |
: Write enable |
NC Note |
: No Connection |
/OE |
: Output enable |
|
|
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
4 |
Preliminary Data Sheet M15867EJ5V0DS |
PD4664312-X
Standby mode control
VCC |
Refresh |
|
|
|
|
|
|
||
VCCQ |
control |
|
|
|
|
|
|
||
GND |
|
Memory cell array |
|
|
|
Refresh |
|
||
|
67,108,864 bits |
|
||
|
counter |
|
||
|
|
|
||
|
Row |
|
|
|
A0 |
decoder |
|
|
|
Address |
|
|
||
|
|
|
||
A21 |
buffer |
|
|
|
I/O0 to I/O7 |
|
Sense amplifier / |
|
|
Input data |
Switching circuit |
Output data |
||
|
||||
|
|
|||
I/O8 to I/O15 |
controller |
Column decoder |
controller |
|
|
|
|||
|
|
Address buffer |
|
|
/CS |
|
|
|
|
MODE |
|
|
|
|
/LB |
|
|
|
|
/UB |
|
|
|
|
/WE |
|
|
|
|
/OE |
|
|
|
Remark VCCQ is the input / output power supply for -BE75X.
Preliminary Data Sheet M15867EJ5V0DS |
5 |
PD4664312-X
Truth Table
/CS |
MODE |
/OE |
/WE |
/LB |
/UB |
Mode |
|
I/O |
Supply |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I/O0 to I/O7 |
|
I/O8 to I/O15 |
current |
|
|
|
|
|
|
|
|
|
|
|
H |
H |
× |
× |
× |
× |
Not selected (Standby Mode 1) |
High-Z |
|
High-Z |
ISB1 |
|
|
|
|
|
|
|
|
|
|
|
× |
H |
× |
× |
H |
H |
Not selected (Standby Mode 1) |
High-Z |
|
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
× |
L |
× |
× |
× |
× |
Not selected (Standby Mode 2) Note |
High-Z |
|
High-Z |
ISB2 |
L |
H |
H |
H |
× |
× |
Output disable |
High-Z |
|
High-Z |
ICCA |
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
L |
L |
Word read |
DOUT |
|
DOUT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
Lower byte read |
DOUT |
|
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
L |
Upper byte read |
High-Z |
|
DOUT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
L |
L |
L |
Word write |
DIN |
|
DIN |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
H |
Lower byte write |
DIN |
|
High-Z |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
L |
Upper byte write |
High-Z |
|
DIN |
|
|
|
|
|
|
|
|
|
|
|
|
Note MODE pin must be fixed to high level except Standby Mode 2. (refer to 2.3 Standby Mode Status Transition).
Remark ×: VIH or VIL, H: VIH, L: VIL
6 |
Preliminary Data Sheet M15867EJ5V0DS |
|
|
|
PD4664312-X |
|
|
|
|
|
|
CONTENTS |
|
1. |
Initialization .................................................................................................................................................................... |
8 |
|
2. |
Partial Refresh ............................................................................................................................................................... |
9 |
|
|
2.1 |
Standby Mode........................................................................................................................................................... |
9 |
|
2.2 |
Density Switching...................................................................................................................................................... |
9 |
|
2.3 |
Standby Mode Status Transition............................................................................................................................... |
9 |
|
2.4 |
Addresses for Which Partial Refresh Is Supported ................................................................................................ |
10 |
3. |
Page Read Operation .................................................................................................................................................. |
11 |
|
|
3.1 |
Features of Page Read Operation.......................................................................................................................... |
11 |
|
3.2 |
Page Length ........................................................................................................................................................... |
11 |
|
3.3 |
Page-Corresponding Addresses............................................................................................................................. |
11 |
|
3.4 |
Page Start Address................................................................................................................................................. |
11 |
|
3.5 |
Page Direction ........................................................................................................................................................ |
11 |
|
3.6 |
Interrupt during Page Read Operation.................................................................................................................... |
11 |
|
3.7 |
When page read is not used................................................................................................................................... |
11 |
4. |
Mode Register Settings................................................................................................................................................ |
12 |
|
|
4.1 |
Mode Register Setting Method ............................................................................................................................... |
12 |
|
4.2 |
Cautions for Setting Mode Register........................................................................................................................ |
13 |
5. |
Electrical Specifications ............................................................................................................................................... |
14 |
|
6. |
Timing Charts............................................................................................................................................................... |
20 |
|
7. |
Package Drawing......................................................................................................................................................... |
30 |
|
8. |
Recommended Soldering Conditions .......................................................................................................................... |
31 |
|
9. |
Revision History ........................................................................................................................................................... |
32 |
Preliminary Data Sheet M15867EJ5V0DS |
7 |
PD4664312-X
Initialize the PD4664312-X at power application using the following sequence to stabilize internal circuits.
(1)Following power application, make MODE high level after fixing MODE to low level for the period of tVHMH. Make /CS high level before making MODE high level.
(2)/CS and MODE are fixed to high level for the period of tMHCL.
Normal operation is possible after the completion of initialization.
Figure1-1. Initialization Timing Chart
Initialization |
Normal Operation |
|
|
/CS (Input)
tCHMH |
|
tMHCL |
tVHMH
MODE (Input)
VCC |
|
VCC (MIN.) |
|
Cautions 1. Make MODE low level when starting the power supply.
2. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (VCC (MIN.)).
8 |
Preliminary Data Sheet M15867EJ5V0DS |
PD4664312-X
In addition to the regular standby mode (Standby Mode 1) with a 64M bits density, Standby Mode 2, which performs partial refresh, is also provided.
In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit. The density for performing refresh can be set with the mode register. Once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application.
(For how to perform mode register settings, refer to section 4. Mode Register Settings.)
In Standby Mode 1, MODE and /CS are high level, or MODE, /LB and /UB are high level. In Standby Mode 2, MODE is low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 16M bits, 8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from Standby Mode 2.
For the timing charts, refer to Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart, Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart.
Preliminary Data Sheet M15867EJ5V0DS |
9 |
PD4664312-X
Figure 2-1. Standby Mode State Machine
|
|
Power On |
|
||||
|
|
|
|
Initialization |
|
||
|
|
|
|
|
|||
|
|
|
|
|
|
||
|
|
Initial State |
|
||||
|
|
|
|
/CS = VIL |
MODE = VIH |
||
|
|
|
|
||||
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
Active |
|
|||
|
|
|
|
|
|
MODE = VIL |
|
MODE = VIH, |
|
|
MODE = VIL |
|
|||
/CS = VIH or |
|
|
|
|
|
||
/LB, /UB = VIH |
/CS = VIL, |
|
|
|
|
||
|
|
|
/CS = VIL, |
|
|||
|
|
MODE = VIH |
|
MODE = VIH |
|
||
Standby |
|
MODE = VIL |
|
Standby Mode 2 |
|||
(16M bits / 8M bits |
|||||||
Mode 1 |
|
|
|
|
|||
|
|
|
|
/ 4M bits) |
|||
|
|
|
|
|
|
MODE = VIL
Standby Mode 2
(Data not held)
Data hold density |
Correspondence address |
|
|
16M bits |
000000H to 0FFFFFH |
|
|
8M bits |
000000H to 07FFFFH |
|
|
4M bits |
000000H to 03FFFFH |
|
|
10 |
Preliminary Data Sheet M15867EJ5V0DS |
PD4664312-X
Features |
8 Words Mode |
|
|
Page length |
8 words |
|
|
Page read-corresponding addresses |
A2, A1, A0 |
|
|
Page read start address |
Don’t care |
|
|
Page direction |
Don’t care |
|
|
Interrupt during page read operation |
Enabled Note |
Note An interrupt is output when /CS = H or in case A3 or a higher address changes.
8 words is supported as the page lengths.
The page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during page read operation.
Since random page read is supported, any address (A2, A1, A0) can be used as the page read start address.
Since random page read is possible, there is not restriction on the page direction.
When generating an interrupt during page read, either make /CS high level or change A3 and higher addresses.
Since random page read is supported, even when not using page read, random access is possible as usual.
Preliminary Data Sheet M15867EJ5V0DS |
11 |