NEC PD4664312-X Technical data

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD4664312-X

µµµµ

64M-BIT CMOS MOBILE SPECIFIED RAM

4M-WORD BY 16-BIT

EXTENDED TEMPERATURE OPERATION

Description

The µPD4664312-X is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) CMOS Mobile

Specified RAM featuring Low Power Static RAM compatible function and pin configuration.

The

PD4664312-X is fabricated with advanced CMOS technology using one-transistor memory cell.

µ

The

PD4664312-X is packed in 93-pin TAPE FBGA.

µ

Features

• 4,194,304 words by 16 bits organization

• Fast access time: 65, 75 ns (MAX.)

• Fast page access time: 18, 25 ns (MAX.)

• Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)

• Low voltage operation:2.7 to 3.1 V (-B65X)

2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X)

= –25 to +85 °C

• Operating ambient temperature: T

• Output Enable input for easy application

• Chip Enable input: /CS pin

• Standby Mode input: MODE pin

• Standby Mode1: Normal standby (Memory cell data hold valid)

• Standby Mode2: Density of memory cell data hold is variable

A

PD4664312 Access Operating supply Operating Supply current

µ

time voltage ambient At operating At standby µA (MAX.)

ns (MAX.) V temperature mA (MAX.) Density of data hold

Chip I/O °C 64M bits 16M bits 8M bits 4M bits 0M bit

-B65X 65 2.7 to 3.1 – –25 to [phone]

Note

-BE75X

Note Under development

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. M15867EJ5V0DS00 (5th edition)
Date Published August 2002 NS CP (K)
Printed in Japan

75 2.7 to 3.1 1.65 to 2.1 40

The mark  shows major revised points.

©

2001

PD4664312-X

µµµµ

Ordering Information

Part number Package Access time Operating supply voltage Operating

ns (MAX.) V temperature

Chip I/O °C

PD4664312F9-B65X-CR2 93-pin TAPE FBGA (12 x 9) 65 2.7 to 3.1 – –25 to +85

µ

PD4664312F9-BE75X-CR2

µ

Note Under development

Note

75 2.7 to 3.1 1.65 to 2.1

2

Preliminary Data Sheet M15867EJ5V0DS

Pin Configurations

/xxx indicates active low signal.

93-pin TAPE FBGA (12 x 9)

PD4664312F9-B65X-CR2 ]

[

µµµµ

PD4664312-X

µµµµ

10

Top View

P

BCDEFGHJKLM

A

ABCDEFGH

NC

NC

NC

NC

A15

A11

A8

/WE V

NC
/LB

A7 /OE

NC

NCNC

A12
A19

MODE A20

/UB

9
8
7
6
5
4
3
2
1

N

NC NCNC NC
A21 NC GND
A13

A18

A5 I/O8

A14
A10
NC
NC
A17

A4
A1A2

10

9
8
7
6
5
4
3
2
1

Top View

A16

NC

I/O6 I/O13A9

NC
NC

I/O1

GND

A0A3

NCNC

Bottom View

NP

M

LKJHGFEDCBA

NC

NC

/CS

I/O14

I/O5

NC

CC

I/O11NCNC

I/O2

I/O15

I/O4
I/O3
I/O9

NC

I/O7

I/O12

I/O10

I/O0A6

MKLJ

NC NC
NCNC

NCNC

NCNC
NCNC

NCNC
NCNC

N

NC

NC

NCNC

P

NC

NC

A0 to A21 : Address inputs

I/O0 to I/O15 : Data inputs / outputs

/CS : Chip Select

MODE : Standby mode

/LB, /UB : Byte data select

V

CC

GND : Ground

Note

NC

/WE : W rite enable

/OE : Output enable

Note Some signals can be applied because this pin is not internally connected.

Remarks Refer to Package Drawing for the index mark.

Preliminary Data Sheet M15867EJ5V0DS

: Power supply

: No Connection

3

93-pin TAPE FBGA (12 x 9)

PD4664312F9-BE75X-CR2 ]

[

µµµµ

PD4664312-X

µµµµ

10

Top View

P

BCDEFGHJKLM

A

ABCDEFGH

NC

NC

NC

NC

A15

A11

A8

/WE V

NC
/LB

A7 /OE

NC

NCNC

A12
A19

MODE A20

/UB

9
8
7
6
5
4
3
2
1

N

NC NCNC NC
A21 NC GND
A13

A18

A5 I/O8

A14
A10
NC
NC
A17

A4
A1A2

10

9
8
7
6
5
4
3
2
1

Top View

A16

NC

I/O6 I/O13A9

NC
NC

I/O1

GND

A0A3

NCNC

Bottom View

NP

M

LKJHGFEDCBA

NC

NC

/CS

I/O14

I/O5

CC

CC

Q

V
I/O11NCNC

I/O2

I/O15

I/O4
I/O3
I/O9

NC

I/O7

I/O12

I/O10

I/O0A6

MKLJ

NC NC
NCNC

NCNC

NCNC
NCNC

NCNC
NCNC

N

NC

NC

NCNC

P

NC

NC

A0 to A21 : Address inputs

I/O0 to I/O15 : Data inputs / outputs

/CS : Chip Select

MODE : Standby mode

/WE : W rite enable

/LB, /UB : Byte data select

V

CC

V

Q : Input / Output power supply

CC

GND : Ground

Note

NC

/OE : Output enable

Note Some signals can be applied because this pin is not internally connected.

Remarks Refer to Package Drawing for the index mark.

4

Preliminary Data Sheet M15867EJ5V0DS

: Power supply

: No Connection

Block Diagram

V

CC

VCCQ

Refresh

control

Standby mode control

PD4664312-X

µµµµ

GND

A0

A21

I/O0 to I/O7

I/O8 to I/O15

/CS

Refresh
counter

Address

buffer

Row

decoder

Input data

controller

Memory cell array

67,108,864 bits

Sense amplifier /

Switching circuit

Column decoder

Address buffer

Output data

controller

MODE

/LB

/UB

/WE

/OE

Remark VCCQ is the input / output power supply for -BE75X.

Preliminary Data Sheet M15867EJ5V0DS

5

PD4664312-X

µµµµ

Truth Table

/CS MODE /OE /WE /LB /UB Mode I/O Supply

I/O0 to I/O7 I/O8 to I/O15 current

HH×××× Not selected (Standby Mode 1) High-Z High-Z I

× H ××H H Not selected (Standby Mode 1) High-Z High-Z

× L ×××× Not selected (Standby Mode 2)

Note

High-Z High-Z I

LHHH×× Output disable High-Z High-Z I

L H L L Word read D

L H Lower byte read D

OUT

OUT

H L Upper byte read High-Z D

HLLL Word write D

L H Lower byte write D

IN

IN

H L Upper byte write High-Z D

OUT

D

High-Z

OUT

IN

D

High-Z

IN

Note MODE pin must be fixed to high level except Standby Mode 2. (refer to 2.3 Standby Mode Status Transition).

Remark ×: VIH

or VIL, H: VIH, L: V

IL

SB1

SB2

CCA

6

Preliminary Data Sheet M15867EJ5V0DS

PD4664312-X

µµµµ

CONTENTS

1. Initialization .................................................................................................................................................................... 8

2. Partial Refresh ............................................................................................................................................................... 9

2.1 Standby Mode........................................................................................................................................................... 9

2.2 Density Switching......................................................................................................................................................9

2.3 Standby Mode Status Transition............................................................................................................................... 9

2.4 Addresses for Which Partial Refresh Is Supported ................................................................................................ 10

3. Page Read Operation .................................................................................................................................................. 11

3.1 Features of Page Read Operation.......................................................................................................................... 11

3.2 Page Length ...........................................................................................................................................................11

3.3 Page-Corresponding Addresses............................................................................................................................. 11

3.4 Page Start Address................................................................................................................................................. 11

3.5 Page Direction ........................................................................................................................................................ 11

3.6 Interrupt during Page Read Operation.................................................................................................................... 11

3.7 When page read is not used................................................................................................................................... 11

4. Mode Register Settings................................................................................................................................................ 12

4.1 Mode Register Setting Method ............................................................................................................................... 12

4.2 Cautions for Setting Mode Register........................................................................................................................ 13

5. Electrical Specifications ............................................................................................................................................... 14

6. Timing Charts............................................................................................................................................................... 20

7. Package Drawing......................................................................................................................................................... 30

8. Recommended Soldering Conditions ..........................................................................................................................31

9. Revision History ........................................................................................................................................................... 32

Preliminary Data Sheet M15867EJ5V0DS

7

PD4664312-X

µµµµ

1. Initialization

Initialize the µPD4664312-X at power application using the following sequence to stabilize internal circuits.

(1) Following power application, make MODE high level after fixing MODE to low level for the period of t

/CS high level before making MODE high level.

(2) /CS and MODE are fixed to high level for the period of t

Normal operation is possible after the completion of initialization.

Figure1-1. Initialization Timing Chart

MHCL

.

VHMH

. Make

Initialization

/CS (Input)

t

CHMH

t

VHMH

MODE (Input)

V

CC

VCC (MIN.)

Cautions 1. Make MODE low level when starting the power supply.

2. t

is specified from when the power supply voltage reaches the prescribed minimum value (V

VHMH

(MIN.)).

t

MHCL

Normal Operation

CC

8

Preliminary Data Sheet M15867EJ5V0DS

PD4664312-X

µµµµ

2. Partial Refresh

2.1 Standby Mode

In addition to the regular standby mode (Standby Mode 1) with a 64M bits density, Standby Mode 2, which performs

partial refresh, is also provided.

2.2 Density Switching

In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit.

The density for performing refresh can be set with the mode register. Once the refresh density has been set in the

mode register, these settings are retained until they are set again, while applying the power supply. However, the mode

register setting will become undefined if the power is turned off, so set the mode register again after power application.

(For how to perform mode register settings, refer to section 4. Mode Register Settings.)

2.3 Standby Mode Status Transition

In Standby Mode 1, MODE and /CS are high level, or MODE, /LB and /UB are high level. In Standby Mode 2, MODE is

low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after

applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 16M bits,

8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from

Standby Mode 2.

For the timing charts, refer to Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit

Timing Chart, Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart.

Preliminary Data Sheet M15867EJ5V0DS

9

Figure 2-1. Standby Mode State Machine

Power On

Initialization

Initial State

PD4664312-X

µµµµ

IL

MODE = VIH,
/CS = VIH or
/LB, /UB = VIH

Standby

Mode 1

/CS = VIL,
MODE = VIH

/CS = V

Active

/CS = VIL,
MODE = V

MODE = VIL

MODE = VIL

2.4 Addresses for Which Partial Refresh Is Supported

MODE = VIH

MODE = VIL

MODE = VIL

IH

Standby Mode 2

(16M bits / 8M bits

/ 4M bits)

Standby Mode 2

(Data not held)

Data hold density Correspondence address

16M bits 000000H to 0FFFFFH

8M bits 000000H to 07FFFFH

4M bits 000000H to 03FFFFH

10

Preliminary Data Sheet M15867EJ5V0DS

3. Page Read Operation

3.1 Features of Page Read Operation

Features 8 Words Mode

Page length 8 words

Page read-corresponding addresses A2, A1, A0

Page read start address Don’t care

Page direction Don’t care

Interrupt during page read operation Enabled

Note An interrupt is output when /CS = H or in case A3 or a higher address changes.

3.2 Page Length

8 words is supported as the page lengths.

Note

PD4664312-X

µµµµ

3.3 Page-Corresponding Addresses

The page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during page read

operation.

3.4 Page Start Address

Since random page read is supported, any address (A2, A1, A0) can be used as the page read start address.

3.5 Page Direction

Since random page read is possible, there is not restriction on the page direction.

3.6 Interrupt during Page Read Operation

When generating an interrupt during page read, either make /CS high level or change A3 and higher addresses.

3.7 When page read is not used

Since random page read is supported, even when not using page read, random access is possible as usual.

Preliminary Data Sheet M15867EJ5V0DS

11