μ
查询UPD43256BGU-70L-A供应商
DATA SHEET
MOS INTEGRATED CIRCUIT
PD43256B
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
Description
The μPD43256B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM.
Battery backup is available. And A and B versions are wide voltage operations.
The μPD43256B is packed in 28-pin PLASTIC DIP, 28-pin PLASTIC SOP and 28-pin PLASTIC TSOP (I) (8 x 13.4 mm).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Low VCC data retention: 2.0 V (MIN.)
• /OE input for easy application
Part number Access time Operating supply Operating ambient Supply current
ns (MAX.) voltage temperature At operating At standby At data retention
μ
V °C mA (MAX.)
μ
PD43256B-xxL
μ
PD43256B-xxLL
μ
PD43256B-Axx
μ
PD43256B-Bxx
Notes 1. TA ≤ 40 °C, VCC = 3.0 V
2. Access time: 85 ns (MAX.) (V
Note2
70, 85 4.5 to 5.5 0 to 70 45 50 3
Note2
85, 100
, 120
100, 120, 150 2.7 to 5.5
Note2
3.0 to 5.5
CC = 4.5 to 5.5 V)
15 2
A (MAX.) μA (MAX.)
Note1
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M10770EJEV0DS00 (14th edition)
Date Published June 2006 NS CP (K)
Printed in Japan
1990, 1993, 1994
μ
PD43256B
Ordering Information (1/2)
Part number Package Access time Operating supply Operating ambient Remark
ns (MAX.) voltage temperature
V °C
μ
PD43256BCZ-70L
μ
PD43256BCZ-85L
μ
PD43256BCZ-70LL
μ
PD43256BCZ-85LL
μ
PD43256BGU-70L
μ
PD43256BGU-85L
μ
PD43256BGU-70LL
μ
PD43256BGU-85LL
μ
PD43256BGU-A85
μ
PD43256BGU-A10
μ
PD43256BGU-A12
28-pin PLASTIC DIP 70 4.5 to 5.5 0 to 70 L version
(15.24 mm (600)) 85
70 LL version
85
28-pin PLASTIC SOP 70 L version
(11.43 mm (450)) 85
70 LL version
85
85 3.0 to 5.5 A version
100
120
μ
PD43256BGU-B10
μ
PD43256BGU-B12
μ
PD43256BGW-70LL-9JL
μ
PD43256BGW-85LL-9JL
μ
PD43256BGW-A85-9JL
μ
PD43256BGW-A10-9JL
μ
PD43256BGW-A12-9JL
μ
PD43256BGW-B10-9JL
μ
PD43256BGW-B12-9JL
μ
PD43256BGW-B15-9JL
μ
PD43256BGW-70LL-9KL
μ
PD43256BGW-85LL-9KL
μ
PD43256BGW-A85-9KL
μ
PD43256BGW-A10-9KL
μ
PD43256BGW-A12-9KL
μ
PD43256BGW-B10-9KL
μ
PD43256BGW-B12-9KL
100 2.7 to 5.5 B version
120
28-pin PLASTIC TSOP (I) 70 4.5 to 5.5 LL version
(8x13.4) (Normal bent) 85
85 3.0 to 5.5 A version
100
120
100 2.7 to 5.5 B version
120
150
28-pin PLASTIC TSOP (I) 70 4.5 to 5.5 LL version
(8x13.4) (Reverse bent) 85
85 3.0 to 5.5 A version
100
120
100 2.7 to 5.5 B version
120
μ
PD43256BGW-B15-9KL
2
150
Data Sheet M10770EJEV0DS
μ
PD43256B
(2/2)
Part number Package Access time Operating supply Operating ambient Remark
ns (MAX.) voltage temperature
V °C
μ
PD43256BGU-70L-A
μ
PD43256BGU-85L-A
μ
PD43256BGU-70LL-A
μ
PD43256BGU-85LL-A
μ
PD43256BGU-A85-A
μ
PD43256BGU-A10-A
μ
PD43256BGU-A12-A
μ
PD43256BGU-B10-A
μ
PD43256BGU-B12-A
μ
PD43256BGW-70LL-9JL-A
μ
PD43256BGW-85LL-9JL-A
28-pin PLASTIC SOP 70 4.5 to 5.5 0 to 70 L version
(11.43 mm (450)) 85
70 LL version
85
85 3.0 to 5.5 A version
100
120
100 2.7 to 5.5 B version
120
28-pin PLASTIC TSOP (I) 70 4.5 to 5.5 LL version
(8x13.4) (Normal bent) 85
μ
PD43256BGW-A85-9JL-A
μ
PD43256BGW-A10-9JL-A
μ
PD43256BGW-A12-9JL-A
μ
PD43256BGW-B10-9JL-A
μ
PD43256BGW-B12-9JL-A
μ
PD43256BGW-B15-9JL-A
μ
PD43256BGW-70LL-9KL-A
μ
PD43256BGW-85LL-9KL-A
μ
PD43256BGW-A85-9KL-A
μ
PD43256BGW-A10-9KL-A
μ
PD43256BGW-A12-9KL-A
μ
PD43256BGW-B10-9KL-A
μ
PD43256BGW-B12-9KL-A
μ
PD43256BGW-B15-9KL-A
Remark Products with -A at the end of the part number are lead-free products.
28-pin PLASTIC TSOP (I) 70 4.5 to 5.5 LL version
(8x13.4) (Reverse bent) 85
85 3.0 to 5.5 A version
100
120
100 2.7 to 5.5 B version
120
150
85 3.0 to 5.5 A version
100
120
100 2.7 to 5.5 B version
120
150
Data Sheet M10770EJEV0DS
3
μ
Pin Configurations (Marking Side)
/xxx indicates active low signal.
28-pin PLASTIC DIP (15.24 mm (600))
[
μ
PD43256BCZ-xxL ]
[ μPD43256BCZ-xxLL ]
PD43256B
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A0 - A14 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CS : Chip Select
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M10770EJEV0DS
μ
PD43256B
28-pin PLASTIC SOP (11.43 mm (450))
[
μ
PD43256BGU-xxL ]
[ μPD43256BGU-xxLL ]
[ μPD43256BGU-Axx ]
[ μPD43256BGU-Bxx ]
[ μPD43256BGU-xxL-A ]
[ μPD43256BGU-xxLL-A ]
[ μPD43256BGU-Axx-A ]
[ μPD43256BGU-Bxx-A ]
A14
1
28
V
CC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
25
24
23
22
21
20
19
18
17
16
15
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A0 - A14 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CS : Chip Select
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M10770EJEV0DS
5
μ
PD43256B
28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
[
μ
PD43256BGW-xxLL-9JL ]
[ μPD43256BGW-Axx-9JL ]
[ μPD43256BGW-Bxx-9JL ]
[ μPD43256BGW-xxLL-9JL-A ]
[ μPD43256BGW-Axx-9JL-A ]
[ μPD43256BGW-Bxx-9JL-A ]
/OE
A11
A9
A8
A13
/WE
V
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
CC
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
[
μ
PD43256BGW-xxLL-9KL ]
[ μPD43256BGW-Axx-9KL ]
[ μPD43256BGW-Bxx-9KL ]
[ μPD43256BGW-xxLL-9KL-A ]
[ μPD43256BGW-Axx-9KL-A ]
[ μPD43256BGW-Bxx-9KL-A ]
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
/OE
A11
A9
A8
A13
/WE
V
A14
A12
A7
A6
A5
A4
A3
CC
A0 - A14 : Address inputs /OE : Output Enable
I/O1 - I/O8 : Data inputs / outputs VCC : Power supply
/CS : Chip Select GND : Ground
/WE : Write Enable
Remark Refer to Package Drawings for the 1-pin index mark.
6
Data Sheet M10770EJEV0DS
μ
Block Diagram
PD43256B
I/O1
I/O8
/CS
A0
A14
Address
buffer
Row
decoder
Input data
controller
Memory cell array
262,144 bits
Sense amplifier /
Switching circuit
Column decoder
Address buffer
Output data
controller
/OE
/WE
CC
V
GND
Truth Table
/CS /OE /WE Mode I/O Supply current
H × × Not selected High impedance ISB
L H H Output disable ICCA
L × L Write DIN
L L H Read DOUT
Remark × : VIH or VIL
Data Sheet M10770EJEV0DS
7
μ
PD43256B
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply voltage VCC –0.5
Input / Output voltage VT –0.5
Operating ambient temperature TA 0 to 70 °C
Storage temperature Tstg –55 to +125 °C
Note –3.0 V (MIN.) (Pulse width : 50 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Note
to +7.0 V
Note
to VCC + 0.5 V
μ
Parameter Symbol Condition
MIN. MAX. MIN. MAX. MIN. MAX.
Supply voltage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V
High level input voltage VIH 2.2 VCC+0.5 2.2 VCC+0.5 2.2 VCC+0.5 V
Low level input voltage VIL –0.3
Operating ambient temperature TA 0 70 0 70 0 70
PD43256B-xxL
μ
PD43256B-xxLL
Note
+0.8 –0.3
μ
PD43256B-Axx
Note
+0.5 –0.3
μ
PD43256B-Bxx
Note
+0.5 V
Unit
°C
Note –3.0 V (MIN.) (Pulse width: 50 ns)
Capacitance (T
Input capacitance CIN VIN = 0 V 5 pF
Input / Output capacitance CI/O VI/O = 0 V 8 pF
A = 25 °C, f = 1 MHz)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
8
Data Sheet M10770EJEV0DS
μ
PD43256B
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
μ
Parameter Symbol Test condition
MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0
I/O leakage current ILO VI/O = 0 V to VCC, /OE = VIH or –1.0 +1.0 –1.0 +1.0
/CS = VIH or /WE = VIL
Operating supply current ICCA1 /CS = VIL, Minimum cycle time, II/O = 0 mA 45 45 mA
ICCA2 /CS = VIL, II/O = 0 mA 10 10
PD43256B-xxL
μ
PD43256B-xxLL
Unit
μ
μ
A
A
ICCA3
Standby supply current ISB /CS = VIH 3 3 mA
ISB1
High level output voltage VOH1 IOH = –1.0 mA 2.4 2.4 V
VOH2 IOH = –0.1 mA
Low level output voltage VOL IOL = 2.1 mA 0.4 0.4 V
/CS ≤ 0.2 V, Cycle = 1 MHz,
I
I/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
/CS ≥ V
CC − 0.2 V
10 10
1.0 50 0.5 15
VCC–0.5
VCC–0.5
μ
A
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M10770EJEV0DS
9
μ
PD43256B
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
μ
Parameter Symbol Test condition
PD43256B-Axx
MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0
I/O leakage current ILO VI/O = 0 V to VCC, /OE = VIH or –1.0 +1.0 –1.0 +1.0
/CS = VIH or /WE = VIL
μ
Operating supply current ICCA1 /CS = VIL,
Minimum cycle time,
II/O = 0 mA
PD43256B-Axx
μ
PD43256B-Bxx
V
CC ≤ 3.3 V
45 – mA
– 45
– 20
ICCA2 /CS = VIL, II/O = 0 mA 10 10
V
CC ≤ 3.3 V
– 5
μ
PD43256B-Bxx
Unit
μ
A
μ
A
ICCA3
/CS ≤ 0.2 V, Cycle = 1 MHz, I
V
IL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V
I/O = 0 mA,
10 10
– 5
Standby supply current ISB /CS = VIH 3 3 mA
V
/CS ≥ V
ISB1
CC − 0.2 V
I
High level output voltage VOH1
OH = –1.0 mA, VCC ≥ 4.5 V
CC ≤ 3.3 V
V
CC ≤ 3.3 V
– 2
μ
0.5 15 0.5 15
– 0.5 10
A
2.4 2.4 V
IOH = –0.5 mA, VCC < 4.5 V 2.4 2.4
VOH2 IOH = –0.02 mA
I
Low level output voltage VOL
OL = 2.1 mA, VCC ≥ 4.5 V
VCC–0.1
0.4 0.4 V
VCC–0.1
IOL = 1.0 mA, VCC < 4.5 V 0.4 0.4
VOL1 IOL = 0.02 mA 0.1 0.1
Remarks 1. VIN : Input voltage
V
I/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
10
Data Sheet M10770EJEV0DS
μ
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[
μ
PD43256B-70L, μPD43256B-85L, μPD43256B-70LL, μPD43256B-85LL ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.2 V
0.8 V
1.5 V
Test points
1.5 V
Output Waveform
Test points1.5 V 1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1 Figure 2
(t
AA, tACS, tOE, tOH) (tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
+5 V
+5 V
PD43256B
1.8 kΩ
5 pF
C
L
I/O (Output)
990 Ω
1.8 kΩ
100 pF
C
L
I/O (Output)
990 Ω
Remark C
L includes capacitance of the probe and jig, and stray capacitance.
[ μPD43256B-A85, μPD43256B-A10, μPD43256B-A12, μPD43256B-B10, μPD43256B-B12, μPD43256B-B15 ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.2 V
0.5 V
1.5 V
Test points
1.5 V
Output Waveform
Test points1.5 V 1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
tAA, tACS, tOE, tOH tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW
1TTL + 100 pF 1TTL + 5 pF
Data Sheet M10770EJEV0DS
11
μ
PD43256B
Read Cycle (1/2)
V
Parameter Symbol
μ
MIN. MAX. MIN. MAX.
Read cycle time tRC 70 85 ns
Address access time tAA 70 85 ns Note
/CS access time tACS 70 85 ns
/OE access time tOE 35 40 ns
Output hold from address change tOH 10 10 ns
/CS to output in low impedance tCLZ 10 10 ns
/OE to output in low impedance tOLZ 5 5 ns
/CS to output in high impedance tCHZ 30 30 ns
/OE to output in high impedance tOHZ 30 30 ns
PD43256B-70
μ
μ
CC ≥ 4.5 V
μ
PD43256B-85
PD43256B-A85/A10/A12
PD43256B-B10/B12/B15
Unit Condition
Note See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
V
Parameter Symbol
μ
PD43256B
-A85
10
10
5
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC 85 100 120 100 120 150 ns
Address access
time
/CS access time tACS 85 100 120 100 120 150 ns
/OE access time tOE 50 60 60 60 60 70 ns
Output hold from
address change
/CS to output in
low impedance
/OE to output in
low impedance
/CS to output in
high impedance
/OE to output in
high impedance
tAA
tOH
tCLZ
tOLZ
tCHZ
tOHZ
CC ≥ 3.0 V VCC ≥ 2.7 V
85
35
35
PD43256B
μ
-A10
10
10
5
100
35
35
PD43256B
μ
-A12
10
10
5
120
40
40
PD43256B
μ
-B10
10
10
5
100
35
35
PD43256B
μ
-B12
120
10
10
5
40
40
PD43256B
μ
-B15
150 ns Note
10
10
5
50 ns
50 ns
Unit Con-
dition
ns
ns
ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
12
Data Sheet M10770EJEV0DS
μ
Read Cycle Timing Chart
PD43256B
Address (Input)
t
AA
/CS (Input)
t
ACS
t
CLZ
/OE (Input)
t
OLZ
I/O (Output)
High impedance
Remark In read cycle, /WE should be fixed to high level.
t
RC
t
OH
t
CHZ
t
t
OE
OHZ
Data out
Data Sheet M10770EJEV0DS
13
μ
PD43256B
Write Cycle (1/2)
V
Parameter Symbol
μ
MIN. MAX. MIN. MAX.
Write cycle time tWC 70 85 ns
/CS to end of write tCW 50 70 ns
Address valid to end of write tAW 50 70 ns
Write pulse width tWP 55 60 ns
Data valid to end of write tDW 30 35 ns
Data hold time tDH 0 0 ns
Address setup time tAS 0 0 ns
Write recovery time tWR 0 0 ns
/WE to output in high impedance tWHZ 30 30 ns Note
Output active from end of write tOW 10 10 ns
PD43256B-70
μ
μ
CC ≥ 4.5 V
μ
PD43256B-85
PD43256B-A85/A10/A12
PD43256B-B10/B12/B15
Unit Condition
Note See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
V
Parameter Symbol
μ
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC 85 100 120 100 120 150 ns
/CS to end of write tCW 70 70 90 70 90 100 ns
Address valid to
end of write
Write pulse width tWP 60 60 80 60 80 90 ns
Data valid to end
of write
Data hold time tDH 0 0 0 0 0 0
Address setup
Write recovery
/WE to output in
high impedance
Output active
from end of write
tAW
tDW
t
t
tWHZ
tOW
PD43256B
AS 0 0 0 0 0 0 ns
WR 0 0 0 0 0 0 ns
-A85
70
60
10
CC ≥ 3.0 V VCC ≥ 2.7 V
30
PD43256B
μ
-A10
70
60
10
35
PD43256B
μ
-A12
90
70
10
40
PD43256B
μ
-B10
70
60
10
35
PD43256B
μ
-B12
90
70
10
40
PD43256B
μ
-B15
100
80
10
Con-
Unit
dition
50 ns Note
ns
ns
ns
ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
14
Data Sheet M10770EJEV0DS
μ
Write Cycle Timing Chart 1 (/WE Controlled)
Address (Input)
/CS (Input)
t
AS
/WE (Input)
t
WHZ
PD43256B
t
WC
t
CW
t
AW
t
WP
t
DW
t
WR
t
OW
t
DH
I/O (Input / Output)
Indefinite data out
High
impedance
Data in Indefinite data out
High
impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O
pins will remain high impedance state.
Data Sheet M10770EJEV0DS
15
μ
Write Cycle Timing Chart 2 (/CS Controlled)
Address (Input)
t
AS
/CS (Input)
/WE (Input)
PD43256B
t
WC
t
CW
t
AW
t
WP
t
DW
t
WR
t
DH
I/O (Input)
High impedance
Data in
High
impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
16
Data Sheet M10770EJEV0DS
μ
PD43256B
Low VCC Data Retention Characteristics (TA = 0 to 70 °C)
μ
Parameter Symbol Test Condition
PD43256B-xxL
μ
μ
MIN. TYP. MAX. MIN. TYP. MAX.
/CS ≥ V
Data retention supply voltage VCCDR
Data retention supply current ICCDR
Chip deselection
to data retention mode
tCDR
CC − 0.2 V
V
CC = 3.0 V, /CS ≥ VCC − 0.2 V
2.0 5.5 2.0 5.5 V
Note1
0.5 20
0
Operation recovery time tR 5 5 ms
Notes 1. 3 μA (TA ≤ 40 °C)
2. 2 μA (TA ≤ 40 °C), 1 μA (TA ≤ 25 °C)
Data Retention Timing Chart
μ
PD43256B-xxLL
PD43256B-Axx
PD43256B-Bxx
0.5 7
0
Note2
Unit
μ
A
ns
t
4.5 V
V
Note
CDR
CC
Data retention mode t
/CS
V
IH
(MIN.)
V
CCDR
(MIN.)
/CS ≥ VCC – 0.2 V
V
IL
(MAX.)
GND
Note A version : 3.0 V, B version : 2.7 V
Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state.
R
Data Sheet M10770EJEV0DS
17
μ
Package Drawings
28-PIN PLASTIC DIP (15.24 mm (600))
PD43256B
28
1
15
14
A
J
I
F
D
M
N
C
B
M
K
L
R
H
G
NOTES
1.
Each lead centerline is located within 0.25 mm
of its true position (T.P.) at maximum material condition.
Item "K" to center of leads when formed parallel.
2.
ITEM MILLIMETERS
A
38.10 MAX.
B
2.54 MAX.
C
2.54 (T.P.)
D 0.50±0.10
F
1.2 MIN.
G
3.6±0.3
H
0.51 MIN.
I
4.31 MAX.
J
5.72 MAX.
K
15.24 (T.P.)
L
13.2
M 0.25
N
R 0 - 15°
+0.10
−0.05
0.25
P28C-100-600A1-2
18
Data Sheet M10770EJEV0DS
μ
28-PIN PLASTIC SOP (11.43 mm (450))
28 15
114
A
F
detail of lead end
P
PD43256B
G
C
DM
M
SN
B
E
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
H
I
J
S
L
K
ITEM MILLIMETERS
+0.6
18.0
A
B
C
D 0.42
E
F
G
H
I 8.4±0.1
J
K 0.22±0.05
L 0.7± 0.2
M
N
P3°
−0.05
1.27 MAX.
1.27 (T.P.)
+0.08
−0.07
0.2±0.1
2.95 MAX.
2.55±0.1
11.8±0.3
1.7±0.2
0.12
0.10
+7°
−3°
P28GU-50-450A-4
Data Sheet M10770EJEV0DS
19
μ
28-PIN PLASTIC TSOP(I) (8x13.4)
PD43256B
14
1
28
detail of lead end
S
R
15
Q
P
I
J
A
G
S
H
L
SN
DM
C
M
B
K
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
ITEM MILLIMETERS
A 8.0± 0.1
B 0.6 MAX.
C 0.55 (T.P.)
D 0.22
G 1.0
H 12.4±0.2
I 11.8±0.1
J 0.8±0.2
K 0.145
L 0.5±0.1
M 0.08
N 0.10
P 13.4± 0.2
Q 0.1±0.05
R3°
S 1.2 MAX.
+0.08
−0.07
+0.025
−0.015
+7°
−3°
P28GW-55-9JL-2
20
Data Sheet M10770EJEV0DS
μ
28-PIN PLASTIC TSOP(I) (8x13.4)
PD43256B
14
1
28
detail of lead end
Q
R
15
S
K
H
S
L
D
M
MN
C
B
S
G
I
J
A
P
NOTE
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
ITEM MILLIMETERS
A 8.0± 0.1
B 0.6 MAX.
C 0.55 (T.P.)
D 0.22
G 1.0
H 12.4±0.2
I 11.8±0.1
J 0.8±0.2
K 0.145
L 0.5±0.1
M 0.08
N 0.10
P 13.4± 0.2
Q 0.1±0.05
R3°
S 1.2 MAX.
+0.08
−0.07
+0.025
−0.015
+7°
−3°
P28GW-55-9KL-2
Data Sheet M10770EJEV0DS
21
μ
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD43256B.
Types of Surface Mount Device
μ
PD43256BGU-xxL : 28-pin PLASTIC SOP (11.43 mm (450))
μ
PD43256BGU-xxLL : 28-pin PLASTIC SOP (11.43 mm (450))
μ
PD43256BGU-Axx : 28-pin PLASTIC SOP (11.43 mm (450))
μ
PD43256BGU-Bxx : 28-pin PLASTIC SOP (11.43 mm (450))
μ
PD43256BGW-xxLL-9JL : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μ
PD43256BGW-xxLL-9KL : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μ
PD43256BGW-Axx-9JL : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μ
PD43256BGW-Axx-9KL : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μ
PD43256BGW-Bxx-9JL : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μ
PD43256BGW-Bxx-9KL : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μ
PD43256BGU-xxL-A : 28-pin PLASTIC SOP (11.43 mm (450))
μ
PD43256BGU-xxLL-A : 28-pin PLASTIC SOP (11.43 mm (450))
μ
PD43256BGU-Axx-A : 28-pin PLASTIC SOP (11.43 mm (450))
μ
PD43256BGU-Bxx-A : 28-pin PLASTIC SOP (11.43 mm (450))
μ
PD43256BGW-xxLL-9JL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μ
PD43256BGW-xxLL-9KL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μ
PD43256BGW-Axx-9JL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μ
PD43256BGW-Axx-9KL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μ
PD43256BGW-Bxx-9JL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μ
PD43256BGW-Bxx-9KL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
Types of Through Hole Mount Device
PD43256B
μ
PD43256BCZ-xxL : 28-pin PLASTIC DIP (15.24 mm (600))
μ
PD43256BCZ-xxLL : 28-pin PLASTIC DIP (15.24 mm (600))
Soldering process Soldering conditions
Wave soldering (only to leads)
Flow time : 10 seconds or below
Partial heating method
Time : 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
22
Data Sheet M10770EJEV0DS
Solder temperature : 260 °C or below,
Terminal temperature : 300 °C or below,
μ
PD43256B
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition → This edition)
edition edition
14th edition/ p.1 p.1 Deletion − Description of Version X and P has been deleted.
Jun. 2006
Data Sheet M10770EJEV0DS
23
μ
[ MEMO ]
PD43256B
24
Data Sheet M10770EJEV0DS
μ
[ MEMO ]
PD43256B
Data Sheet M10770EJEV0DS
25
μ
[ MEMO ]
PD43256B
26
Data Sheet M10770EJEV0DS
μ
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
IL
CMOS device stays in the area between V
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
(MAX) and VIH (MIN) due to noise, etc., the device may
IL
(MAX) and
DD
PD43256B
or GND
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet M10770EJEV0DS
27
μ
PD43256B
•
The information in this document is current as of June, 2006. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
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No part of this document may be copied or reproduced in any form or by any means without the prior
•
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M8E 02. 11-1
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