NEC PD23C32340, PD23C32380 Technical data

查询UPD23C32340供应商

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD23C32340, 23C32380

32M-BIT MASK-PROGRAMMABLE ROM

4M-WORD BY 8-BIT (BYTE MODE) / 2M-WORD BY 16-BIT (WORD MODE)

PAGE ACCESS MODE

Description

The µPD23C32340 and µPD23C32380 are 33,554,432 bits mask-programmable ROM. The word organization is

selectable (BYTE mode : 4,194,304 words by 8 bits, WORD mode : 2,097,152 words by 16 bits).

The active levels of OE (Output Enable Input) can be selected with mask-option.

The

PD23C32340 and µPD23C32380 are packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA.

Features

• Pin compatible with NOR Flash Memory

• Word organization

4,194,304 words by 8 bits (BYTE mode)

2,097,152 words by 16 bits (WORD mode)

• Page access mode

BYTE mode : 8 byte random page access (µPD23C32340)

16 byte random page access (

WORD mode :4 word random page access (

8 word random page access (

= 2.7 V to 3.6 V

• Operating supply voltage : V

Operating supply Access time / Power supply current (Active mode) Standby current

voltage Page access time mA (MAX.) (CMOS level input)

3.0 V ± 0.3 V 100 / 25 40 55 30

3.3 V ± 0.3 V 90 / 25

ns (MAX.)

PD23C32380)

PD23C32340)

PD23C32380)

PD23C32340

PD23C32380

A (MAX.)

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

Document No. M15711EJ2V0DS00 (2nd edition) Date Published February 2003 NS CP(K) Printed in Japan

The mark shows major revised points.

2001

µµµµ

PD23C32340, 23C32380

Ordering Information

Part Number Package

PD23C32340GZ-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)

PD23C32340F9-xxx-BC3 48-pin TAPE FBGA (8 x 6)

PD23C32380GZ-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)

PD23C32380F9-xxx-BC3 48-pin TAPE FBGA (8 x 6)

(xxx : ROM code suffix No.)

Data Sheet M15711EJ2V0DS

Pin Configurations

/xxx indicates active low signal.

µµµµ

PD23C32340, 23C32380

48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)

µµµµ

PD23C32340GZ-xxx-MJH ]

[

µµµµ

PD23C32380GZ-xxx-MJH ]

[

Marking Side

A15

A14

A13

A12

A11

A10

A19

A20

A18

A17

A16

WORD, /BYTE

GND

O15, A−1

O14

O13

O12

O11

O10

/OE or OE or DC

GND

/CE

A0 to A20 : Address inputs

O0 to O7, O8 to O14 : Data outputs

O15, A–1 : Data output 15 (WORD mode),

LSB Address input (BYTE mode)

WORD, /BYTE : Mode select

/CE : Chip Enable

/OE or OE : Output Enable

: Supply voltage

GND : Ground

Note

: No Connection

DC : Don’t Care

Note Some signals can be applied because this pin is not connected to the inside of the chip.

Remark Refer to Package Drawings for the 1-pin index mark.

Data Sheet M15711EJ2V0DS

µµµµ

PD23C32340, 23C32380

48-pin TAPE FBGA (8 x 6)

µµµµ

PD23C32340F9-xxx-BC3 ]

[

µµµµ

[

PD23C32380F9-xxx-BC3 ]

Top View Bottom View

ABCDEFGHHGFEDCBA

ABCDEFGH HGFEDCBA

6 A13 A12 A14 A15 A16 WORD, O15, GND 6 GND O15, W ORD, A16 A15 A14 A12 A13

/BYTE A–1 A–1 /BYTE

5 A9 A8 A10 A11 O7 O14 O13 O6 5 O6 O13 O14 O7 A11 A10 A8 A9

4NCNCNCA19O5O12VCCO4 4 O4 V

3 NC NC A18 A20 O2 O10 O11 O3 3 O3 O11 O10 O2 A20 A18 NC NC

2 A7 A17 A6 A5 O0 O8 O9 O1 2 O1 O9 O8 O0 A5 A6 A17 A7

1 A3 A4 A2 A1 A0 /CE /OE or GND 1 GND /OE or /CE A0 A1 A2 A4 A3

OE OE

O12 O5 A19 NC NC NC

A0 to A20 : Address inputs

O0 to O7, O8 to O14 : Data outputs

O15, A–1 : Data output 15 (WORD mode),

LSB Address input (BYTE mode)

WORD, /BYTE : Mode select

/CE : Chip Enable

/OE or OE : Output Enable

: Supply voltage

GND : Ground

Note

: No Connection

DC : Don’t Care

Note Some signals can be applied because this pin is not connected to the inside of the chip.

Remark Refer to Package Drawings for the index mark.

Data Sheet M15711EJ2V0DS

µµµµ

PD23C32340, 23C32380

Input / Output Pin Functions

Pin name Input / Output Function

WORD, /BYTE Input The pin for switching WORD mode and BYTE mode.

High level : WORD mode (2M-word by 16-bit)

Low level : BYTE mode (4M-word by 8-bit)

A0 to A20

(Address inputs)

O0 to O7, O8 to O14

(Data outputs)

O15, A−1

(Data output 15,

LSB Address input)

/CE

(Chip Enable)

/OE or OE or DC

(Output Enable, Don't care)

GND − Ground

NC − Not internally connected. (The signal can be connected.)

Input Address input pins.

A0 to A20 are used differently in the WORD mode and the BYTE mode.

WORD mode (2M-word by 16-bit)

A0 to A20 are used as 21 bits address signals.

BYTE mode (4M-word by 8-bit)

A0 to A20 are used as the upper 21 bits of total 22 bits of address signal.

(The least significant bit (A−1) is combined to O15.)

Output Data output pins.

O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.

WORD mode (2M-word by 16-bit)

The lower 15 bits of 16 bits data outputs to O0 to O14.

(The most significant bit (O15) combined to A−1.)

BYTE mode (4M-word by 8-bit)

8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.

Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.

WORD mode (2M-word by 16-bit)

The most significant output data bus (O15).

BYTE mode (4M-word by 8-bit)

The least significant address bus (A−1).

Input Chip activating signal.

When the OE is active, output states are following.

High level : High-Z

Low level : Data out

Input Output enable signal. The active level of OE is mask option. The active level of OE

can be selected from high active, low active and Don’t care at order.

− Supply voltage

Data Sheet M15711EJ2V0DS

Block Diagram

µµµµ

PD23C32340, 23C32380

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

Y-Decoder

Address Input Buffer

X-Decoder

O10O9

O3 O4

Output Buffer

Y-Selector

Memory Cell Matrix

2,097,152 words by 16 bits /

4,194,304 words by 8 bits

O12O11

O5 O6 O7

O14O13

O15, A−1

Logic/InputInput Buffer

WORD, /BYTE

/OE or OE or DC

/CE

Data Sheet M15711EJ2V0DS

+ 14 hidden pages