NEC PD23C32340, PD23C32380 Technical data
UPD23C32340 |
DATA SHEET |
MOS INTEGRATED CIRCUIT
PD23C32340, 23C32380
32M-BIT MASK-PROGRAMMABLE ROM
4M-WORD BY 8-BIT (BYTE MODE) / 2M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Description
The PD23C32340 and PD23C32380 are 33,554,432 bits mask-programmable ROM. The word organization is selectable (BYTE mode : 4,194,304 words by 8 bits, WORD mode : 2,097,152 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The PD23C32340 and PD23C32380 are packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA.
Features
•Pin compatible with NOR Flash Memory
•Word organization
4,194,304 words by 8 bits (BYTE mode)
2,097,152 words by 16 bits (WORD mode)
• Page access mode
BYTE mode : 8 byte random page access ( PD23C32340) 16 byte random page access ( PD23C32380)
WORD mode : 4 word random page access ( PD23C32340) 8 word random page access ( PD23C32380)
• Operating supply voltage : VCC = 2.7 V to 3.6 V
Operating supply |
Access time / |
Power supply current (Active mode) |
Standby current |
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voltage |
Page access time |
mA (MAX.) |
(CMOS level input) |
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VCC |
ns (MAX.) |
PD23C32340 |
PD23C32380 |
A (MAX.) |
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3.0 V ± 0.3 V |
100 / 25 |
40 |
55 |
30 |
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3.3 V ± 0.3 V |
90 / 25 |
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. M15711EJ2V0DS00 (2nd edition) Date Published February 2003 NS CP(K) Printed in Japan
The mark 
shows major revised points.
2001
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PD23C32340, 23C32380 |
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Ordering Information |
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Part Number |
Package |
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PD23C32340GZ-xxx-MJH |
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) |
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PD23C32340F9-xxx-BC3 |
48-pin TAPE FBGA (8 x 6) |
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PD23C32380GZ-xxx-MJH |
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) |
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PD23C32380F9-xxx-BC3 |
48-pin TAPE FBGA (8 x 6) |
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(xxx : ROM code suffix No.) |
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2 |
Data Sheet M15711EJ2V0DS |
PD23C32340, 23C32380
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
[ PD23C32340GZ-xxx-MJH ] [ PD23C32380GZ-xxx-MJH ]
Marking Side
A15 |
1 |
48 |
A16 |
A14 |
2 |
47 |
WORD, /BYTE |
A13 |
3 |
46 |
GND |
A12 |
4 |
45 |
O15, A−1 |
A11 |
5 |
44 |
O7 |
A10 |
6 |
43 |
O14 |
A9 |
7 |
42 |
O6 |
A8 |
8 |
41 |
O13 |
A19 |
9 |
40 |
O5 |
A20 |
10 |
39 |
O12 |
NC |
11 |
38 |
O4 |
NC |
12 |
37 |
VCC |
NC |
13 |
36 |
O11 |
NC |
14 |
35 |
O3 |
NC |
15 |
34 |
O10 |
A18 |
16 |
33 |
O2 |
A17 |
17 |
32 |
O9 |
A7 |
18 |
31 |
O1 |
A6 |
19 |
30 |
O8 |
A5 |
20 |
29 |
O0 |
A4 |
21 |
28 |
/OE or OE or DC |
A3 |
22 |
27 |
GND |
A2 |
23 |
26 |
/CE |
A1 |
24 |
25 |
A0 |
A0 to A20 |
: Address inputs |
O0 to O7, O8 to O14 : Data outputs |
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O15, A–1 |
: Data output 15 (WORD mode), |
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LSB Address input (BYTE mode) |
WORD, /BYTE |
: Mode select |
/CE |
: Chip Enable |
/OE or OE |
: Output Enable |
VCC |
: Supply voltage |
GND |
: Ground |
NC Note |
: No Connection |
DC |
: Don’t Care |
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15711EJ2V0DS |
3 |
PD23C32340, 23C32380
48-pin TAPE FBGA (8 x 6)
[ PD23C32340F9-xxx-BC3 ]
[ PD23C32380F9-xxx-BC3 ]
Top View |
Bottom View |
6
5
4
3
2
1
A B C D E F G H H G F E D C B A
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A |
B |
C |
D |
E |
F |
G |
H |
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6 |
A13 |
A12 |
A14 |
A15 |
A16 |
WORD, |
O15, |
GND |
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/BYTE |
A–1 |
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5 |
A9 |
A8 |
A10 |
A11 |
O7 |
O14 |
O13 |
O6 |
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4 |
NC |
NC |
NC |
A19 |
O5 |
O12 |
VCC |
O4 |
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3 |
NC |
NC |
A18 |
A20 |
O2 |
O10 |
O11 |
O3 |
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2 |
A7 |
A17 |
A6 |
A5 |
O0 |
O8 |
O9 |
O1 |
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1 |
A3 |
A4 |
A2 |
A1 |
A0 |
/CE |
/OE or |
GND |
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OE |
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H |
G |
F |
E |
D |
C |
B |
A |
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6 |
GND |
O15, |
WORD, |
A16 |
A15 |
A14 |
A12 |
A13 |
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A–1 |
/BYTE |
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5 |
O6 |
O13 |
O14 |
O7 |
A11 |
A10 |
A8 |
A9 |
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4 |
O4 |
VCC |
O12 |
O5 |
A19 |
NC |
NC |
NC |
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3 |
O3 |
O11 |
O10 |
O2 |
A20 |
A18 |
NC |
NC |
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2 |
O1 |
O9 |
O8 |
O0 |
A5 |
A6 |
A17 |
A7 |
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1 |
GND |
/OE or |
/CE |
A0 |
A1 |
A2 |
A4 |
A3 |
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OE |
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A0 to A20 |
: Address inputs |
O0 to O7, O8 to O14 : Data outputs |
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O15, A–1 |
: Data output 15 (WORD mode), |
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LSB Address input (BYTE mode) |
WORD, /BYTE |
: Mode select |
/CE |
: Chip Enable |
/OE or OE |
: Output Enable |
VCC |
: Supply voltage |
GND |
: Ground |
NC Note |
: No Connection |
DC |
: Don’t Care |
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the index mark.
4 |
Data Sheet M15711EJ2V0DS |
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PD23C32340, 23C32380 |
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Input / Output Pin Functions |
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Pin name |
Input / Output |
Function |
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WORD, /BYTE |
Input |
The pin for switching WORD mode and BYTE mode. |
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High level : WORD mode (2M-word by 16-bit) |
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Low level : BYTE mode (4M-word by 8-bit) |
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A0 to A20 |
Input |
Address input pins. |
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(Address inputs) |
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A0 to A20 are used differently in the WORD mode and the BYTE mode. |
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WORD mode (2M-word by 16-bit) |
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A0 to A20 are used as 21 bits address signals. |
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BYTE mode (4M-word by 8-bit) |
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A0 to A20 are used as the upper 21 bits of total 22 bits of address signal. |
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(The least significant bit (A−1) is combined to O15.) |
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O0 to O7, O8 to O14 |
Output |
Data output pins. |
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(Data outputs) |
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O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode. |
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WORD mode (2M-word by 16-bit) |
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The lower 15 bits of 16 bits data outputs to O0 to O14. |
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(The most significant bit (O15) combined to A−1.) |
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BYTE mode (4M-word by 8-bit) |
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8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance. |
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O15, A−1 |
Output, Input |
O15, A−1 are used differently in the WORD mode and the BYTE mode. |
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(Data output 15, |
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WORD mode (2M-word by 16-bit) |
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LSB Address input) |
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The most significant output data bus (O15). |
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BYTE mode (4M-word by 8-bit) |
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The least significant address bus (A−1). |
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/CE |
Input |
Chip activating signal. |
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(Chip Enable) |
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When the OE is active, output states are following. |
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High level : High-Z |
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Low level : Data out |
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/OE or OE or DC |
Input |
Output enable signal. The active level of OE is mask option. The active level of OE |
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(Output Enable, Don't care) |
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can be selected from high active, low active and Don’t care at order. |
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VCC |
− |
Supply voltage |
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GND |
− |
Ground |
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NC |
− |
Not internally connected. (The signal can be connected.) |
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Data Sheet M15711EJ2V0DS |
5 |
Block Diagram
A0 |
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Decoder- |
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A1 |
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A2 |
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A3 |
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Y |
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A4 |
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A5 |
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A6 |
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A7 |
Buffer |
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A8 |
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A9 |
Input |
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A10 |
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Address |
Decoder- |
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A13 |
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A11 |
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A12 |
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A14 |
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X |
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A15 |
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A16
A17
A18
A19 
A20 
PD23C32340, 23C32380
O8 |
O9 |
O10 |
O11 |
O12 |
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O13 |
O14 O15, A−1 |
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O0 |
O1 |
O2 |
O3 |
O4 |
O5 |
O6 |
O7 |
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Output Buffer |
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Logic/Input |
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WORD, /BYTE |
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Y-Selector
/OE or OE or DC
Memory Cell Matrix |
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2,097,152 words by 16 bits / |
BufferInput |
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4,194,304 words by 8 bits |
/CE |
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6 |
Data Sheet M15711EJ2V0DS |
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