DATA SHEET
MOS INTEGRATED CIRCUIT
µµµµ
PD23C32000AL
32M-BIT MASK-PROGRAMMABLE ROM
4M-WORD BY 8-BIT (BYTE MODE) / 2M-WORD BY 16-BIT (WORD MODE)
Description
The µPD23C32000AL is a 33,554,432 bits mask-programmable ROM. The word organization is selectable (BYTE
mode : 4,194,304 words by 8 bits, WORD mode : 2,097,152 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
PD23C32000AL is packed in 48-pin PLASTIC TSOP (I) and 44-pin PLASTIC SOP.
µ
Features
• Word organization
4,194,304 words by 8 bits (BYTE mode)
2,097,152 words by 16 bits (WORD mode)
= 2.7 V to 3.6 V
• Operating supply voltage : V
Operating supply voltage Access time Power supply current (Active mode) Standby current (CMOS level input)
V
CC
3.0 V ± 0.3 V 100 30 30
3.3 V ± 0.3 V 90
CC
ns (MAX.) mA (MAX.)
A (MAX.)
µ
Ordering Information
Part Number Package
PD23C32000ALGY-xxx-MJH 48-pin PLASTIC TSOP (I) (12 x 18) (Normal bent)
µ
PD23C32000ALGY-xxx-MKH 48-pin PLASTIC TSOP (I) (12 x 18) (Reverse bent)
µ
PD23C32000ALGX-xxx 44-pin PLASTIC SOP (15.24 mm (600))
µ
(xxx : ROM code suffix No.)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15773EJ4V0DS00 (4th edition)
Date Published February 2003 NS CP(K)
Printed in Japan
The mark shows major revised points.
2001
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12 x 18) (Normal bent)
[
µµµµ
PD23C32000ALGY-xxx-MJH ]
Marking Side
µµµµ
PD23C32000AL
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A19
NC
A20
A18
A17
/CE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
V
CC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
GND
A0 to A20 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
V
CC
: Supply voltage
GND : Ground
Note
NC
: No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
2
Data Sheet M15773EJ4V0DS
48-pin PLASTIC TSOP (I) (12 x 18) (Reverse bent)
µµµµ
[
PD23C32000ALGY-xxx-MKH ]
Marking Side
µµµµ
PD23C32000AL
GND
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
VCC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
GND
48
47
46
45
44
43
42
41
40
39
CC
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
A0 to A20 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
V
CC
: Supply voltage
GND : Ground
NC
Note
: No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15773EJ4V0DS
3
44-pin PLASTIC SOP (15.24 mm (600))
µµµµ
[
PD23C32000ALGX-xxx ]
Marking Side
µµµµ
PD23C32000AL
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
GND
/OE or OE or DC
O0
O8
O1
O9
O2
O10
O3
O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
WORD, /BYTE
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
A0 to A20 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
V
CC
: Supply voltage
GND : Ground
Note
NC
: No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M15773EJ4V0DS
Input / Output Pin Functions
Pin name Input / Output Function
WORD, /BYTE Input The pin for switching WORD mode and BYTE mode.
High level : WORD mode (2M-word by 16-bit)
Low level : BYTE mode (4M-word by 8-bit)
A0 to A20
(Address inputs)
O0 to O7, O8 to O14
(Data outputs)
O15, A−1
(Data output 15,
LSB Address input)
/CE
(Chip Enable)
/OE or OE or DC
(Output Enable, Don't care)
V
CC
GND − Ground
NC − Not internally connected. (The signal can be connected.)
Input Address input pins.
A0 to A20 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
A0 to A20 are used as 21 bits address signals.
BYTE mode (4M-word by 8-bit)
A0 to A20 are used as the upper 21 bits of total 22 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
Output Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (4M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
The most significant output data bus (O15).
BYTE mode (4M-word by 8-bit)
The least significant address bus (A−1).
Input Chip activating signal.
When the OE is active, output states are following.
High level : High-Z
Low level : Data out
Input Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low active and Don’t care at order.
− Supply voltage
µµµµ
PD23C32000AL
Data Sheet M15773EJ4V0DS
5
Block Diagram
µµµµ
PD23C32000AL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
Y-Decoder
Address Input Buffer
X-Decoder
O0
O8
O10O9
O2
O1
O3 O4
Output Buffer
Y-Selector
Memory Cell Matrix
2,097,152 words by 16 bits /
4,194,304 words by 8 bits
O12O11
O5 O6 O7
O14O13
O15, A−1
Logic/InputInput Buffer
WORD, /BYTE
/OE or OE or DC
/CE
6
Data Sheet M15773EJ4V0DS
µµµµ
PD23C32000AL
Mask Option
The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected
from among " 0 " " 1 " " x " shown in the table below.
Option /OE or OE or DC OE active level
0/OE L
1OE H
x DC Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE /OE Mode Output state
L L Active Data out
H High-Z
H H or L Standby High-Z
Operation mode (Option : 1)
/CE OE Mode Output state
L L Active High-Z
H Data out
H H or L Standby High-Z
Operation mode (Option : x)
/CE DC Mode Output state
L H or L Active Data out
H H or L Standby High-Z
Remark L : Low level input
H : High level input
Data Sheet M15773EJ4V0DS
7
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
µµµµ
PD23C32000AL
Supply voltage V
Input voltage V
Output voltage V
Operating ambient temperature T
Storage temperature T
CC
I
O
A
stg
–0.3 to +4.6 V
–0.3 to VCC+0.3 V
–0.3 to VCC+0.3 V
–10 to +70 °C
–65 to +150 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (T
Input capacitance CIf = 1 MHz 10 pF
Output capacitance C
A
= 25 °C)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
O
12 pF
DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
High level input voltage V
Low level input voltage V
High level output voltage V
Low level output voltage V
Input leakage current I
Output leakage current I
Power supply current I
Standby current I
IH
V
= 3.0 V ± 0.3 V –0.3 +0.5 V
IL
OHIOH
OLIOL
LI
LO
CC1
CC3
CC
V
= 3.3 V ± 0.3 V –0.3 +0.8
CC
= –100 µA2.4V
= 2.1 mA 0.4 V
V
= 0 V to V
I
V
= 0 V to VCC, Chip deselected –10 +10
O
/CE = V
I
= 0 mA V
O
CC
(Active mode), V
IL
= 3.0 V ± 0.3 V 30 mA
CC
= 3.3 V ± 0.3 V 30
CC
/CE = VCC – 0.2 V (Standby mode) 30
2.0 VCC + 0.3 V
–10 +10
A
µ
A
µ
A
µ
8
Data Sheet M15773EJ4V0DS
AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter Symbol Test condition VCC = 3.0 V ± 0.3 V VCC = 3.3 V ± 0.3 V Unit
µµµµ
PD23C32000AL
MIN. TYP. MAX. MIN. TYP. MAX.
Address access time t
Address skew time t
Chip enable access time t
Output enable access time t
Output hold time t
Output disable time t
WORD, /BYTE access time t
t
indicates the following three types of time depending on the condition.
Note
SKEW
ACC
SKEW Note 10 10 ns
CE
OE
OH
DF
WB
1) When switching /CE from high level to low level, t
00ns
0 25 0 25 ns
is the time from the /CE low level input point until the
SKEW
100 90 ns
100 90 ns
25 25 ns
100 90 ns
next address is determined.
2) When switching /CE from low level to high level, t
is the time from the address change start point to the
SKEW
/CE high level input point.
3) When /CE is fixed to low level, t
is the time from the address change start point until the next address is
SKEW
determined.
Since specs are defined for t
only when /CE is active, t
SKEW
is not subject to limitations when /CE is switched
SKEW
from high level to low level following address determination, or when the address is changed after /CE is switched
from low level to high level.
Remark
t
is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
DF
high impedance state output.
AC Test Conditions
Input waveform (Rise
Output waveform
/
Fall time
≤
≤
≤≤
5 ns)
Test points1.4 V 1.4 V
Test points1.4 V 1.4 V
Output load
1TTL + 100 pF
Data Sheet M15773EJ4V0DS
9
PD23C32000AL
µµµµ
Cautions on power application
To ensure normal operation, always apply power using /CE following the procedure shown below.
1) Input a high level to /CE during and after power application.
2) Hold the high level input to /CE for 200 ns or longer (wait time).
3) Start normal operation after the wait time has elapsed.
Power Application Timing Chart 1 (When /CE is made high at power application)
Wait time
/CE (Input)
200 ns or longer
CC
V
Power Application Timing Chart 2 (When /CE is made high after power application)
Wait time
/CE (Input)
200 ns or longer
CC
V
Caution Other signals can be either high or low during the wait time.
Normal operation
Normal operation
10
Data Sheet M15773EJ4V0DS
Read Cycle Timing Chart
t
SKEW
t
SKEW
µµµµ
PD23C32000AL
t
SKEW
A0 to A20,
A−1
/OE or OE
O0 to O7,
O8 to O15
Note1
Note3
/CE
(Input)
(Input)
(Input)
(Input)
t
ACC
t
CE
t
OE
Notes 1. During WORD mode, A–1 is O15.
is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
DF
2. t
high impedance state output.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
WORD, /BYTE Switch Timing Chart
t
ACC
Note2
t
DF
t
OH
Data out Data out Data out
High-ZHigh-Z
t
ACC
t
OH
t
OH
Note2
t
DF
A–1 (Input)
WORD, /BYTE
O0 to O7 (Output)
O8 to O15 (Output)
(Input)
High-Z
t
OH
t
ACC
Data Out Data Out
t
DF
Data Out Data Out
Remark Chip Enable (/CE) and Output Enable (/OE or OE) : Active.
Data Out
High-Z
High-Z
t
OH
t
WB
Data Sheet M15773EJ4V0DS
11
Package Drawings
48-PIN PLASTIC TSOP(I) (12x18)
µµµµ
PD23C32000AL
1
24
48
25
P
I
J
S
K
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
SN
detail of lead end
F
G
E
C
D
R
Q
L
S
A
B
M
M
ITEM MILLIMETERS
A
12.0±0.1
B
0.45 MAX.
C
0.5 (T.P.)
D 0.22± 0.05
E
0.1±0.05
1.2 MAX.
F
1.0±0.05G
I
16.4±0.1
J 0.8± 0.2
K
0.145±0.05
L 0.5
0.10M
0.10N
P 18.0±0.2
Q3°
S 0.60±0.15
+5°
−3°
0.25R
S48GY-50-MJH1-1
12
Data Sheet M15773EJ4V0DS
48-PIN PLASTIC TSOP(I) (12x18)
1
48
detail of lead end
E
µµµµ
PD23C32000AL
S
24
K
SN
I
P
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
25
Q
L
R
G
F
D
S
J
M
M
C
B
A
ITEM MILLIMETERS
A
12.0±0.1
B
0.45 MAX.
C
0.5 (T.P.)
D 0.22± 0.05
E
0.1±0.05
1.2 MAX.
F
1.0±0.05G
I
16.4±0.1
J 0.8± 0.2
0.145±0.05
K
L 0.5
0.10M
0.10N
P 18.0±0.2
Q3°
S 0.60±0.15
+5°
−3°
0.25R
S48GY-50-MKH1-1
Data Sheet M15773EJ4V0DS
13
44-PIN PLASTIC SOP (15.24 mm (600))
44 23
122
A
F
G
µµµµ
PD23C32000AL
detail of lead end
P
H
I
J
S
C
DM
M
SN
B
E
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
L
K
ITEM MILLIMETERS
A 27.83
B
C
D 0.42
E 0.15± 0.1
F 3.0 MAX.
G 2.7±0.05
H
I
J
K 0.22
L 0.8±0.2
M
N
P3°
+0.4
−0.05
0.78 MAX.
1.27 (T.P.)
+0.08
−0.07
16.04±0.3
13.24±0.1
1.4±0.2
+0.08
−0.07
0.12
0.10
+7°
−3°
P44GX-50-600A-4
14
Data Sheet M15773EJ4V0DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD23C32000AL.
Types of Surface Mount Device
PD23C32000ALGY-MJH : 48-pin PLASTIC TSOP (I) (12 x 18) (Normal bent)
µ
PD23C32000ALGY-MKH : 48-pin PLASTIC TSOP (I) (12 x 18) (Reverse bent)
µ
PD23C32000ALGX : 44-pin PLASTIC SOP (15.24 mm (600))
µ
µµµµ
PD23C32000AL
Data Sheet M15773EJ4V0DS
15
PD23C32000AL
µµµµ
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition → This edition)
edition edition
4th edition/ p.9 p.9 Addition AC Characteristics Address skew time (t
Feb. 2003 Note
p.10 – Addition Cautions on power application
p.11 p.10 Modification Read Cycle Timing Chart
SKEW
)
16
Data Sheet M15773EJ4V0DS
[MEMO]
µµµµ
PD23C32000AL
Data Sheet M15773EJ4V0DS
17
[MEMO]
µµµµ
PD23C32000AL
18
Data Sheet M15773EJ4V0DS
PD23C32000AL
µµµµ
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF THE APPLIED WAVEFORM OF INPUT PINS AND THE UNUSED INPUT PINS
FOR CMOS
Note:
Input levels of CMOS devices must be fixed. CMOS devices behave differently than Bipolar or
IL
NMOS devices. If the input of a CMOS device stays in an area that is between V
IH
(MIN.) due to the effects of noise or some other irregularity, malfunction may result.
V
Therefore, not only the input waveform is fixed, but also the waveform changes, it is important
to use the CMOS device under AC test conditions. For unused input pins in particular, CMOS
devices should not be operated in a state where nothing is connected, so input levels of CMOS
devices must be fixed to high or low by using pull-up or pull-down circuitry. Each unused pin
DD
should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device
and related specifications governing the devices.
or GND with a resistor, if it is considered to have a possibility of
(MAX.) and
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M15773EJ 4V0DS
19
µµµµ
PD23C32000AL
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of February, 2003. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
•
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
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Descriptions of circuits, software and other related information in this document are provided for illustrative
•
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•
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(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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