NEC PD17P709A Technical data

DATA SHEET

MOS INTEGRATED CIRCUIT

PD17P709A

4-BIT SINGLE-CHIP MICROCONTROLLER

WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM

DESCRIPTION

The µPD17P709A is produced by replacing the on-chip mask ROM of the µPD17704A, 17705A, 17707A, 17708A,

and 17709A with a one-time PROM.

PD17P709A allows programs to be written once, so the µPD17P709A is suitable for preproduction in

The

PD17704A, 17705A, 17707A, 17708A, or 17709A system development or low-volume production.

When reading this document, also refer to the publications on the µPD17704A, 17705A, 17707A, 17708A,

or 17709A.

The electrical characteristics (including power supply current) and PLL analog characteristics of the

PD17P709A differ from those of the µPD17704A, 17705A, 17707A, 17708A, and 17709A. In high-volume

application set production, be sure to carefully check these differences.

FEATURES

• Compatible with the

• On-chip one-time PROM: 32 KB (16384 × 16 bits)

• Supply voltage: VDD = 5 V ±10%

ORDERING INFORMATION

Part Number Package

PD17P709AGC-3B9 80-pin plastic QFP (14 × 14)

PD17704A, 17705A, 17707A, 17708A, and 17709A

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U15723EJ1V0DS00 (1st edition) Date Published October 2001 N CP(K) Printed in Japan

2001

FUNCTIONAL OUTLINE

Part Number

Item

Program memory (ROM)

General-purpose data memory (RAM)

Instruction execution time 1.78 µs (with fX = 4.5 MHz crystal oscillator)

General-purpose ports • I/O ports: 46

Stack levels • Address stack: 15 levels

Interrupts • External: 6 sources (falling edge of CE pin, INT0 to INT4)

Timer 5 channels

A/D converter 8 bits × 6 channels (hardware mode and software mode selectable)

D/A converter (PWM) 3 channels (8-bit or 9-bit resolution selectable by software)

Serial interface 2 units (3 channels)

PLL Division mode • Direct division mode (VCOL pin (MF mode): 0.5 to 3 MHz)

Reference frequency

Charge pump Two error-out output pins (EO0, EO1)

Phase comparator Unlock status detectable by program

Intermediate frequency counter • Intermediate frequency (IF) measurement

BEEP output 2 pins

PD17704AµPD17705AµPD17707AµPD17708AµPD17709AµPD17P709A

8192 × 16 bits

(mask ROM) (mask ROM) (mask ROM)

672 × 4 bits 1120 × 4 bits 1176 × 4 bits

• Input ports: 12

• Output ports: 4

• Interrupt stack: 4 levels

• DBF stack: 4 levels (can be manipulated via software)

• Internal: 6 sources (timers 0 to 3, serial interfaces 0 and 1)

• Basic timer (clock: 10, 20, 50, 100 Hz): 1 channel

• 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 kHz): 1 channel

• 8-bit timer (clock: 1 kHz, 2 kHz, 10 kHz, 100 kHz): 2 channels

• 8-bit timer multiplexed with PWM (clock: 440 Hz, 4.4 kHz): 1 channel

Output frequency: 4.4 kHz, 440 Hz (with 8-bit PWM selected)

• 3-wire serial I/O: 2 channels

• 2-wire serial I/O/I2C bus: 1 channel

• Pulse swallow mode (VCOL pin (HF mode): 10 to 40 MHz)

13 types selectable (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, 50 kHz)

P1C0/FMIFC pin: 10 to 11 MHz in FMIF mode

P1C1/AMIFC pin: 0.4 to 0.5 MHz in AMIF mode

• External gate width measurement

P2A1/FCG1, P2A0/FCG0 pin

Output frequency: 1 kHz, 3 kHz, 4 kHz, 6.7 kHz (BEEP0 pin)

12288 × 16 bits 16384 × 16 bits

2.2 kHz, 220 Hz (with 9-bit PWM selected)

(VCOH pin (VHF mode): 60 to 130 MHz)

0.4 to 0.5 MHz in AMIF mode

67 Hz, 200 Hz, 3 kHz, 4 kHz (BEEP1 pin)

PD17P709A

(1/2)

16384 × 16 bits

(one-time PROM)

Data Sheet U15723EJ1V0DS

Part Number

Item

Reset • Power-on reset (on power application)

Standby • Clock stop mode (STOP)

Supply voltage • PLL operation: VDD = 4.5 to 5.5 V

Package 80-pin plastic QFP (14 × 14)

PD17704AµPD17705AµPD17707AµPD17708AµPD17709AµPD17P709A

• Reset by RESET pin

• Watchdog timer reset

Can be set only once on power application: 65536 instructions, 131072

• Stack pointer overflow/underflow reset

Can be set only once on power application: interrupt stack or address stack

• CE reset (CE pin low → high level)

CE reset delay timing can be set.

• Power failure detection function

• Halt mode (HALT)

• CPU operation: VDD = 3.5 to 5.5 V

PD17P709A

instructions, or no-use

selectable

(2/2)

Data Sheet U15723EJ1V0DS

PIN CONFIGURATION (TOP VIEW)

80-pin plastic QFP (14 × 14)

PD17P709AGC-3B9

(1) Normal operation mode

INXOUT

INT2

P1A3/INT4

P1A2/INT3

P1A1

P1A0/TM0G

P3A3

P3A2

P3A1

P3A0

P3B3

P3B2

P3B1

P3B0

P2A2

P2A1/FCG1

P2A0/FCG0

P1B3

P1B2/PWM2

P1B1/PWM1

P1B0/PWM0

RESET

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

GND0

REG

P2D0

P2D1

P2D2

P0B0/SI1

P0B1/SO1

P0B2/SCK1

P0B3/SI0

P0A0/SO0

P0A1/SCK0

P0A2/SCL

P0A3/SDA

P0C0

P0C1

PD17P709A

P0C2

P0C3

P2C0

P2C1

P2C2

P2C3

P3D0

P3D1

P3D2

P3D3

P3C0

P3C1

P3C2

P3C3

P2B0

P2B1

P2B2

P2B3

INT0

INT1

GND2

P0D3/AD3

P0D2/AD2

P0D1/AD1

P0D0/AD0

P1C3/AD5

P1C2/AD4

Data Sheet U15723EJ1V0DS

P1C0/FMIFC

P1C1/AMIFC

VCOH

VCOL

GND1

EO0

EO1

TEST

P1D3

P1D2

P1D1/BEEP1

P1D0/BEEP0

(2) PROM programming mode

PD17P709A

(L)

(OPEN)

GND0

Note

(L)

REG

(L)

(H)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

CLK

(L)

GND2

(L)

Note Connect to the same potential as V

MD3

DD.

MD2

MD1

MD0

(L)

GND1

(OPEN)

(L)

Caution The items in parentheses indicate the processing of pins not used in the PROM programming

mode.

L: Independently connect to GND via a resistor (470 Ω)

H: Independently connect each pin to VDD via a resistor (470 Ω)

OPEN: Leave open.

Data Sheet U15723EJ1V0DS

PIN NAMES

PD17P709A

AD0 to AD5: A/D converter input

AMIFC: AM frequency counter input

BEEP0, BEEP1: BEEP output

CE: Chip enable

CLK: Address update clock input

D0 to D7: Data I/O

EO0, EO1: Error-out output

FCG0, FGC1: Frequency counter gate input

FMIFC: FM frequency counter input

GND0 to GND2: Ground 0 to 2

INT0 to INT4: External interrupt input

MD0 to MD3: Operation mode selection

PWM0 to PWM2: D/A converter output

P0A0 to P0A3: Port 0A

P0B0 to P0B3: Port 0B

P0C0 to P0C3: Port 0C

P0D0 to P0D3: Port 0D

P1A0 to P1A3: Port 1A

P1B0 to P1B3: Port 1B

P1C0 to P1C3: Port 1C

P1D0 to P1D3: Port 1D

P2A0 to P2A2: Port 2A

P2B0 to P2B3: Port 2B

P2C0 to P2C3: Port 2C

P2D0 to P2D2: Port 2D

P3A0 to P3A3: Port 3A

P3B0 to P3B3: Port 3B

P3C0 to P3C3: Port 3C

P3D0 to P3D3: Port 3D

REG: CPU regulator

RESET: Reset input

SCK0, SCK1: 3-wire serial clock I/O

SCL: 2-wire serial clock I/O

SDA: 2-wire serial data I/O

SI0, SI1: 3-wire serial data input

SO0, SO1: 3-wire serial data output

TEST: Test input

TM0G: Timer 0 gate input

VCOH: Local oscillation high input

VCOL: Local oscillation low input

DD0, VDD1: Power supply

VPP: Program voltage application

XIN, XOUT: Main clock oscillation

Data Sheet U15723EJ1V0DS

BLOCK DIAGRAM

PD17P709A

P0A0 to P0A3

P0B0 to P0B3

P0C0 to P0C3

P0D0 to P0D3

P1A0 to P1A3

P1B0 to P1B3

P1C0 (MD0)

to P1C3 (MD3)

P1D0 to P1D3

P2A0 to P2A2

P2B0 to P2B3

P2C0 (D0)

to P2C3 (D3)

P2D0 to P2D2

P3A0 to P3A3

P3B0 to P3B3

P3C0 to P3C3

P3D0 (D4)

to P3D3 (D7)

AD0/P0D0

AD1/P0D1

AD2/P0D2

AD3/P0D3

AD4/P1C2

AD5/P1C3

PWM0/P1B0

PWM1/P1B1

PWM2/P1B2

Ports

A/D

converter

D/A

converter

8-bit

timer 3

RAM

1776 × 4 bits

SYSREG

ALU

Instruction

decoder

One-time PROM

16384 × 16 bits

Program counter

Stack

CPU

Peripheral

PLL

Serial

interface 0

Serial

interface 1

BEEP

Interrupt

control

Frequency

counter

8-bit

timer 0

gate

counter

8-bit

timer 1

8-bit

timer 2

OSC

VCOH

VCOL

EO0

EO1

SO0/P0A0

SCK0/P0A1

SCL/P0A2

SDA/P0A3

SI0/P0B3

SCK1/P0B2

SO1/P0B1

SI1/P0B0

BEEP0/P1D0

BEEP1/P1D1

INT0

INT1

INT2

INT3/P1A2

INT4/P1A3

FCG0/P2A0

FCG1/P2A1

FMIFC/P1C0

AMIFC/P1C1

TM0G/P1A0

OUT

Basic

timer

GND0 to GND2

CPU

Remark Pins in parentheses are used in PROM programming mode.

Data Sheet U15723EJ1V0DS

Reset

Regulator

RESET

0, VDD1

REG

PD17P709A

CONTENTS

1. PIN FUNCTIONS .............................................................................................................................. 9

1.1 Pin Function List .................................................................................................................. 9

1.2 PROM Programming Mode ................................................................................................. 13

1.3 Equivalent Circuits of Pins ................................................................................................. 14

1.4 Connections of Unused Pins .............................................................................................. 19

1.5 Cautions on Using CE, INT0 to INT4, and RESET Pins

(Only in Normal Operation Mode) ...................................................................................... 21

1.6 Cautions on Using TEST Pin (Only in Normal Operation Mode) ..................................... 21

2. ONE-TIME PROM (PROGRAM MEMORY) WRITE, READ, AND VERIFY .................................... 22

2.1 Operation Modes for Program Memory Write, Read and Verify ...................................... 23

2.2 Program Memory Write Procedure .................................................................................... 24

2.3 Program Memory Read Procedure ..................................................................................... 25

3. ELECTRICAL SPECIFICATIONS .........................................................................................................26

4. PACKAGE DRAWING ..........................................................................................................................31

5. RECOMMENDED SOLDERING CONDITIONS ...................................................................................32

APPENDIX DEVELOPMENT TOOLS ......................................................................................................33

Data Sheet U15723EJ1V0DS

PD17P709A

1. PIN FUNCTIONS

1.1 Pin Function List

Pin No. Symbol Function Output Form

1 INT2 Edge-detectable vectored interrupt input pins. Rising or falling edge can be –

41 INT1 specified.

42 INT0

2 P1A3/INT4 Port 1A multiplexed with external interrupt request signal input and event –

3 P1A2/INT3 signal input pins.

4 P1A1 • P1A3 to P1A0

5 P1A0/TM0G • 4-bit input port

• INT4, INT3

• Edge-detectable vectored interrupt

• TM0G

• Input for gate of 8-bit timer 0

After reset

Power-on reset WDT&SP reset CE reset

Input Input Retained Retained

(P1A3 to P1A0) (P1A3 to P1A0)

6 P3A3 4-bit I/O port. CMOS

| | Input or output can be specified in 4-bit units. push-pull

9 P3A0

Power-on reset WDT&SP reset CE reset

Input Input Retained Retained

10 P3B3 4-bit I/O port. CMOS

| | Input or output can be specified in 4-bit units. push-pull

13 P3B0

Power-on reset WDT&SP reset CE reset

Input Input Retained Retained

14 P2A2 Port 2A multiplexed with external gate counter input pins. CMOS

15 P2A1/FCG1 • P2A2 to P2A0 push-pull

16 P2A0/FCG0 • 3-bit I/O port

• Input or output can be specified in 1-bit units.

• FCG1, FCG0

• Input for external gate counter

Power-on reset WDT&SP reset CE reset

Input Input Retained Retained

(P2A2 to P2A0) (P2A2 to P2A0) (P2A2 to P2A0) (P2A2 to P2A0)

After reset

With clock stopped

Data Sheet U15723EJ1V0DS

PD17P709A

Pin No. Symbol Function Output Form

17 P1B3 Port 1B multiplexed with D/A converter output pins. N-ch

18 P1B2/PWM2 • P1B3 to P1B0 open-drain

| | • 4-bit output port (12 V

20 P1B0/PWM0 • PWM2 to P2M0 withstanding

• 8- or 9-bit D/A converter output voltage)

After reset

Power-on reset WDT&SP reset CE reset

Outputs low level Outputs low level Retained Retained

(P1B3 to P1B0) (P1B3 to P1B0) (P1B3 to P1B0)

21 GND2 Ground –

33 GND1

75 GND0

22 P0D3/AD3 Port 0D multiplexed with A/D converter input pins –

| | • P0D3 to P0D0

25 P0D0/AD0 • 4-bit input port

• Pull-down resistors can be connected in 1-bit units.

• AD3 to AD0

• Analog input of A/D converter with 8-bit resolution

After reset

Power-on reset WDT&SP reset CE reset

Input with pull-down Input with pull-down

resistor resistor

(P0D3 to P0D0) (P0D3 to P0D0)

26 P1C3/AD5 Port 1C multiplexed with A/D converter input and IF counter input pins. –

27 P1C2/AD4 • P1C3 to P1C0

28 P1C1/AMIFC • 4-bit input port

29 P1C0/FMIFC • AD5, AD4

• Analog input to A/D converter with 8-bit resolution

• FMIFC, AMIFC

• Input to frequency counter

After reset

Power-on reset WDT&SP reset CE reset

Input Input • P1C3/AD5, • P1C3/AD5,

(P1C3 to P1C0) (P1C3 to P1C0) P1C2/AD4 P1C2/AD4

Retained Retained

• P1C1/AMIFC, • P1C1/AMIFC,

P1C0/FMIFC P1C0/FMIFC

Input Input

(P1C1, P1C0) (P1C1, P1C0)

With clock stopped

Data Sheet U15723EJ1V0DS

PD17P709A

Pin No. Symbol Function Output Form

30 VDD1 Power supply. Supply the same voltage to these pins. –

79 VDD0 • With CPU and peripheral function operating: 4.5 to 5.5 V

• With CPU operating: 3.5 to 5.5 V

• With clock stopped: 2.2 to 5.5 V

31 VCOH PLL local oscillation (VCO) frequency input. –

32 VCOL • VCOH

• Active with VHF mode selected by program; otherwise, pulled down.

• VCOL

•

Active with HF or MW mode selected by program; otherwise, pulled down.

Because the input of these pins goes into an AC amplifier, cut the DC

component of the input signal with a capacitor.

34 EO0 Output from charge pump of PLL frequency synthesizer. Outputs the divided CMOS

35 EO1 frequency of local oscillation and the result of comparison of the phase 3-state

difference of the reference frequency.

After reset

Power-on reset WDT&SP reset CE reset

High-impedance High-impedance High-impendance High-impedance

output output output output

36 TEST Test input pin. –

Be sure to connect this pin to GND.

37 P1D3 Port 1D and BEEP output. CMOS

38 P1D2 • P1D3 to P1D0 push-pull

39 P1D1/BEEP1 • 4-bit I/O port

40 P1D0/BEEP0 • Input or output can be specified in 1-bit units.

• BEEP1, BEEP0

• BEEP output

After reset

Power-on reset WDT&SP reset CE reset

Input Input Retained Retained

(P1D3 to P1D0) (P1D3 to P1D0) (P1D3 to P1D0) (P1D3 to P1D0)

43 P2B3 4-bit I/O port. CMOS

| | Input or output can be specified in 1-bit units. push-pull

46 P2B0

Power-on reset WDT&SP reset CE reset

Input Input Retained Retained

47 P3C3 4-bit I/O port. CMOS

| | Input or output can be specified in 4-bit units. push-pull

50 P3C0

Power-on reset WDT&SP reset CE reset

Input Input Retained Retained

After reset

With clock stopped

Data Sheet U15723EJ1V0DS

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