NEC PD168110 DATA SHEET

UPD168110

DATA SHEET

MOS INTEGRATED CIRCUIT

PD168110

MICROSTEP DRIVER FOR DRIVING CAMERA LENS

DESCRIPTION

The PD168110 is a monolithic 2-channel H bridge driver that consists of a CMOS controller and a MOS output stage. It can reduce the current consumption and the voltage loss at the output stage compared with a conventional driver using bipolar transistors, thanks to employment of a MOS process. This product employs a P-channel MOSFET on the high side of the output stage, eliminating a charge pump. As a result, the circuit current consumption can be substantially reduced during operation.

This product is ideal for driving the motor of a digital still camera as it can switch over between two-phase excitation driving and microstep driving, using a stepper motor.

FEATURES

O Two H bridge circuits employing power MOSFET

O Current feedback 64-step microstep driving and two-phase excitation driving selectable

O Low on-resistance: 2 Ω MAX.

O 3 V power supply

Minimum operating power supply voltage VDD = 2.7 V

O Under voltage lockout circuit

Shuts down internal circuitry at VDD = 1.7 V TYP.

O 24-pin TSSOP

ORDERING INFORMATION

Part Number	Package
PD168110MA-6A5	24-pin plastic TSSOP (5.72 mm (225))

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

Document No. S15840EJ2V0DS00 (2nd edition)	The mark shows major revised points.
Date Published June 2005 NS CP(K)			2003
Printed in Japan

PD168110

PIN FUNCTIONS

Package: 24-pin TSSOP

	MODE			1	24			RESETB
	CLK			2	23			CW
	LGND			3	22			VDD
	COSC			4	21			FIL2
	MOB			5	20			FIL1
	PGND2			6	19			FB1
	OUT2B			7	18			OUT1B
	VM2			8	17			VM1
	OUT2A			9	16			OUT1A
	FB2			10	15			PGND1
	PS			11	14			MOBSEL
	OE			12	13			STOP
Pin No.	Pin Name						Pin Function
1		MODE			Microstep/2-phase excitation switch pin
2		CLK			Pulse input pin
3		LGND			Control block GND pin
4		COSC			Pin connecting capacitor for output oscillator
5		MOB			Phase detection output pin
6	PGND2				Output block GND pin
7		OUT2B			Channel 2 output B
8			VM2		Motor power pin
9		OUT2A			Channel 2 output A
10			FB2		Channel 2 current detection resistor connecting pin
11			PS		Power save mode pin
12			OE		Output enable pin
13		STOP			Stop mode pin
14	MOBSEL				MOB output select pin
15	PGND1				Output block GND pin
16		OUT1A			Channel 1 output A
17			VM1		Motor power pin
18		OUT1B			Channel 1 output B
19			FB1		Channel 1 current detection resistor connecting pin
20		FIL1			Channel 1 filter capacitor connecting pin
21		FIL2			Channel 2 filter capacitor connecting pin
22			VDD		Control block power pin
23			CW		Revolution direction setting pin
24	RESETB				Reset input pin

2	Data Sheet S15840EJ2V0DS

PD168110

BLOCK DIAGRAM

		MODE MOBSEL RESET CLK				CW	PS	STOP
VDD				DECODER
VM1
VM2				PULSE
				GENERATER
				EVR1	EVR2
COSC		OSC		CURRENT SET						MOB
LGND		+		FILTER	FILTER		+
		– +		Internal Block				+ –
FB1	Current	VM						VM	Current	FB2
	Sense1								Sense2
		H BRIDGE
							H BRIDGE
		ch1						ch2
	PGND	OUT1A OUT1B	FIL1	OE		FIL2	OUT2A OUT2B		PGND

Truth Table

RESET		CLK			CW	OE	PS	STOP	MODE	MOBSEL	Operation Mode
H					L	H	L	L	H	L	Microstep CW mode
											MOB: 1 pulse/cycle
H					H	H	L	L	H	L	Microstep CCW mode
											MOB: 1 pulse/cycle
H					L	H	L	L	H	H	Microstep CW mode
											MOB: 4 pulses/cycle
H					H	H	L	L	H	H	Microstep CCW mode
											MOB: 4 pulses/cycle
H					L	H	L	L	L	X	2-phase CW mode
H					H	H	L	L	L	X	2-phase CCW mode
H			X		X	L	X	X	X	X	Output Hi-Z
H			X		X	H	L	H	H	X	STOP mode after MOB = L
											(CLK must be input until MOB = L)
H			X		X	H	H	H	H	X	PS mode after MOB = L
											(CLK must be input until MOB = L)
H			X		X	H	H	L	H	X	Setting prohibited
L			X		X	X	X	X	X	X	Reset mode

H: High level, L: Low level, X: High level or low level

Data Sheet S15840EJ2V0DS

3

PD168110

Command Input Timing Chart

In microstep mode

RESET
	1				2		3		4		5		6		7		8		9 10 1112 1314 15 16 17 18 19 20 21 22 23242526272829 30
CLK
CW
OE
PS
STOP
	1				2		3		4		5		6		7		8		9 10 111213 1415 16 1718 17 16																								15 1413
PULSE
OUT
(internal)
Chopping pulse
																																								Power save mode
MOB																																											STOP mode
																											Output when MOBSEL = H
													CW mode																																stopped															Output Hi-Z
Reset status																																											CCW mode																									Reset status

4	Data Sheet S15840EJ2V0DS

PD168110

Standard Connection Diagram

Microstep/2-phase excitation driving

CPU

MODE

MOBSEL RESET

CLK

CW

PS

STOP

VDD

DECODER

3.3 V

VM1

VM2

PULSE

VDD

GENERATER

5.0 V

EVR1

EVR2

330 pF

COSC

OSC

CURRENT SET

MOB

10 kΩ

LGND

+

FILTER

FILTER

+

– +

Internal Block

+ –

FB1

Current

VM

VM

Current

FB2

Sense1

Sense2

H BRIDGE

H BRIDGE

1000 pF

2 kΩ

ch1

ch2

2 kΩ

1000 pF

PGND

OUT1A OUT1B

FIL1

OE

FIL2

OUT2A OUT2B

PGND

1000 pF

1000 pF

from CPU

M

Only 2-phase excitation driving

CPU

MODE

MOBSEL RESET CLK

CW

PS

STOP

VDD

DECODER

3.3 V

VM1

VM2

PULSE

VDD

GENERATER

5.0 V

EVR1

EVR2

10 kΩ

COSC

OSC

CURRENT SET

MOB

LGND

+

FILTER

FILTER

+

VDD

Internal Block

VDD

– +

+ –

FB1

Current

VM

VM

Current

FB2

Sense1

Sense2

H BRIDGE

H BRIDGE

ch1

ch2

PGND

OUT1A OUT1B

FIL1

OE

FIL2

OUT2A OUT2B

PGND

From CPU

M

Data Sheet S15840EJ2V0DS

5

PD168110

Output Timing Chart

• Microstep output mode

position

Ch 1 current

100 99.5

98.1 95.7

92.4

88.2

83.1

77.3

70.7

63.4

55.6

47.1

38.3

29.0

19.5

9.8

0

–9.8

–19.5

–29.0

–38.3

–47.1

–55.6

–63.4

–70.7

–77.3

–83.1

–92.4 –88.2 –98.1 –95.7 –100 –99.5

0

5

10

15

20

25

30

35

40

45

50

55

60

65

Ch 2 current

100 99.5

98.1 95.7

92.4

88.2

83.1

77.3

70.7

63.4

55.6

47.1

38.3

29.0

19.5

9.8

0

—9.8

—19.5

—29.0

—38.3

—47.1

—55.6

—63.4

—70.7

—77.3

—83.1

—92.4 —88.2 —98.1 —95.7 —100 —99.5

0	5	10	15	20	25	30	35	40	45	50	55	60	65
					MOB output (when MOBSEL = “L”)
0	5	10	15	20	25	30	35	40	45	50	55	60	65
					MOB output (when MOBSEL = “H”)
0	5	10	15	20	25	30	35	40	45	50	55	60	65
						CLK input

0

5

10

15

20

25

30

35

40

45

50

55

60

65

The horizontal axis indicates the number of steps. This figure shows an example in the CW mode. The pulse advances in synchronization with the rising edge of CLK. The current flows into ch 1 and ch 2 in the positive direction when it flows from OUT1A to OUT1B, and in the negative direction when it flows from OUT1B to OUT1A (the values shown above are ideal values and do not indicate the actual values).

6	Data Sheet S15840EJ2V0DS