NEC PD168110 DATA SHEET
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DESCRIPTION
The µPD168110 is a monolithic 2-channel H bridge driver that consists of a CMOS controller and a MOS output
stage. It can reduce the current consumption and the voltage loss at the output stage compared with a conventional
driver using bipolar transistors, thanks to employment of a MOS process. This product employs a P-channel
MOSFET on the high side of the output stage, eliminating a charge pump. As a result, the circuit current consumption
can be substantially reduced during operation.
This product is ideal for driving the motor of a digital still camera as it can switch over between two-phase excitation
driving and microstep driving, using a stepper motor.
FEATURES
O Two H bridge circuits employing power MOSFET
O Current feedback 64-step microstep driving and two-phase excitation driving selectable
O Low on-resistance: 2 Ω MAX.
O 3 V power supply
Minimum operating power supply voltage V
O Under voltage lockout circuit
Shuts down internal circuitry at V
O 24-pin TSSOP
ORDERING INFORMATION
Part Number Package
MICROSTEP DRIVER FOR DRIVING CAMERA LENS
µ
PD168110MA-6A5 24-pin plastic TSSOP (5.72 mm (225))
DATA SHEET
DD = 2.7 V
DD = 1.7 V TYP.
MOS INTEGRATED CIRCUIT
µ
PD168110
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15840EJ2V0DS00 (2nd edition)
Date Published June 2005 NS CP(K)
Printed in Japan
The mark shows major revised points.
2003
µ
PD168110
PIN FUNCTIONS
Package: 24-pin TSSOP
MODE
CLK
LGND
C
OSC
MOB
PGND2
OUT2B
V
OUT2A
FB2
PS
OE
1
2
3
4
5
6
7
M2
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
RESETB
CW
DD
V
FIL2
FIL1
FB1
OUT1B
M1
V
OUT1A
PGND1
MOBSEL
STOP
Pin No. Pin Name Pin Function
1 MODE Microstep/2-phase excitation switch pin
2 CLK Pulse input pin
3 LGND Control block GND pin
4 COSC Pin connecting capacitor for output oscillator
5 MOB Phase detection output pin
6 PGND2 Output block GND pin
7 OUT2B Channel 2 output B
8 VM2 Motor power pin
9 OUT2A Channel 2 output A
10 FB2 Channel 2 current detection resistor connecting pin
11 PS Power save mode pin
12 OE Output enable pin
13 STOP Stop mode pin
14 MOBSEL MOB output select pin
15 PGND1 Output block GND pin
16 OUT1A Channel 1 output A
17 VM1 Motor power pin
18 OUT1B Channel 1 output B
19 FB1 Channel 1 current detection resistor connecting pin
20 FIL1 Channel 1 filter capacitor connecting pin
21 FIL2 Channel 2 filter capacitor connecting pin
22 VDD Control block power pin
23 CW Revolution direction setting pin
24 RESETB Reset input pin
2
Data Sheet S15840EJ2V0DS
µ
PD168110
BLOCK DIAGRAM
V
DD
V
M1
V
M2
MODE MOBSEL
RESET CLK
DECODER
PULSE
GENERATER
CW PS STOP
C
OSC
LGND
FB1
Current
Sense1
PGND
EVR1
OSC
++
+
–
V
M
H BRIDGE
ch1
OUT1A OUT1B
CURRENT SET
FILTER FILTER
Internal Block
FIL1 OE FIL2
EVR2
+
–
M
V
H BRIDGE
ch2
OUT2A OUT2B
Current
Sense2
PGND
Truth Table
RESET CLK CW OE PS STOP MODE MOBSEL Operation Mode
H
H
H
H
H
H
H X X L X X X X Output Hi-Z
H X X H L H H X
H X X H H H H X
H X X H H L H X Setting prohibited
L X X X X X X X Reset mode
L H L L H L
H H L L H L
L H L L H H
H H L L H H
L H L L L X 2-phase CW mode
H H L L L X 2-phase CCW mode
Microstep CW mode
MOB: 1 pulse/cycle
Microstep CCW mode
MOB: 1 pulse/cycle
Microstep CW mode
MOB: 4 pulses/cycle
Microstep CCW mode
MOB: 4 pulses/cycle
STOP mode after MOB = L
(CLK must be input until MOB = L)
PS mode after MOB = L
(CLK must be input until MOB = L)
MOB
FB2
H: High level, L: Low level, X: High level or low level
Data Sheet S15840EJ2V0DS
3
µ
PD168110
Command Input Timing Chart
In microstep mode
RESET
CLK
CW
OE
PS
STOP
PULSE
OUT
(internal)
Chopping pulse
MOB
Reset status
1
2 3 4 5 6 7 8 9 1011 12 13 14 1516
12 345678910111213 1314 1415 1516 17 18 17 16
Output when MOBSEL = H
CW mode
17 1819 20 21 22 23 24 25 26272829 30
Power save mode
STOP mode
stopped
CCW mode Reset status
Output Hi-Z
4
Data Sheet S15840EJ2V0DS
µ
PD168110
Standard Connection Diagram
Microstep/2-phase excitation driving
CPU
DD
5.0 V
330 pF
V
V
V
C
LGND
FB1
2 kΩ
M1
M2
OSC
Current
Sense1
PGND
3.3 V
Only 2-phase excitation driving
DECODER
PULSE
EVR2
1000 pF
from CPU
M
CPU
CW PS STOP
–
H BRIDGE
ch2
OUT2A OUT2B
M
V
Current
Sense2
PGND
MODE MOBSEL
OSC
++
++–
V
M
H BRIDGE
ch1
OUT1A OUT1B
RESET CLK
GENERATER
EVR1
CURRENT SET
FILTER FILTER
Internal Block
FIL1 OE FIL2
1000 pF
MOB
FB2
2 kΩ
V
10 kΩ
DD
1000 pF1000 pF
3.3 V
5.0 V
V
MODE MOBSEL
V
DD
V
M1
V
M2
C
OSC
LGND
DD
Current
FB1
Sense1
PGND
OSC
++–
V
M
H BRIDGE
ch1
OUT1A OUT1B
RESET CLK
DECODER
PULSE
GENERATER
EVR1
CURRENT SET
FILTER FILTER
Internal Block
FIL1 OE
EVR2
From CPU
M
CW PS STOP
++
–
H BRIDGE
ch2
FIL2
OUT2A OUT2B
DD
V
10 kΩ
MOB
V
DD
M
V
Current
Sense2
PGND
FB2
Data Sheet S15840EJ2V0DS
5
µ
PD168110
Output Timing Chart
• Microstep output mode
100
99.5
98.1
95.7
92.4
88.2
83.1
77.3
70.7
63.4
55.6
47.1
38.3
29.0
19.5
9.8
0
–9.8
–19.5
–29.0
–38.3
–47.1
–55.6
–63.4
–70.7
–77.3
–83.1
–88.2
–92.4
–95.7
–98.1
–99.5
–100
0510
position
Ch 1 current
15 20 25 30 35 40 45 50 55 60 65
100
Ch 2 current
99.5
98.1
95.7
92.4
88.2
83.1
77.3
70.7
63.4
55.6
47.1
38.3
29.0
19.5
9.8
0
—
9.8
—
19.5
—
29.0
—
38.3
—
47.1
—
55.6
—
63.4
—
70.7
—
77.3
—
83.1
—
88.2
—
92.4
—
95.7
—
98.1
—
99.5
—
100
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0
5 101520253035404550556065
MOB output (when MOBSEL = “L”)
MOB output (when MOBSEL = “H”)
CLK input
0 5 10 15 20 25 30 35 40 45 50 55 60 65
The horizontal axis indicates the number of steps. This figure shows an example in the CW mode. The pulse
advances in synchronization with the rising edge of CLK. The current flows into ch 1 and ch 2 in the positive direction
when it flows from OUT1A to OUT1B, and in the negative direction when it flows from OUT1B to OUT1A (the values
shown above are ideal values and do not indicate the actual values).
6
Data Sheet S15840EJ2V0DS
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