NEC PD16435, PD16435A DATA SHEET

UPD16435	DATA SHEET
	MOS INTEGRATED CIRCUIT
	μPD16435, 16435A

DOT MATRIX LCD CONTROLLER/DRIVER

DESCRIPTION

The μPD16435 and 16435A are controllers/drivers for a 119 × 73-dot LCD, and perform LCD full-dot and character composite display by means of control by a microprocessor that has a 4 or 8-bit data bus. A charge pump type DC/DC converter is also incorporated, enabling 3 or 5 V single power supply drive.

The μPD16435 uses an external reference clock. The μPD16435A has the on-chip oscillation circuit (external crystal resonator).

FEATURES

•Can interface to 4 or 8-bit CPU.

•Incorporates 119 segment outputs and 73 common outputs. (Display duty selectable from 1/35, 1/37, 1/71, 1/73)

•5 × 7 character font 208 character data configuration character generation ROM and 16 character data configuration character generation RAM, allowing composite full-dot and character display

•Incorporates extended display functions such as magnification, lateral scrolling, blink, reverse, etc.

•Operating voltage: 2.7 V to 5.5 V

•On-chip DC/DC converter: Selectable between ×4 set-up circuit and ×2 step-up circuit

•On-chip temperature correction circuit

•Master/slave operation capability

•On-chip power-on reset circuit

•On-chip oscillation circuit (μPD16435A)

•232-pin TCP (Tape Carried Package)

ORDERING INFORMATION

Part Number		Package
μPD16435N-001-×××	TCP (TAB), Standard ROM code
μPD16435N-001-001	Standard quad TCP (Conforms to EIAJ), Standard ROM code
μPD16435N-001-002	Standard dual TCP (Output OLB:	0.25 mm pitch), Standard ROM code
μPD16435AN-001-×××	TCP (TAB), Standard ROM code
μPD16435AN-001-001	Standard quad TCP (Conforms to EIAJ), Standard ROM code
μPD16435AN-001-052	Standard dual TCP (Output OLB:	0.25 mm pitch), Standard ROM code

Explanation of Part Number

μPD16435 (A) N-xxx-xxx

TCP code

ROM code

The TCP model is a custom model. For details, consult NEC sales representative.

Document No. S10298EJ3V0DS00 (3rd edition) Date Published April 1997 N

Printed in Japan

© 1995

μPD16435, 16435A

BLOCK DIAGRAM

OSC1

OSC2

COM73

COM1

SEG119

SEG1

OSC

		Common Driver
	GeneratorTiming	73
Scaler		73-Bit Shift Register

		CursorBlinking ControlRegister	119
OSC3	Selector		Display RAM
			119 × 73 Bits
		Address
		Counter
		7
		Instruction Decoder
		8	8
		8
		Instruction Register	Data Register
		8
		Parallel I/F

Segment Driver

119

119-Bit Latch

Scroll RAM

13 × 73 Bits

CGROM

5 × 7 × 208 Bits

5

V5

V4

5

V3

CGRAM

V2

5 × 7 × 16 Bits

V1

8

– IN

-Amp

V

+

Busy Flag

OP

VIN

×2/×4 Step-Up Circuit

2

8

TEST1

TEST2

WS

CS

RS

RD

WR

D0~7

BUSY

RESET

SYNC

SCR

C1

C1

C2

C2

C3

C3

3/5

VCC

GND1

VDD

GND2

+

–

+

–

+

–

μPD16435, 16435A

PIN CONFIGURATION (CHIP)

DDDDDDDDVV 01234567ININV1V2V3V4V5 VDDCSRSRDWRWSSCR3/5OSCOSCOSCVCCC1–C1+C2–C2+C3–C3+–(( Dummy26GND1RESETBUSYSYNCTEST1TEST2123Dummy25)+)GND2Dummy24Dummy23

258

Dummy1

Dummy2 1 COM38

COM39

COM73

Dummy3

Dummy4

SEG1

SEG30

Dummy5

79 80 Dummy13

SEG32

SEG31

Dummy14

	215
214	Dummy22
	Dummy21
	COM1
	COM2

COM37

Dummy20

Dummy17

SEG119

135	136	SEG85
		Dummy16

Dummy15

SEG84

SEG83

3

μPD16435, 16435A

PIN DESCRIPTIONS

Pin Name

Pin No.

Input/Output

Output Type

Description

255

Input

–––

Chip select signal

CS

RS

254

Input

–––

Register selection signal (specifies address register when “0”,

control register when “1”).

Read enable signal. Reads write address when scrolling.

RD

253

Input (Schmitt)

–––

Active edge is falling edge.

Write enable signal.

WR

252

Input (Schmitt)

–––

Active edge is falling edge.

WS

251

Input

–––

Word length selection signal (4-bit input when “1”, 8-bit input

when “0”).

Transmit/receive data (3-state bidirectional)

Upper → D4 to D7

250

Lower → D0 to D3 (These pins should be set as unused in case

D0 to D7

to

Input/output

CMOS 3-state

of 4-bit data).

243

In test mode, these pins are output pins.

In a 4-bit transfer, storage is performed in the upper (MSB) in

order from the data transferred first.

240

Output

Nch open-drain

“0” indicates busy state.

BUSY

“0” → Initialization of all internal registers and commands is

RESET

242

Input

–––

performed. Output is fixed at V1.

SCR

241

Output

CMOS

Signal is output to CPU on completion of one-character scroll.

SYNC

239

Input/output

Nch open-drain

Synchronization signal input/output pins for master/slave

operation.

μPD16435: Input the 4.19 MHz reference clock to the OSC1 pin

OSC1

235

externally. Leave the OSC2 pin open. (Always outputs high

–––

–––

level.)

OSC2

234

μPD16435A: This is the pin to which the 4.19 MHz crystal

resonator is connected. Input the external clock to OSC1 first.

OSC3

233

Input (Schmitt)

–––

2 Hz external clock input pin. Scaled by 2 internally to generate 1

Hz, used as blink synchronization signal.

COM1 to

212 to 176

Output

Analog switch

Common output signals

COM73

3 to 38

SEG1 to

41 to 70

81 to 134

Output

Analog switch

Segment output signals

SEG119

137 to 171

TEST1

238

Output

–––

“1” → Test mode

TEST2

237

“0” or open → Normal operating mode

4

μPD16435, 16435A

Pin Name

Pin No.

Input/Output

Output Type

Description

V1

221

Output

–––

LCD drive power supply pin

Internal OP-amp output

220

LCD drive power supply pins

V2 to V5

to

Input

–––

Can be adjusted by addition of external resistor.

217

VIN(–)

224

Input

–––

Liquid crystal drive power supply OP-amp input pins

VIN(+)

223

VCC, GND1

232, 256

–––

–––

Logic power supply, GND

VDD, GND2

257, 222

–––

–––

Liquid crystal drive (step-up) power supply, GND

Drive voltage selection pin

236

Input

–––

“1” → VDD = 3 V (×4 step-up circuit selected)

3/5

“0” → VDD = 5 V (×2 step-up circuit selected)

C1±, C2±,

230 to

–––

–––

A 1 μF tantalum or ceramic capacitor should be connected

C3±

225

externally.

REFERENCE CLOCK

Product Name

Reference Clock

μPD16435

External input

μPD16435A

On-chip oscillation circuit (External crystal resonator)

OSC CIRCUIT (μPD16435A)

OSC1	OSC2
	4.19 MHz

5

μPD16435, 16435A

REGISTER FUNCTIONS

(1) Address Register

Sets the address of each register, and also sets display control, standby mode, and scaler resetting.

MSB

LSB

× : Don’t Care

b7

b6

b5

b4

b3 b2 b1 b0

Register address (0H to CH)

See table below

Display control

00: Display control off (SEGn, COMn = V1)

01: Display control off (SEGn, COMn = unselected waveform)

10: Normal operation

11: Normal operation

Standby mode setting

0: Normal operation

1: Standby modeNote

Blink internal scaler reset and 1/2 scaler reset

0: Normal operation

1: Reset (Blinking starts when it lights.)

																(Used to synchronize time variations and time mark blinking.)
Note Standby mode =							DC/DC converter stopped
								OSC1 input invalid ( μPD16435)
								OSC stopped ( μPD16435A)
								SEGn, COMn = V1
								Data write/read prohibited
After powering on
	0	0	0		0	0			0		0	0
																Register address list
										Address						Register Name
									b3	b2		b1		b0
								0		0		0		0		Full-dot X address register
								0		0		0		1		Full-dot Y address register
								0		0		1		0		Full-dot data register
								0		0		1		1		Character X address register
								0		1		0		0		Character Y address register
								0		1		0		1		Character data register
								0		1		1		0		CGRAM address register
								0		1		1		1		CGRAM data register
								1		0		0		0		Extension register
								1		0		0		1		Extension register X address register
								1		0		1		0		Extension register Y address register
								1		0		1		1		Scroll register
								1		1		0		0		Control register

6

μPD16435, 16435A

(2) Full-Dot X Address Register (Register Address = 0000B)

Performs full-dot display, display screen X (segment) direction address setting. As scrolling is not possible with a fulldot display, addresses are not allocated to the scroll RAM area.

MSB

LSB

				b3	b2	b1 b0	× : Don’t Care

Full-dot X address (00H to 0EH)

After powering on: Undefined

(3) Full-Dot Y Address Register (Register Address = 0001B)

Performs full-dot display, display screen Y (common) direction address setting.

MSB				LSB
						× : Don’t Care
	b6	b5	b4	b3 b2 b1 b0

Full-dot Y address (00H to 48H)

After powering on: Undefined

(4) Full-Dot Data Register (Register Address = 0010B)

Inputs full-dot display data. Display data is stored in the display memory with the MSB on the left, and display data “1” corresponds to illumination.

Full-dot X address = 00H to 0DH

MSB

LSB

b7

b6

b5

b4

b3

b2

b1

b0

Full-dot display data

Full-dot X address = 0EH

MSB

LSB

× : Don’t Care

b7

b6

b5

b4

b3

b2

b1

Full-dot display data

After powering on: Undefined

7

μPD16435, 16435A

Y Address

Full-Dot X Address and Y Address Allocation

X Address

00H(1)

01H(2)

0EH(15)

00H(1)

01H(2)

48H(73)

b7

b6

b5

b4

b3

b2

b1

b0

b7

b6

b5

b4

b3

b2

b1

8 Bits

7 Bits

(5) Character X Address Register (Register Address = 0011B)

Performs character display display, screen X (segment) direction address setting. X addresses include the scroll RAM

area.

MSB						LSB
							× : Don’t Care
			b4	b3	b2	b1 b0

Character X address (00H to 15H)

After powering on: Undefined

(6) Character Y Address Register (Register Address = 0100B)

Performs character display display, screen Y (common) direction address setting.

MSB

LSB

					b2	b1	b0	× : Don’t Care

Character Y address (00H to 07H)

After powering on: Undefined

8

μPD16435, 16435A

(7) Character Data Register (Register Address = 0101B)

The character indicated in the character code table is displayed at the position indicated by the character X and Y address

registers.

MSB				LSB
						× : Don’t Care
b7	b6	b5	b4	b3 b2 b1 b0

Character code

After powering on: Undefined

Character X Address and Y Address Allocation

X Address

Y Address

						Scroll
		Display RAM Area				RAM Area
					14H		15H
00H(1)	01H(2)		13H(20)	(21)			(22)

00H(1)

01H(2)

1 Bit

07H(8)

8 Bits

5 Bits

1 Bit

9

μPD16435, 16435A

(8) CGRAM Address Register (Register Address = 0110B)

Performs address setting when display data is written to CGRAM. Bits b6 to b3 of the CGRAM address indicate the character code, and bits b2 to b0 indicate the character line.

MSB				LSB
						× : Don’t Care
	b6	b5	b4	b3 b2 b1 b0

Line address (00H to 06H)Note

Character code (00H to 0FH)

Note If auto increment is set with the control register, 06H is followed by 07H. Dummy data should be sent when the address is 07H.

Example: (CGRAM address with auto increment)

--- → 15H → 16H → 17H → 18H → ---

After powering on: Underfined

(9) CGRAM Data Register (Register Address = 0111B)

CGRAM display data. The lower 5 bits of the write data are valid.

MSB						LSB
							× : Don’t Care
			b4	b3	b2	b1 b0

CGRAM data

After powering on: Undefined

10

μPD16435, 16435A

(10) Extension Register (Register Address = 1000B)

Performs magnification, reverse, cursor, and time mark setting.

MSB

LSB

				b3	b2	b1 b0	× : Don’t Care

In case of magnification setting 00: Standard

01: ×2 horizontal

10:×2 vertical

11:×4 magnification (×2 horizontal & vertical)

Magnification display is performed at any line position; characters of different sizes cannot be displayed on the same line.

Line specification magnification display is possible by setting an extension Y address after this command, and multiple-line magnification display is possible by setting consecutive extension Y address.

In case of reverse setting

00: Reverse cancellation (line specification) 01: Reverse (line specification)

10:Reverse cancellation (full screen)

11:Reverse (full screen)

Line specification reverse display is possible by setting an extension Y address after this command, and multiple-line reverse display is possible by setting consecutive extension Y addresses.

Regarding the reverse display Y address direction, a total of 9 dots (7 character part dots + 1 cursor part dot + 1 top space dot) are reversed.

In the case of ×2 vertical magnification or ×4 magnification, a total of 18 dots (14 character part dots + 2 cursor part dots + 2 top space dots) are reversed.

In case of cursor setting 00: Cursor non-display

01: Cursor display (blinking stopped)

10:Cursor display (blink operation)

11:Don’t Care

Blinking display can be performed at any address by specifying an extension X and Y address after this command. The specification is for one address only.

The address specification should be performed in the order: X address → Y address.

In case of character blink setting

X0: Blinking stopped

X1: Blink operation

Blinking can be performed at any address by specifying an extension X and Y address after this command. The specification is for one address only.

The address specification should be performed in the order: X address → Y address.

Extension function setting 00: Magnification setting

01: Reverse setting

10:Cursor setting

11:Character blink setting

After powering on

0 0 0 0

11