UPD16435 |
DATA SHEET |
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MOS INTEGRATED CIRCUIT |
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μPD16435, 16435A |
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DOT MATRIX LCD CONTROLLER/DRIVER
DESCRIPTION
The μPD16435 and 16435A are controllers/drivers for a 119 × 73-dot LCD, and perform LCD full-dot and character composite display by means of control by a microprocessor that has a 4 or 8-bit data bus. A charge pump type DC/DC converter is also incorporated, enabling 3 or 5 V single power supply drive.
The μPD16435 uses an external reference clock. The μPD16435A has the on-chip oscillation circuit (external crystal resonator).
FEATURES
•Can interface to 4 or 8-bit CPU.
•Incorporates 119 segment outputs and 73 common outputs. (Display duty selectable from 1/35, 1/37, 1/71, 1/73)
•5 × 7 character font 208 character data configuration character generation ROM and 16 character data configuration character generation RAM, allowing composite full-dot and character display
•Incorporates extended display functions such as magnification, lateral scrolling, blink, reverse, etc.
•Operating voltage: 2.7 V to 5.5 V
•On-chip DC/DC converter: Selectable between ×4 set-up circuit and ×2 step-up circuit
•On-chip temperature correction circuit
•Master/slave operation capability
•On-chip power-on reset circuit
•On-chip oscillation circuit (μPD16435A)
•232-pin TCP (Tape Carried Package)
ORDERING INFORMATION
Part Number |
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Package |
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μPD16435N-001-××× |
TCP (TAB), Standard ROM code |
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μPD16435N-001-001 |
Standard quad TCP (Conforms to EIAJ), Standard ROM code |
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μPD16435N-001-002 |
Standard dual TCP (Output OLB: |
0.25 mm pitch), Standard ROM code |
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μPD16435AN-001-××× |
TCP (TAB), Standard ROM code |
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μPD16435AN-001-001 |
Standard quad TCP (Conforms to EIAJ), Standard ROM code |
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μPD16435AN-001-052 |
Standard dual TCP (Output OLB: |
0.25 mm pitch), Standard ROM code |
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Explanation of Part Number
μPD16435 (A) N-xxx-xxx
TCP code
ROM code
The TCP model is a custom model. For details, consult NEC sales representative.
Document No. S10298EJ3V0DS00 (3rd edition) Date Published April 1997 N
Printed in Japan
© 1995
μPD16435, 16435A
BLOCK DIAGRAM
OSC1 |
OSC2 |
COM73 |
COM1 |
SEG119 |
SEG1 |
OSC
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Common Driver |
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GeneratorTiming |
73 |
Scaler |
73-Bit Shift Register |
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CursorBlinking ControlRegister |
119 |
OSC3 |
Selector |
Display RAM |
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119 × 73 Bits |
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Address |
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Counter |
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7 |
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Instruction Decoder |
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8 |
8 |
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8 |
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Instruction Register |
Data Register |
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8 |
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Parallel I/F |
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Segment Driver
119
119-Bit Latch
Scroll RAM
13 × 73 Bits
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CGROM |
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5 × 7 × 208 Bits |
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5 |
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V5 |
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V4 |
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5 |
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V3 |
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CGRAM |
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V2 |
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5 × 7 × 16 Bits |
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V1 |
8 |
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– IN |
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-Amp |
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V |
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+ |
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Busy Flag |
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OP |
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VIN |
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×2/×4 Step-Up Circuit
2
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TEST1 |
TEST2 |
WS |
CS |
RS |
RD |
WR |
D0~7 |
BUSY |
RESET |
SYNC |
SCR |
C1 |
C1 |
C2 |
C2 |
C3 |
C3 |
3/5 |
VCC |
GND1 |
VDD |
GND2 |
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+ |
– |
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μPD16435, 16435A
PIN CONFIGURATION (CHIP)
DDDDDDDDVV 01234567ININV1V2V3V4V5 VDDCSRSRDWRWSSCR3/5OSCOSCOSCVCCC1–C1+C2–C2+C3–C3+–(( Dummy26GND1RESETBUSYSYNCTEST1TEST2123Dummy25)+)GND2Dummy24Dummy23
258
Dummy1
Dummy2 1 COM38
COM39
COM73
Dummy3
Dummy4
SEG1
SEG30
Dummy5
79 80 Dummy13
SEG32
SEG31
Dummy14
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215 |
214 |
Dummy22 |
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Dummy21 |
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COM1 |
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COM2 |
COM37
Dummy20
Dummy17
SEG119
135 |
136 |
SEG85 |
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Dummy16 |
Dummy15
SEG84
SEG83
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μPD16435, 16435A |
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PIN DESCRIPTIONS |
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Pin Name |
Pin No. |
Input/Output |
Output Type |
Description |
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255 |
Input |
––– |
Chip select signal |
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CS |
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RS |
254 |
Input |
––– |
Register selection signal (specifies address register when “0”, |
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control register when “1”). |
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Read enable signal. Reads write address when scrolling. |
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RD |
253 |
Input (Schmitt) |
––– |
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Active edge is falling edge. |
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Write enable signal. |
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WR |
252 |
Input (Schmitt) |
––– |
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Active edge is falling edge. |
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WS |
251 |
Input |
––– |
Word length selection signal (4-bit input when “1”, 8-bit input |
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when “0”). |
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Transmit/receive data (3-state bidirectional) |
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Upper → D4 to D7 |
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250 |
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Lower → D0 to D3 (These pins should be set as unused in case |
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D0 to D7 |
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Input/output |
CMOS 3-state |
of 4-bit data). |
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243 |
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In test mode, these pins are output pins. |
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In a 4-bit transfer, storage is performed in the upper (MSB) in |
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order from the data transferred first. |
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240 |
Output |
Nch open-drain |
“0” indicates busy state. |
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BUSY |
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“0” → Initialization of all internal registers and commands is |
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RESET |
242 |
Input |
––– |
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performed. Output is fixed at V1. |
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SCR |
241 |
Output |
CMOS |
Signal is output to CPU on completion of one-character scroll. |
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SYNC |
239 |
Input/output |
Nch open-drain |
Synchronization signal input/output pins for master/slave |
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operation. |
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μPD16435: Input the 4.19 MHz reference clock to the OSC1 pin |
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OSC1 |
235 |
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externally. Leave the OSC2 pin open. (Always outputs high |
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––– |
––– |
level.) |
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OSC2 |
234 |
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μPD16435A: This is the pin to which the 4.19 MHz crystal |
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resonator is connected. Input the external clock to OSC1 first. |
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OSC3 |
233 |
Input (Schmitt) |
––– |
2 Hz external clock input pin. Scaled by 2 internally to generate 1 |
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Hz, used as blink synchronization signal. |
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COM1 to |
212 to 176 |
Output |
Analog switch |
Common output signals |
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COM73 |
3 to 38 |
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SEG1 to |
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81 to 134 |
Output |
Analog switch |
Segment output signals |
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SEG119 |
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TEST1 |
238 |
Output |
––– |
“1” → Test mode |
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TEST2 |
237 |
“0” or open → Normal operating mode |
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μPD16435, 16435A |
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Pin Name |
Pin No. |
Input/Output |
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Description |
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V1 |
221 |
Output |
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––– |
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LCD drive power supply pin |
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Internal OP-amp output |
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220 |
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LCD drive power supply pins |
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V2 to V5 |
to |
Input |
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––– |
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Can be adjusted by addition of external resistor. |
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VIN(–) |
224 |
Input |
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––– |
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Liquid crystal drive power supply OP-amp input pins |
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VIN(+) |
223 |
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VCC, GND1 |
232, 256 |
––– |
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Logic power supply, GND |
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VDD, GND2 |
257, 222 |
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Liquid crystal drive (step-up) power supply, GND |
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Drive voltage selection pin |
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236 |
Input |
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“1” → VDD = 3 V (×4 step-up circuit selected) |
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3/5 |
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“0” → VDD = 5 V (×2 step-up circuit selected) |
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C1±, C2±, |
230 to |
––– |
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A 1 μF tantalum or ceramic capacitor should be connected |
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C3± |
225 |
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externally. |
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REFERENCE CLOCK |
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Product Name |
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Reference Clock |
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μPD16435 |
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External input |
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μPD16435A |
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On-chip oscillation circuit (External crystal resonator) |
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OSC CIRCUIT (μPD16435A)
OSC1 |
OSC2 |
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4.19 MHz |
5
μPD16435, 16435A
REGISTER FUNCTIONS
(1) Address Register
Sets the address of each register, and also sets display control, standby mode, and scaler resetting.
MSB |
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LSB |
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× : Don’t Care |
b7 |
b6 |
b5 |
b4 |
b3 b2 b1 b0 |
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Register address (0H to CH) |
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See table below |
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Display control |
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00: Display control off (SEGn, COMn = V1) |
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01: Display control off (SEGn, COMn = unselected waveform) |
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10: Normal operation |
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11: Normal operation |
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Standby mode setting |
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0: Normal operation |
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1: Standby modeNote |
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Blink internal scaler reset and 1/2 scaler reset |
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0: Normal operation |
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1: Reset (Blinking starts when it lights.) |
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(Used to synchronize time variations and time mark blinking.) |
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Note Standby mode = |
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DC/DC converter stopped |
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OSC1 input invalid ( μPD16435) |
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OSC stopped ( μPD16435A) |
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SEGn, COMn = V1 |
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Data write/read prohibited |
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After powering on |
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0 |
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0 |
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0 |
0 |
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0 |
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0 |
0 |
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Register address list |
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Address |
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Register Name |
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b3 |
b2 |
b1 |
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b0 |
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0 |
0 |
0 |
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0 |
Full-dot X address register |
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0 |
0 |
0 |
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1 |
Full-dot Y address register |
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0 |
0 |
1 |
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0 |
Full-dot data register |
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0 |
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1 |
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1 |
Character X address register |
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0 |
1 |
0 |
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0 |
Character Y address register |
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0 |
1 |
0 |
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1 |
Character data register |
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0 |
1 |
1 |
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0 |
CGRAM address register |
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0 |
1 |
1 |
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1 |
CGRAM data register |
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1 |
0 |
0 |
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0 |
Extension register |
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1 |
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0 |
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1 |
Extension register X address register |
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1 |
0 |
1 |
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0 |
Extension register Y address register |
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1 |
0 |
1 |
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1 |
Scroll register |
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1 |
1 |
0 |
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0 |
Control register |
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6
μPD16435, 16435A
(2) Full-Dot X Address Register (Register Address = 0000B)
Performs full-dot display, display screen X (segment) direction address setting. As scrolling is not possible with a fulldot display, addresses are not allocated to the scroll RAM area.
MSB |
LSB |
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b3 |
b2 |
b1 b0 |
× : Don’t Care |
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Full-dot X address (00H to 0EH)
After powering on: Undefined
(3) Full-Dot Y Address Register (Register Address = 0001B)
Performs full-dot display, display screen Y (common) direction address setting.
MSB |
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LSB |
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× : Don’t Care |
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b6 |
b5 |
b4 |
b3 b2 b1 b0 |
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Full-dot Y address (00H to 48H)
After powering on: Undefined
(4) Full-Dot Data Register (Register Address = 0010B)
Inputs full-dot display data. Display data is stored in the display memory with the MSB on the left, and display data “1” corresponds to illumination.
Full-dot X address = 00H to 0DH |
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MSB |
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LSB |
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b7 |
b6 |
b5 |
b4 |
b3 |
b2 |
b1 |
b0 |
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Full-dot display data |
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Full-dot X address = 0EH |
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MSB |
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LSB |
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× : Don’t Care |
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b7 |
b6 |
b5 |
b4 |
b3 |
b2 |
b1 |
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Full-dot display data
After powering on: Undefined
7
μPD16435, 16435A
Y Address
Full-Dot X Address and Y Address Allocation
X Address
00H(1) |
01H(2) |
0EH(15) |
00H(1)
01H(2)
48H(73)
b7 |
b6 |
b5 |
b4 |
b3 |
b2 |
b1 |
b0 |
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b7 |
b6 |
b5 |
b4 |
b3 |
b2 |
b1 |
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8 Bits |
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7 Bits |
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(5) Character X Address Register (Register Address = 0011B)
Performs character display display, screen X (segment) direction address setting. X addresses include the scroll RAM
area.
MSB |
LSB |
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× : Don’t Care |
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b4 |
b3 |
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b1 b0 |
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Character X address (00H to 15H)
After powering on: Undefined
(6) Character Y Address Register (Register Address = 0100B)
Performs character display display, screen Y (common) direction address setting.
MSB |
LSB |
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b2 |
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b0 |
× : Don’t Care |
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Character Y address (00H to 07H)
After powering on: Undefined
8
μPD16435, 16435A
(7) Character Data Register (Register Address = 0101B)
The character indicated in the character code table is displayed at the position indicated by the character X and Y address
registers.
MSB |
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LSB |
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× : Don’t Care |
b7 |
b6 |
b5 |
b4 |
b3 b2 b1 b0 |
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Character code
After powering on: Undefined
Character X Address and Y Address Allocation
X Address
Y Address
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Scroll |
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Display RAM Area |
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RAM Area |
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14H |
15H |
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00H(1) |
01H(2) |
13H(20) |
(21) |
(22) |
00H(1)
01H(2)
1 Bit
07H(8) |
8 Bits |
5 Bits
1 Bit
9
μPD16435, 16435A
(8) CGRAM Address Register (Register Address = 0110B)
Performs address setting when display data is written to CGRAM. Bits b6 to b3 of the CGRAM address indicate the character code, and bits b2 to b0 indicate the character line.
MSB |
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× : Don’t Care |
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b6 |
b5 |
b4 |
b3 b2 b1 b0 |
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Line address (00H to 06H)Note
Character code (00H to 0FH)
Note If auto increment is set with the control register, 06H is followed by 07H. Dummy data should be sent when the address is 07H.
Example: (CGRAM address with auto increment)
--- → 15H → 16H → 17H → 18H → ---
After powering on: Underfined
(9) CGRAM Data Register (Register Address = 0111B)
CGRAM display data. The lower 5 bits of the write data are valid.
MSB |
LSB |
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× : Don’t Care |
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b4 |
b3 |
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b1 b0 |
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CGRAM data
After powering on: Undefined
10
μPD16435, 16435A
(10) Extension Register (Register Address = 1000B)
Performs magnification, reverse, cursor, and time mark setting.
MSB |
LSB |
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b3 |
b2 |
b1 b0 |
× : Don’t Care |
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In case of magnification setting 00: Standard
01: ×2 horizontal
10:×2 vertical
11:×4 magnification (×2 horizontal & vertical)
Magnification display is performed at any line position; characters of different sizes cannot be displayed on the same line.
Line specification magnification display is possible by setting an extension Y address after this command, and multiple-line magnification display is possible by setting consecutive extension Y address.
In case of reverse setting
00: Reverse cancellation (line specification) 01: Reverse (line specification)
10:Reverse cancellation (full screen)
11:Reverse (full screen)
Line specification reverse display is possible by setting an extension Y address after this command, and multiple-line reverse display is possible by setting consecutive extension Y addresses.
Regarding the reverse display Y address direction, a total of 9 dots (7 character part dots + 1 cursor part dot + 1 top space dot) are reversed.
In the case of ×2 vertical magnification or ×4 magnification, a total of 18 dots (14 character part dots + 2 cursor part dots + 2 top space dots) are reversed.
In case of cursor setting 00: Cursor non-display
01: Cursor display (blinking stopped)
10:Cursor display (blink operation)
11:Don’t Care
Blinking display can be performed at any address by specifying an extension X and Y address after this command. The specification is for one address only.
The address specification should be performed in the order: X address → Y address.
In case of character blink setting
X0: Blinking stopped
X1: Blink operation
Blinking can be performed at any address by specifying an extension X and Y address after this command. The specification is for one address only.
The address specification should be performed in the order: X address → Y address.
Extension function setting 00: Magnification setting
01: Reverse setting
10:Cursor setting
11:Character blink setting
After powering on
0 0 0 0
11