NEC PD161644A Technical data

PRELIMINARY PRODUCT INFORMATION

MOS INTEGRATED CIRCUIT

PD161644A

241 OUTPUT GATE DRIVER WITH POWER SUPPLY FOR TFT-LCD GATE DRIVER

DESCRIPTION

The PD161644A is a TFT-LCD gate driver with power supply for TFT-LCD driver. Because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input. This ICs can generate the levels which TFT-LCD driver need, from 2.7 V.

FEATURES

•High breakdown voltage output (VDD1–VSS3 = 40 V MAX.)

•2.7 V CMOS level input

•Number of output: 241 output selectable

•To generate 4 levels from single voltage input

•To integrate regulator circuit for source driver

•Mode setting from source driver: Serial I/F or pin control

•On-chip VCOM driver

•On-chip gate output low-level selector

ORDERING INFORMATION

Part number	Package
PD161644A	Chip

Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.

The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. S16027EJ0V9PM00 (0.9th edition) Date Published April 2002 NS CP(K)

Printed in Japan

© 2001

PD161644A

1. BLOCK DIAGRAM/SYSTEM DIAGRAM

C1

C1

C2

C2

C2

C2

C1+
C1-			DC/DC converter		VDD2
C2+				VDC	C2
C2-
C3+					VDD1
C3-					C2
C4+					VSS2
C4	-		DC/DC converter		C2
					VSS3
C5+
					C2
C5-
C6+			DC/DC converter		VSS4
C6-				VDC	C2
					VGD
DCCLK		OSC		Regurator	VR
GCS				VR		C2
		Serial I/F
GCL
		register			VS
GDA			VREF	Regurator			Source driver
				VR	MVS	C3		5V
								4V
DCON
RGONR
VCD2			D/A		VCIN		Source driver
VMS					VCOM
				Common			Common
FS0
					COMH
				driver
FS2
			D/A	circuit	C2
CLS0					COML
RGON		Switch			C2
					VCOMIN
VSEL
EXRV
ACS0			Gate output
SCN0			low level select circuit		VM
SCN1
SCN2					IFSEL
PUPT0
					/GRESET
DUPF0
R,/L
CLK
FRM		SR1 SR2	SR119 SR120 SR121 SR122	SR240 SR241	STVL
STVR
			MPX
OE1
OE2					VMON
					TESTIN1
VDC					TESTIN2
VCC1
VSS1					TESTOUT1
PVCC1			Level Shifter		TESTOUT2
PVSS1					VB
PVSS3

O1 O2

O119 O120

O122 O122

O240 O241

Remarks 1. /xxx indicates active low signal.

2.Level Shifter (LS): Interfaces between 2.7 V CMOS level and VT to VB level.

2	Preliminary Product Information S16027EJ0V9PM

PD161644A

1.1 Boost Voltage Construction

The boost voltage generated in PD161644A is shown below.

VGD=VR			VDD1=VR x 3	VGD=VDD2
			=15V
	VDD2 : 5.4V
VDC: 2.7V			VR: 5V	VDC 2.7V
VSS1: 0V			VSS4=VDC x -1	VSS1 0V
			=-2.7V
			VSS2=VR x -2
			=-10v
			VSS3=VR x -3
			=-15v

VDD1=VDD2 x 3 =16.2V

VDD2 5.4V

VR 5V

VSS4=VDC x -1 =-2.7V

VSS2=VDD2 x -2 =-10.8V VSS3=VDD2 x -3 =-16.2V

1.2 Boost Voltage Auto Start and Rising Order

VGD=VR, VCD2=H	VDD1=3 x VR

VDD2=3 x VDC

VR

DCON

VSS1

VSS4=-VDC

T1

T2

T3

T4

VSS2=-2 x VR

VSS3=-3 x VR

T1,T2,T3,T4: changeable by PUPT0/1, DUPF0/1

1.3 VS_AMP Circuit

Vs_AMP circuits are shown below.

TESTOUT1			VDD2		TESTOUT1			VDD2
VREF	−		C3		VREF	−		C3
MVS	+	VS	5V		MVS	+	VS	5V
			4V					4V
RbS			C3	RbS	RaS			C3
	RcS
RaS
					External Resistor Mode
					EXRV=H
Internal Resistor Mode					VS=(1+	RbS	)VREF
EXRV=L
						RaS

Preliminary Product Information S16027EJ0V9PM

3

PD161644A

1.4 Common Drive Circuit

The common drive circuit is shown below.

		VS			VDD2
				+
CDA0						COMH
CDA1			Vs
CDA2		+		−		C3
CDA3	D/A
CDA4
CDA5		−
CDA6						VCOM
CDA7					LS
VCOMIN	VS				VCC1
				+
						COML
DA0				−		C3
DA1			Vs
DA2					VSS4
DA3	D/A	+				VCIN
DA4
DA5		−
DA6
DA7

1.5 Variable Boost Steps

The boost steps of VDD1, VSS2, VSS3 are selected according to how the external capacitor is connected.

The examples of connection are shown below. VS is selected as a boost reference voltage in these examples (short between the VS and VGD pins).

VDD2 = VDC x 3

C1+

C1VDD2

C2+

C2-

VDD1= VGD x 3

VSS2 = VGD x -2

VSS3 = VGD x -3

			C3+	VDD1
			C3-
			C4+	VSS2
			C4-
			C5+
				VSS3
			C5-

VSS4=VDC x -1

C6+ VSS4 C6-

VDD2 = VDC x 2 (dual mode)

C1+

C1VDD2

C2+

C2-

VDD1= VGD x 3 VSS2 = -

VSS3 = VGD x -2

C3+ VDD1

C3-

C4+ VSS2

C4-

C5+ VSS3

C5-

VSS4= -

C6+ VSS4 C6-

VDD2 = VDC x 2 (single mode)

C1+

C1- VDD2

C2+

C2-

VDD1= VGD x 2 VSS2 = VGD x -1 VSS3 = VGD x -2

C3+ VDD1

C3-

C4+ VSS2

C4-

C5+ VSS3

C5-

VDD1= VGD x 2 VSS2 = -

VSS3 = VGD x -1

C3+ VDD1

C3-

C4+ VSS2

C4-

C5+ VSS3

C5-

4	Preliminary Product Information S16027EJ0V9PM

PD161644A

2. PIN CONFIGURATION (Pad Layout)

Chip size: 2.8 mm x 9.4 mm
Bump size
Input/Left/Right (includes DUMMY of input side)	: 100 m x 40 m
Output (includes DUMMY output side)	: 86 m x 35 m

Alignment Mark Coordinate (mark center, unit: mm)

X	Y	Shape of Alignment Mark
−1.125	−4.5705	Type A
0.9705	4.5495	Type B
0.9705	−4.5495	Type B

Alignment Mark

Type A

Type B

10 m 10 m 10 m

30 m 30 m 30 m

10 m

30 m

10 m

30 m

10 m

30 m

Preliminary Product Information S16027EJ0V9PM

5

PD161644A

Table 2-1 Pad Layout (1/4)

6	Preliminary Product Information S16027EJ0V9PM

PD161644A

Table 2-1 Pad Layout (2/4)

Preliminary Product Information S16027EJ0V9PM

7

PD161644A

Table 2-1 Pad Layout (3/4)

8	Preliminary Product Information S16027EJ0V9PM

PD161644A

Table 2-1 Pad Layout (4/4)

Preliminary Product Information S16027EJ0V9PM

9

					PD161644A
	3. PIN FUNCTIONS
					(1/5)
	Symbol	Pin Name	Pad No.	I/O	Function
	O1 to O241	Driver output pins	388 to 148	Output	Scan signal output pins that drive the gate electrode of a TFT-
					LCD.
					The status of each output pin changes in synchronization with
					the rising edge of shift clock CLK. The output voltage of the
					driver is VDD1 to VB.
	CLK	Shift clock input	139	Input	Shift clock input for the internal shift resistor. The contents of
					internal shift resistor are shifted at the rising edge of CLK.
					Connect to GCLK pin of source driver.
	STVR,	Start pulse	136,	I/O	Input/output pin of the internal shift resistor.
	STVL	input/output pin	137		Start pulse signal (output from GSTB pin of source driver) is
					read at the rising edge of shift clock CLK and a scan signal is
					output from the driver output pin.
					The valid level of the STVR/STVL pin is determined by the
					setting of STVSEL.
					When STVSEL = L, the pulse becomes low level at the falling
					edge of the 240th shift clock CLK and high level at falling
					edge of the 241st clock.
	OE1	Enable input	140	Input	If the level selected by OE1SEL is input, the driver output is
					fixed to low level. (When OE1SEL = L the driver output is fixed
					to low level if a low level is input.)
					However, the shift resistor is not cleared. And, output enable
					actuation is asynchronous in the clock.
					Connect to GOE1 pin of source driver.
	OE2	Enable input	141	Input	If the level selected by OE2SEL is input, the driver output is
					fixed to high level. (When OE2SEL = L the driver output is fixed
					to low level if a high level is input.)
					However, the shift resistor is not cleared. And, output enable
					actuation is asynchronous in the clock.
					Connect to GOE2 pin of source driver.
	R,/L	Shift direction	25	Input	Shift direction switching input pin of the internal shift register.
		switching			R,/L = 1 (right shift): STVR →O1 →O2 ··· O239 →O240 →STVL
		input			R,/L = 0 (left shift): STVL →O241 →O240 ··· O2 →O1 →STVR
	FRM	Frame signal	129	Input	Input frame reverse signals.
		input			Connect to GFRAME pin of source driver.
	GCS	Chip select input	133	Input	<IFSEL = 0> To input chip select signals.
					Connect to GCS pin of source driver.
					<IFSEL = 1> Leave open.
	GCL	Serial clock input	134	Input	<IFSEL = 0> To input serial clock signals.
					Connect to GCL pin of source driver.
					<IFSEL = 1> Leave open.

10	Preliminary Product Information S16027EJ0V9PM

PD161644A

(2/5)

Symbol	Pin Name	Pad No.	I/O	Function
GDA	Serial data input	135	Input	<IFSEL = 0> To input serial data signals.
				Connect to GDA pin of source driver.
				<IFSEL = 1> Leave open.
/GRESET	Reset input	132	Input	Reset input pin. Connect to /GRESET pin of source driver.
				If /GRESET is made low, the serial interface is initialized (the
				register values are not initialized). A reset operation is
				executed according to the level of the /GRESET signal. Be
				sure to execute a reset using this pin at power application.
VCIN	Common pulse	130	Input	To input common pulse. Connect to VCOUT3 pin of source
	input			driver. Fix this pin to low when not using it.
DCCLK	Clock input for	138	Input	To input the external clock for the DC/DC converter.
	DC/DC converter			This pin is valid only when CLS0 = 1 and CLS1 = 1. Other
				settings cause this pin to be pulled down to low level, so in
				these cases, leave open.
VGD	Power supply input	114 to 116	Input	Reference voltage input pins for VDD1, VSS1 to VSS4 boost.
	for DC/DC			Connect to any of VDD2, VR or VS.
	converter
VR	Power supply	111 to 113	Output	Positive power supply voltage output for the DC/DC converter.
	output for DC/DC			The VR output voltage can be changed by setting VRSEL0 to
	converter			VRSEL2.
VS	Positive power	118 to 123	Output	Positive power supply voltage output for source driver. The VS
	output supply for			output voltage can be changed by setting VSEL0 to VSEL2.
	driver
MVS	External resistor	117	Input	Any output voltage can be set by connecting an external
	input			resistor.
				<EXRV = 0> Leave open.
				<EXRV = 1> Connect to external resistor.
C1 +, C1 −	Capacitor connect	80 to 83, 76 to 79,	−	To connect booster for DC/DC converter.
C2 +, C2 −	pin for boost	72 to 75, 68 to 71,		The recommended values of the capacitance and tolerance of
C3 +, C3 −		63, 64, 61, 62,		each capacitor are shown below.
C4 +, C4 −		59, 60, 57, 58,		Capacitance : C1, C2: 1 F, C3 to C6: 0.47 F
C5 +, C5 −		55, 56, 53, 54,		Tolerance : 10 V
C6 +, C6 −		51, 52, 49, 50
VDD1	DC/DC converter	65 to 67	Output	Boost voltage of DC/DC converter (VR x2 or x3).
	output			The boost step number of VDD1 is selected according to how
				the external capacitor is connected. The boost reference
				voltage can be set using VGD. Refer to the function of VGD
				pin.
VDD2	DC/DC converter	84 to 87	Output	Boost voltage of DC/DC converter (VDC x2 or x3). The boost
	output			step number for VDD2 can be set using VCD2.
VSS2	DC/DC converter	46 to 48	Output	Boost voltage of DC/DC converter (VR x-1 or x-2).
	output			The boost step number of VSS2 is selected according to how the
				external capacitor is connected. The boost reference voltage
				can be set using VGD. Refer to the function of VGD pin.

Preliminary Product Information S16027EJ0V9PM

11

					PD161644A
					(3/5)
	Symbol	Pin Name	Pad No.	I/O	Function
	VSS3	DC/DC converter	40 to 42, 143	Output	Boost voltage of DC/DC converter (VR x-1 or x-2).
		output			The boost step number of VSS2 is selected according to how
					the external capacitor is connected. The boost reference
					voltage can be set using VGD. Refer to VGD pin function.
	VSS4	DC/DC converter	43 to 45	Output	Boost voltage output of DC/DC converter (VDC x-1).
		output
	COMH	Common high level	34, 35	Output	<COMON = 1> High level of common voltage is output. The
		output			voltage level changes accordance with DA0 to DA7 and CDA0
					to CDA7.
					<COMON = 1> Leave open when not using it.
	COML	Common low	32, 33	Output	<COMON = 1> Low level of common voltage is output. The
		level output			voltage level changes accordance with DA0 to DA7 and CDA0
					to CDA7.
					<COMON = 0> Leave open when not using it.
	VCOM	Common output	29 to 31	Output	<COMON = 1> The common voltage synchronized with the
					VCIN input is output. Connect to common pin of panel.
					<COMON = 0> Leave open when not using it.
	VM	Gate output low	36, 37	Output	Gate output low level select voltage synchronized with the
		level select			VCIN input is output. Connect to VB pin.
		voltage
	VB	Driver negative	38, 39	Input	Negative voltage of output buffer. This is the input pin of the
		voltage			liquid crystal driver negative voltage. Connect to VM pin.
	IFSEL	I/F selection	26	Input	The serial I/F input switching pin.
					<IFSEL = 0> Serial I/F input.
					The DCON, RGONR, VCD2, VMS, FS0, FS2, CLS0, RGON,
					VSEL, EXRV, ACS0, SCN0, SCN0, SCN2, PUPT0, DUPF0
					pins should be left open.
					<IFSEL = 1> Control pin input.
					The GCS, GCL, GDA pins should be left open.
	DCON	DC/DC converter	128	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
		control			<IFSEL = 1> The DC/DC converter ON/OFF control signal is
					input. Connect to the DCON pin of the source driver.
					<DCON = 0> DC/DC converter OFF.
					<DCON = 1> DC/DC converter ON.
	RGONR	VR regulator	19	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
		control			<IFSEL = 1> The VR regulator ON/OFF control signal is input.
					<RGONR = 0> VR regulator OFF.
					<RGONR = 1> VR regulator ON.
	VCD2	VDD2 boost	126	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
		selection			<IFSEL = 1> The VDD2 boost step number select pin.
					<VCD2 = 0> VDD2 = VDC x 2.
					<VCD2 = 1> VDD2 = VDC x 3.

12	Preliminary Product Information S16027EJ0V9PM

PD161644A

(4/5)

Symbol	Pin Name	Pad No.	I/O	Function
VMS	VDD2 boost	18	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	selection			<IFSEL = 1> VDD2 boost mode select pin.
				<VMS = 0> VDD2: single boost mode
				<VMS = 1> VDD2: dual boost mode
VCOMIN	VCOM center	28	Input	VCOM center voltage input pin.
	voltage input			Leave open when COMSEL = 0.
				<COMSEL = 0> Internal D/A is valid.
				<COMSEL = 1> VCOMIN input voltage is valid.
FS0	VDD2 boost	17	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	frequency			<IFSEL = 1> VDD2 boost frequency select pin in scan mode
	selection in scan			<FS0 = 0 > fOSC/2 <FS0 = 0 > fOSC/4
	mode
FS2	VDD1, VSS2 to	16	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	VSS4 boost			<IFSEL = 1> VDD1, VSS2 to VSS4 boost frequency select pin in
	frequency			scan mode.
	selection in scan			<FS2 = 0 > fOSC/2 <FS2 = 1, > fOSC/4
	mode
CLS0	DC/DC OSC	15	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	frequency			<IFSEL = 1> Select pin of the OSC oscillation frequency for
	selection			DC/DC converter.
				<CLS0 = 0> fOSC = 20 kHz, DCCLK: Open
				<CLS0 = 1> External CK input mode
RGON	VS regulator	127	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	control			<IFSEL = 1> The VS regulator ON/OFF control signal is input.
				Connect this pin to the RGON pin of the source driver.
				<RGON = 0> VS regulator OFF.
				<RGON = 1> VS regulator ON.
VSEL	VS regulator voltage	14	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	selection			<IFSEL = 1> Select pin of output voltage for VS regulator.
				<VSEL = 1> VS = 4 V
				<VSEL = 0> VS = 5 V
EXRV	VS regulating	13	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	resistor			<IFSEL = 1> Select pin of external resistor for VS regulator.
	selection			<EXRV = 0> Internal resistor setting mode.
				<EXRV = 1> Any output voltage can be set by connecting
				MVS to an external resistor
ACS0	Amp. current	12	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	selection in scan			<IFSEL = 1> Amp. current select pin in scan mode.
	mode			<ACS0 = 0> Amp. current = 5 A.
				<ACS0 = 1> Amp. current = 15 A

Preliminary Product Information S16027EJ0V9PM

13

					PD161644A
					(5/5)
	Symbol	Name	Pad No.	I/O	Function
	SCN0,	Gate scan	11,	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
	SCN1,	selection	10,		<IFSEL = 1> Select pin of Gate scan order.
	SCN2		9		<SCN0 = 1, SCN1 = 1, SCN2 = 1> MODE1
					<SCN0 = 1, SCN1 = 1, SCN2 = 0> MODE2
					<SCN0 = 1, SCN1 = 0, SCN2 = 1> MODE3
					<SCN0 = 1, SCN1 = 0, SCN2 = 0> MODE4
					<SCN0 = 0, SCN1, SCN2 = x> MODE5
	PUPT0	Setting pin of	8	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
		DC/DC converter			<IFSEL = 1> This pin sets the rising time of VDD1, VDD2, VSS2
		power on time			to VSS4 at DC/DC converter power on time.
	DUPF0	Operating	7	Input	<IFSEL = 0> Leave open. (Internal resistors are valid.)
		frequency setting			<IFSEL = 1> This pin sets the operating frequency at DC/DC
		pin at DC/DC			converter power on time.
		converter power			<DUPT0 = 0> fOSC/8
		on			<DUPT0 = 0> fOSC/16
	VMON	Stand-by current	22	Input	The standby current reduction control pin.
		reduction control			<VMON = PVSS3> Normal mode
		pin			A quiescent current of about 0.5 A is consumed in standby
					mode. When the VCC1 voltage drops, the driver output pins
					are fixed to ALL-High.
					<VMON = PVCC1> Standby current reduction mode
					Makes the quiescent current consumed in standby mode 0.
					When the VCC1 voltage drops, the driver output pins are
					undefined.
	TESTOUT1	VREF reference	5	Output	The VREF voltage measurement pin.
		voltage output			Leave open.
	VDC	DC/DC converter	93 to 100	−	Reference voltage input pin for DC/DC converter.
		reference voltage
	VCC1	Logic reference	101 to 104	−	2.7 V ± 5% LS: level shifter reference voltage input pins.
		voltage
	VSS1	Ground	105 to 110	−	Connect to the system ground.
	PVCC1	Pull-up voltage	6, 24, 125	−	Pull-up voltage for mode setting pins.
	PVSS1	Pull-down voltage	20, 27, 131	−	Pull-down voltage for mode setting pins.
	TESTIN1,	TEST input pin	4,	Input	Test input pins. Leave open.
	TESTIN2		3
	TESTOUT2	TEST output pin	2	Output	Test output pin. Leave open.
	PVSS3	Pull-down voltage	21	−	Pull-down voltage for mode setting pin.
	DUMMY	Dummy	1, 23, 92, 124,	−	Dummy data
			142, 144 to 147,
			389 to 391

14	Preliminary Product Information S16027EJ0V9PM

PD161644A

4. COMMAND

4.1 Command List

													Data bit
7	6	5	4	3	2	1	0		Register	7	6	5	4	3	2	1	0
0	0	0	1	1	0	0	0	R24	DC/DC operation		RGONR	VS4ON	VS3ON	VS2ON	VD2ON	VD1ON	DCON
									setting
0	0	0	1	1	0	0	1	R25	DC/DC step setting				VRSEL2VRSEL1		VRSEL0	VMS	VCD2
0	0	0	1	1	0	1	0	R26	DC/DC oscillation		FUP	CLS1	CLS0	FS3	FS2	FS1	FS0
									setting
0	0	0	1	1	0	1	1	R27	Regulator output setting		ACS1	ACS0	EXRV	VSEL2	VSEL1	VSEL0	RGON
0	0	0	1	1	1	0	0	R28	LPM setting		LACS1	LACS0	LFS3	LFS2	LFS1	LFS0	LPM
0	0	0	1	1	1	0	1	R29	Gate scan setting			OE2SEL	OE1SELSTVSEL		SCN2	SCN1	SCN0
0	0	0	1	1	1	1	0	R30	Gate mode setting				COMHI COMSEL		COMON	NLINE2	NLINE1
0	0	0	1	1	1	1	1	R31	Common amplitude	DA7	DA6	DA5	DA4	DA3	DA2	DA1	DA0
									setting
0	0	1	0	0	0	0	0	R32	Common center setting	CDA7	CDA6	CDA5	CDA4	CDA3	CDA2	CDA1	CDA0
0	0	1	0	0	0	0	1	R33	DC/DC power on setting			PONM	PON	DUPF1	DUPF0	PUPT1	PUPT0
0	0	1	0	0	0	1	0	R34	Reset								RES

4.2 Command Description

Reset the internal data at power application by inputting a low level to the /GRESET pin.

(1/3)

Resistor	Bit	Symbol	Reset	Functions	Descriptions
R24	D0	DCON	0	DC/DC converter control	Control ON/OFF of DC/DC converter
					<DCON = 0> DC/DC converter OFF
					<DCON = 1> DC/DC converter ON
	D1	VD1ON	0	VDD1 boost control	Control ON/OFF of VDD1 boost
					<VD1ON = 0> VDD1 boost OFF
					<VD1ON = 1> VDD1 boost ON
	D2	VD2ON	0	VDD2 boost control	Control VDD2 boost ON/OFF
					<VD2ON = 0> VDD2 boost OFF
					<VD2ON = 1> VDD2 boost ON
	D3	VS2ON	0	VSS2 boost control	Control VSS2 boost ON/OFF.
					<VS2ON = 0> VSS2 boost OFF
					<VS2ON = 1> VSS2 boost ON
	D4	VS3ON	0	VSS3 boost control	Control VSS3 boost ON/OFF.
					<VS3ON = 0> VSS3 boost OFF
					<VS3ON = 1> VSS3 boost ON
	D5	VS4ON	0	VSS4 boost control	Control VSS4 boost ON/OFF.
					<VS4ON = 0> VSS4 boost OFF
					<VS4ON = 1> VSS4 boost ON
	D6	RGONR	0	VR regulator control	Control ON/OFF of VR regulator
					<RGON = 0> VR regulator OFF
					<RGON = 1> VR regulator ON

Preliminary Product Information S16027EJ0V9PM

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