NEC PD161644A Technical data
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µµµµ
PD161644A
241 OUTPUT GATE DRIVER WITH POWER SUPPLY FOR TFT-LCD GATE DRIVER
DESCRIPTION
The µPD161644A is a TFT-LCD gate driver with power supply for TFT-LCD driver. Because this gate driver has a
level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input. This
ICs can generate the levels which TFT-LCD driver need, from 2.7 V.
FEATURES
• High breakdown voltage output (VDD1–VSS3 = 40 V MAX.)
• 2.7 V CMOS level input
• Number of output: 241 output selectable
• To generate 4 levels from single voltage input
• To integrate regulator circuit for source driver
• Mode setting from source driver: Serial I/F or pin control
• On-chip VCOM driver
• On-chip gate output low-level selector
ORDERING INFORMATION
Part number Package
µ
PD161644A Chip
Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or
product quality, so please contact one of our sales representatives.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S16027EJ0V9PM00 (0.9th edition)
Date Published April 2002 NS CP(K)
Printed in Japan
©
2001
1. BLOCK DIAGRAM/SYSTEM DIAGRAM
C1
C1
C2
C2
C2
C2
C1
C1
C2
C2
C3
C3
C4
C4
C5
C5
C6
C6
DCCLK
GCS
GCL
GDA
DCON
RGONR
VCD2
VMS
FS0
FS2
CLS0
RGON
VSEL
EXRV
ACS0
SCN0
SCN1
SCN2
PUPT0
DUPF0
R,/L
CLK
FRM
STVR
+
-
+
-
+
-
+
-
+
-
+
-
OSC
DC/DC converter
DC/DC converter
DC/DC converter
Serial I/F
register
Switch
SR2SR1
SR120SR119
VREF
D/A
D/A
Gate output
low level select circuit
SR121
SR122
Regurator
R
V
Regurator
R
V
Common
driver
circuit
SR240 SR241
µµµµ
PD161644A
V
DD2
V
DC
C2
V
DD1
C2
V
SS2
C2
V
SS3
C2
V
SS4
V
DC
VGD
V
R
C2
C2
V
S
MVS
VCIN
VCOM
Source driver
C3
5V
4V
Source driver
Common
COMH
C2
COML
C2
VCOMIN
VM
IFSEL
/GRESET
STVL
MPX
OE1
PV
PV
PV
OE2
V
V
V
DC
CC1
SS1
CC1
SS1
SS3
O1O
Level Shifter
2
O
119O120
O
122
O
122
O
O
240
241
VMON
TESTIN1
TESTIN2
TESTOUT1
TESTOUT2
V
B
Remarks 1. /xxx indicates active low signal.
2. Level Shifter (LS): Interfaces between 2.7 V CMOS level and V
2
Preliminary Product Information S16027EJ0V9PM
T to VB level.
1.1 Boost Voltage Construction
The boost voltage generated in
µ
PD161644A is shown below.
VGD=VR VGD=VDD2
VDD2 : 5.4V
VDC: 2.7V
VSS1: 0V
VR: 5V
VDD1=VR x 3
=15V
VSS4=VDC x -1
=-2.7V
VSS2=VR x -2
=-10v
VSS3=VR x -3
=-15v
1.2 Boost Voltage Auto Start and Rising Order
VGD=VR, VCD2=H
VDD1=3 x V
R
VDC：2.7V
VSS1：0V
VDD2：5.4V
µµµµ
PD161644A
VDD1=VDD2 x 3
=16.2V
VR：5V
VSS4=VDC x -1
=-2.7V
VSS2=VDD2 x -2
=-10.8V
VSS3=VDD2 x -3
=-16.2V
T1 T2 T3 T4
T1,T2,T3,T4: changeable by PUPT0/1, DUPF0/1
1.3 V
S_AMP Circuit
Vs_AMP circuits are shown below.
TESTOUT1
−
+
RcS
MVS
V
REF
RbS
RaS
VDD2=3 x VDC
VR
DCON
VSS1
VSS4=-VDC
VSS2=-2 x VR
VSS3=-3 x VR
V
DD2
C3
5V
V
S
4V
C3
RbS RaS
MV
S
TESTOUT1
V
REF
−
+
V
DD2
C3
5V
V
S
4V
C3
External Resistor Mode
Internal Resistor Mode
EXRV=L
EXRV=H
RbS
S=(1+ )VREF
V
RaS
Preliminary Product Information S16027EJ0V9PM
3
1.4 Common Drive Circuit
The common drive circuit is shown below.
µµµµ
PD161644A
VCOMIN
CDA0
CDA1
CDA2
CDA3
CDA4
CDA5
CDA6
CDA7
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
D/A
VS
D/A
VS
Vs
+
−
Vs
+
−
VDD2
+
−
LS
COMH
C3
VCOM
VCC1
+
−
VSS4
COML
C3
VCIN
1.5 Variable Boost Steps
The boost steps of VDD1, VSS2, VSS3 are selected according to how the external capacitor is connected.
The examples of connection are shown below. V
between the V
S and VGD pins).
S is selected as a boost reference voltage in these examples (short
VDD2 = VDC x 3
VDD2 = VDC x 2 VDD2 = VDC x 2
(dual mode)
(single mode)
C1+
VDD2
C1-
C2+
C2-
VDD1= VGD x 3
VSS2 = VGD x -2
VSS3 = VGD x -3
C3+
VDD1
C3-
C4+
VSS2
C4-
C5+
VSS3
C5-
VSS4=VDC x -1
+
C6
VSS4
C6-
C1+
C1-
VDD2
C2+
C2-
VDD1= VGD x 3
VSS2 = VSS3 = VGD x -2
C3+
VDD1
C3-
C4+
VSS2
C4-
C5+
VSS3
C5-
VSS4= -
C6+
VSS4
C6-
C1+
VDD2
C1-
C2+
C2-
VDD1= VGD x 2
VSS2 = VGD x -1
VSS3 = VGD x -2
C3+
VDD1
C3-
C4+
VSS2
C4-
C5+
VSS3
C5-
VDD1= VGD x 2
VSS2 = VSS3 = VGD x -1
C3+
VDD1
C3-
C4+
VSS2
C4-
C5+
VSS3
C5-
4
Preliminary Product Information S16027EJ0V9PM
2. PIN CONFIGURATION (Pad Layout)
Chip size: 2.8 mm x 9.4 mm
Bump size
Input/Left/Right (includes DUMMY of input side) : 100
Output (includes DUMMY output side) : 86
Alignment Mark Coordinate (mark center, unit: mm)
X Y Shape of Alignment Mark
−1.125 −4.5705 Type A
0.9705 4.5495 Type B
0.9705 −4.5495 Type B
Alignment Mark
Type A Type B
µ
m x 40 µm
µ
m x 35 µm
µµµµ
PD161644A
10 µm10 µm 10 µm
m
10
µ
µ
m
10
m
10
µ
30 µm30 µm 30 µm
m
30
µ
µ
m
30
m
30
µ
Preliminary Product Information S16027EJ0V9PM
5
Table 2-1 Pad Layout (1/4)
µµµµ
PD161644A
6
Preliminary Product Information S16027EJ0V9PM
Table 2-1 Pad Layout (2/4)
µµµµ
PD161644A
Preliminary Product Information S16027EJ0V9PM
7
Table 2-1 Pad Layout (3/4)
µµµµ
PD161644A
8
Preliminary Product Information S16027EJ0V9PM
Table 2-1 Pad Layout (4/4)
µµµµ
PD161644A
Preliminary Product Information S16027EJ0V9PM
9
µµµµ
PD161644A
3. PIN FUNCTIONS
Symbol Pin Name Pad No. I/O Function
O1 to O241 Driver output pins 388 to 148 Output Scan signal output pins that drive the gate electrode of a TFT-
LCD.
The status of each output pin changes in synchronization with
the rising edge of shift clock CLK. The output voltage of the
driver is V
CLK Shift clock input 139 Input Shift clock input for the internal shift resistor. The contents of
internal shift resistor are shifted at the rising edge of CLK.
Connect to GCLK pin of source driver.
STVR,
STVL
OE1 Enable input 140 Input If the level selected by OE1SEL is input, the driver output is
OE2 Enable input 141 Input If the level selected by OE2SEL is input, the driver output is
R,/L Shift direction
FRM Frame signal
GCS Chip select input 133 Input <IFSEL = 0> To input chip select signals.
GCL Serial clock input 134 Input <IFSEL = 0> To input serial clock signals.
Start pulse
input/output pin
switching
input
input
136,
137
25 Input Shift direction switching input pin of the internal shift register.
129 Input Input frame reverse signals.
I/O Input/output pin of the internal shift resistor.
Start pulse signal (output from GSTB pin of source driver) is
read at the rising edge of shift clock CLK and a scan signal is
output from the driver output pin.
The valid level of the STVR/STVL pin is determined by the
setting of STVSEL.
When STVSEL = L, the pulse becomes low level at the falling
edge of the 240th shift clock CLK and high level at falling
edge of the 241st clock.
fixed to low level. (When OE1SEL = L the driver output is fixed
to low level if a low level is input.)
However, the shift resistor is not cleared. And, output enable
actuation is asynchronous in the clock.
Connect to GOE1 pin of source driver.
fixed to high level. (When OE2SEL = L the driver output is fixed
to low level if a high level is input.)
However, the shift resistor is not cleared. And, output enable
actuation is asynchronous in the clock.
Connect to GOE2 pin of source driver.
R,/L = 1 (right shift): STVR →O
R,/L = 0 (left shift): STVL →O
Connect to GFRAME pin of source driver.
Connect to GCS pin of source driver.
<IFSEL = 1> Leave open.
Connect to GCL pin of source driver.
<IFSEL = 1> Leave open.
DD1 to VB.
1 →O2 ··· O239 →O240 →STVL
241 →O240 ··· O2 →O1 →STVR
(1/5)
10
Preliminary Product Information S16027EJ0V9PM
µµµµ
PD161644A
Symbol Pin Name Pad No. I/O Function
GDA Serial data input 135 Input <IFSEL = 0> To input serial data signals.
Connect to GDA pin of source driver.
<IFSEL = 1> Leave open.
/GRESET Reset input 132 Input Reset input pin. Connect to /GRESET pin of source driver.
If /GRESET is made low, the serial interface is initialized (the
register values are not initialized). A reset operation is
executed according to the level of the /GRESET signal. Be
sure to execute a reset using this pin at power application.
VCIN Common pulse
input
DCCLK Clock input for
DC/DC converter
130 Input To input common pulse. Connect to VCOUT3 pin of source
driver. Fix this pin to low when not using it.
138 Input To input the external clock for the DC/DC converter.
This pin is valid only when CLS0 = 1 and CLS1 = 1. Other
settings cause this pin to be pulled down to low level, so in
these cases, leave open.
VGD Power supply input
for DC/DC
114 to 116 Input Reference voltage input pins for V
Connect to any of V
DD2, VR or VS.
DD1, VSS1 to VSS4 boost.
converter
VR Power supply
output for DC/DC
converter
VS Positive power
output supply for
111 to 113 Output Positive power supply voltage output for the DC/DC converter.
R output voltage can be changed by setting VRSEL0 to
The V
VRSEL2.
118 to 123 Output Positive power supply voltage output for source driver. The V
output voltage can be changed by setting VSEL0 to VSEL2.
driver
MVS External resistor
input
117 Input Any output voltage can be set by connecting an external
resistor.
<EXRV = 0> Leave open.
<EXRV = 1> Connect to external resistor.
−
C1 +, C1
C2 +, C2
C3 +, C3
C4 +, C4
C5 +, C5
C6 +, C6 −
VDD1 DC/DC converter
Capacitor connect
−
pin for boost
−
−
−
output
80 to 83, 76 to 79,
72 to 75, 68 to 71,
63, 64, 61, 62,
59, 60, 57, 58,
55, 56, 53, 54,
− To connect booster for DC/DC converter.
The recommended values of the capacitance and tolerance of
each capacitor are shown below.
µ
Capacitance : C1, C2: 1
F, C3 to C6: 0.47 µF
Tolerance : 10 V
51, 52, 49, 50
65 to 67 Output Boost voltage of DC/DC converter (VR x2 or x3).
The boost step number of V
DD1 is selected according to how
the external capacitor is connected. The boost reference
voltage can be set using VGD. Refer to the function of VGD
pin.
VDD2 DC/DC converter
output
VSS2 DC/DC converter
output
84 to 87 Output Boost voltage of DC/DC converter (VDC x2 or x3). The boost
step number for V
DD2 can be set using VCD2.
46 to 48 Output Boost voltage of DC/DC converter (VR x-1 or x-2).
The boost step number of V
SS2 is selected according to how the
external capacitor is connected. The boost reference voltage
can be set using VGD. Refer to the function of VGD pin.
(2/5)
S
Preliminary Product Information S16027EJ0V9PM
11
µµµµ
PD161644A
Symbol Pin Name Pad No. I/O Function
VSS3 DC/DC converter
output
40 to 42, 143 Output Boost voltage of DC/DC converter (VR x-1 or x-2).
The boost step number of V
SS2 is selected according to how
the external capacitor is connected. The boost reference
voltage can be set using VGD. Refer to VGD pin function.
VSS4 DC/DC converter
43 to 45 Output Boost voltage output of DC/DC converter (VDC x-1).
output
COMH Common high level
output
34, 35 Output <COMON = 1> High level of common voltage is output. The
voltage level changes accordance with DA0 to DA7 and CDA0
to CDA7.
<COMON = 1> Leave open when not using it.
COML Common low
level output
32, 33 Output <COMON = 1> Low level of common voltage is output. The
voltage level changes accordance with DA0 to DA7 and CDA0
to CDA7.
<COMON = 0> Leave open when not using it.
VCOM Common output 29 to 31 Output <COMON = 1> The common voltage synchronized with the
VCIN input is output.
Connect to common pin of panel.
<COMON = 0> Leave open when not using it.
VM Gate output low
level select
36, 37 Output Gate output low level select voltage synchronized with the
VCIN input is output. Connect to V
B pin.
voltage
VB Driver negative
voltage
38, 39 Input Negative voltage of output buffer. This is the input pin of the
liquid crystal driver negative voltage. Connect to V
M pin.
IFSEL I/F selection 26 Input The serial I/F input switching pin.
<IFSEL = 0> Serial I/F input.
The DCON, RGONR, VCD2, VMS, FS0, FS2, CLS0, RGON,
VSEL, EXRV, ACS0, SCN0, SCN0, SCN2, PUPT0, DUPF0
pins should be left open.
<IFSEL = 1> Control pin input.
The GCS, GCL, GDA pins should be left open.
DCON DC/DC converter
control
128 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> The DC/DC converter ON/OFF control signal is
input. Connect to the DCON pin of the source driver.
<DCON = 0> DC/DC converter OFF.
<DCON = 1> DC/DC converter ON.
RGONR VR regulator
control
VCD2 VDD2 boost
selection
19 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> The V
<RGONR = 0> V
<RGONR = 1> V
R regulator ON/OFF control signal is input.
R regulator OFF.
R regulator ON.
126 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> The V
<VCD2 = 0> V
<VCD2 = 1> V
DD2 boost step number select pin.
DD2 = VDC x 2.
DD2 = VDC x 3.
(3/5)
12
Preliminary Product Information S16027EJ0V9PM
Symbol Pin Name Pad No. I/O Function
VMS VDD2 boost
selection
VCOMIN VCOM center
voltage input
18 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> V
<VMS = 0> V
<VMS = 1> V
DD2 boost mode select pin.
DD2: single boost mode
DD2: dual boost mode
28 Input VCOM center voltage input pin.
Leave open when COMSEL = 0.
<COMSEL = 0> Internal D/A is valid.
<COMSEL = 1> VCOMIN input voltage is valid.
FS0 VDD2 boost
frequency
selection in scan
17 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> V
<FS0 = 0 > f
DD2 boost frequency select pin in scan mode
OSC/2 <FS0 = 0 > fOSC/4
mode
FS2 VDD1, VSS2 to
SS4 boost
V
frequency
selection in scan
16 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> V
DD1, VSS2 to VSS4 boost frequency select pin in
scan mode.
<FS2 = 0 > f
OSC/2 <FS2 = 1, > fOSC/4
mode
CLS0 DC/DC OSC
frequency
selection
15 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> Select pin of the OSC oscillation frequency for
DC/DC converter.
<CLS0 = 0> f
OSC = 20 kHz, DCCLK: Open
<CLS0 = 1> External CK input mode
RGON VS regulator
control
127 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> The V
S regulator ON/OFF control signal is input.
Connect this pin to the RGON pin of the source driver.
S regulator OFF.
S regulator ON.
S = 4 V
S = 5 V
VSEL VS regulator voltage
selection
EXRV VS regulating
resistor
selection
<RGON = 0> V
<RGON = 1> V
14 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> Select pin of output voltage for V
<VSEL = 1> V
<VSEL = 0> V
13 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> Select pin of external resistor for V
<EXRV = 0> Internal resistor setting mode.
<EXRV = 1> Any output voltage can be set by connecting
MVS to an external resistor
ACS0
Amp. current
selection in scan
mode
12 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> Amp. current select pin in scan mode.
<ACS0 = 0> Amp. current = 5
<ACS0 = 1> Amp. current = 15
µµµµ
PD161644A
(4/5)
S regulator.
S regulator.
µ
A.
µ
A
Preliminary Product Information S16027EJ0V9PM
13
Symbol Name Pad No. I/O Function
SCN0,
SCN1,
SCN2
PUPT0 Setting pin of
DUPF0 Operating
VMON Stand-by current
TESTOUT1 VREF reference
VDC DC/DC converter
VCC1 Logic reference
VSS1 Ground 105 to 110 − Connect to the system ground.
PVCC1 Pull-up voltage 6, 24, 125 − Pull-up voltage for mode setting pins.
PVSS1 Pull-down voltage 20, 27, 131 − Pull-down voltage for mode setting pins.
TESTIN1,
TESTIN2
TESTOUT2 TEST output pin 2 Output Test output pin. Leave open.
PVSS3 Pull-down voltage 21 − Pull-down voltage for mode setting pin.
DUMMY Dummy 1, 23, 92, 124,
Gate scan
selection
DC/DC converter
power on time
frequency setting
pin at DC/DC
converter power
on
reduction control
pin
voltage output
reference voltage
voltage
TEST input pin 4,
11,
10,
9
8 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
7 Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
22 Input The standby current reduction control pin.
5 Output The VREF voltage measurement pin.
93 to 100 − Reference voltage input pin for DC/DC converter.
101 to 104 − 2.7 V ± 5% LS: level shifter reference voltage input pins.
3
142, 144 to 147,
389 to 391
Input <IFSEL = 0> Leave open. (Internal resistors are valid.)
<IFSEL = 1> Select pin of Gate scan order.
<SCN0 = 1, SCN1 = 1, SCN2 = 1> MODE1
<SCN0 = 1, SCN1 = 1, SCN2 = 0> MODE2
<SCN0 = 1, SCN1 = 0, SCN2 = 1> MODE3
<SCN0 = 1, SCN1 = 0, SCN2 = 0> MODE4
<SCN0 = 0, SCN1, SCN2 = x> MODE5
<IFSEL = 1> This pin sets the rising time of V
SS4 at DC/DC converter power on time.
to V
<IFSEL = 1> This pin sets the operating frequency at DC/DC
converter power on time.
<DUPT0 = 0> f
<DUPT0 = 0> f
<VMON = PVSS3> Normal mode
A quiescent current of about 0.5
mode. When the V
are fixed to ALL-High.
<VMON = PVCC1> Standby current reduction mode
Makes the quiescent current consumed in standby mode 0.
When the V
undefined.
Leave open.
Input Test input pins. Leave open.
− Dummy data
OSC/8
OSC/16
µ
A is consumed in standby
CC1 voltage drops, the driver output pins
CC1 voltage drops, the driver output pins are
µµµµ
PD161644A
(5/5)
DD1, VDD2, VSS2
14
Preliminary Product Information S16027EJ0V9PM
µµµµ
PD161644A
4. COMMAND
4.1 Command List
Data bit
7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0
0 0 0 1 1 0 0 0 R24 DC/DC operation
setting
0 0 0 1 1 0 0 1 R25 DC/DC step setting VRSEL2 VRSEL1 VRSEL0 VMS VCD2
0 0 0 1 1 0 1 0 R26 DC/DC oscillation
setting
0 0 0 1 1 0 1 1 R27 Regulator output setting ACS1 ACS0 EXRV VSEL2 VSEL1 VSEL0 RGON
0 0 0 1 1 1 0 0 R28 LPM setting LACS1 LACS0 LFS3 LFS2 LFS1 LFS0 LPM
0 0 0 1 1 1 0 1 R29 Gate scan setting OE2SELOE1SELSTVSEL SCN2 SCN1 SCN0
0 0 0 1 1 1 1 0 R30 Gate mode setting COMHI COMSEL COMON NLINE2 NLINE1
0 0 0 1 1 1 1 1 R31 Common amplitude
setting
0 0 1 0 0 0 0 0 R32 Common center setting CDA7 CDA6 CDA5 CDA4 CDA3 CDA2 CDA1 CDA0
0 0 1 0 0 0 0 1 R33 DC/DC power on setting PONM PON DUPF1 DUPF0 PUPT1 PUPT0
0 0 1 0 0 0 1 0 R34 Reset RES
RGONR VS4ON VS3ON VS2ON VD2ON VD1ON DCON
FUP CLS1 CLS0 FS3 FS2 FS1 FS0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
4.2 Command Description
Reset the internal data at power application by inputting a low level to the /GRESET pin.
(1/3)
Resistor Bit Symbol Reset Functions Descriptions
R24 D0 DCON 0 DC/DC converter control Control ON/OFF of DC/DC converter
<DCON = 0> DC/DC converter OFF
<DCON = 1> DC/DC converter ON
D1 VD1ON 0 VDD1 boost control Control ON/OFF of VDD1 boost
<VD1ON = 0> V
<VD1ON = 1> V
D2 VD2ON 0 VDD2 boost control Control VDD2 boost ON/OFF
<VD2ON = 0> V
<VD2ON = 1> V
D3 VS2ON 0 VSS2 boost control Control VSS2 boost ON/OFF.
<VS2ON = 0> V
<VS2ON = 1> V
D4 VS3ON 0 VSS3 boost control Control VSS3 boost ON/OFF.
<VS3ON = 0> V
<VS3ON = 1> V
D5 VS4ON 0 VSS4 boost control Control VSS4 boost ON/OFF.
<VS4ON = 0> V
<VS4ON = 1> V
D6 RGONR 0 VR regulator control Control ON/OFF of VR regulator
<RGON = 0> V
<RGON = 1> V
DD1 boost OFF
DD1 boost ON
DD2 boost OFF
DD2 boost ON
SS2 boost OFF
SS2 boost ON
SS3 boost OFF
SS3 boost ON
SS4 boost OFF
SS4 boost ON
R regulator OFF
R regulator ON
Preliminary Product Information S16027EJ0V9PM
15
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