DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µµµµ
PC4741
HIGH PERFORMANCE QUAD OPERATIONAL AMPLIFIER
DESCRIPTION
The µPC4741 consists of four independent frequency compensated operational amplifiers featuring higher speed,
broader band than general purpose type as 741. The
such as active filters or pulse amplifiers.
FEATURES
• Internal frequency compensation
• Low noise
• Output short circuit protection
PC4741 is most appropriate for AC signal amplifier applications
µ
ORDERING INFORMATION
Part Number Package
PC4741C
µ
PC4741C(5)
µ
PC4741G2
µ
PC4741G2(5)
µ
14-pin plastic DIP (7.62 mm (300))
14-pin plastic DIP (7.62 mm (300))
14-pin plastic SOP (5.72 mm (225))
14-pin plastic SOP (5.72 mm (225))
EQUIVALENT CIRCUIT (1/4 Circuit)
+
V
R
1
Q
5
Q
1
Q
I
I
I
N
Q
3
–
V
2
Q
6
Q
4
R
2
Q
8
R
C
1
Q
7
R
3
PIN CONFIGURATION (Top View)
µ
PC4741C, 4741G2
1
OUT
OUT
1
14
2
I
I1
−+
3
I
N1
+
4
V
5
I
N2
−+
6
I
I2
2
23
7
Q
9
Q
14
Q
12
Q
R
Q
10
4
D
1
Q
11
5
R
7
R
6
Q
15
Q
13
R
8
16
OUT
D
2
14
13
−+
12
11
10
−+
OUT
4
I
I4
I
N4
−
V
I
N3
I
I3
9
OUT
3
8
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G16051EJ3V0DS00 (3rd edition)
(Previous No. IC-1197)
Date Published February 2002 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
1987
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter Symbol Ratings Unit
−
Voltage between V+ and V
Note1
V+ − V
µµµµ
PC4741
−
−0.3 to +40 V
Differential Input Vol t age V
Input Voltage
Output Voltage
Output Short Circuit Durati on
Note2
Note3
C Package
G2 Package
Note6
Note4
Note5
Operating Ambient Temperature T
Storage Temperature T
ID
I
V
O
V
T
P
±30 V
−
V
−0.3 to V
−
V
−0.3 to V
+
+0.3
+
+0.3
570 mWPower Dissipation
550 mW
10 sec
A
stg
−20 to +80 °C
−55 to +125 °C
Notes 1. Reverse connection of supply voltage can cause destruction.
The input voltage should be allowed to input without damage or destruction. Even during the transition
2.
period of supply voltage, power on/off etc., this specification should be kept. The normal operation will
establish when the both inputs are within the Common Mode Input Voltage Range of electrical
characteristics.
3. This specification is the voltage which should be allowed to supply to the output terminal from external
without damage or destructive. Even during the transition period of supply voltage, power on/off etc., this
specification should be kept. The output voltage of normal operation will be the Output Voltage Swing of
electrical characteristics.
4. Thermal derating factor is –7.6 mW/°C when ambient temperature is higher than 50°C.
5. Thermal derating factor is –5.5 mW/°C when ambient temperature is higher than 25°C.
Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note 4 and
6.
Note 5.
V
V
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol MIN. TYP. MAX. Unit
Supply Voltage V
2
Data Sheet G16051EJ3V0DS
±
±4 ±16 V
PC4741C, 4741G2
µµµµ
ELECTRICAL CHARACTERISTICS (T
Parameter Symbol Conditions MIN. TYP. MAX. Unit
= 25°C, V
A
±±±±
= ±±±±15 V)
µµµµ
PC4741
Input Offset Voltage V
Input Offset Current
Input Bias Current
Note
Note
Large Signal Voltage Gain A
IO
RS ≤ 100 Ω±1.0 ±5.0 mV
IO
I
B
I
V
RL ≥ 2 kΩ , VO = ±10 V 25,000 50,000
±30 ±50 nA
70 300 nA
Power Consumption Pd IO = 0 A, All Amplif i ers 150 210 mW
Common Mode Rejection Rati o CMR 80 100 dB
Supply Voltage Rejection Rat i o SVR 50 100
Maximum Output Voltage V
Maximum Output Voltage V
Common Mode Input Voltage Range V
om
RL ≥ 10 kΩ±12 ±13.7 V
om
RL ≥ 2 kΩ±10 ±12.5 V
ICM
±12 ±14 V
Slew Rate SR AV = 1 1.6 V/ µs
Input Equivalent Noise Vol t age Density e
n
f = 1 kHz 9 nV/ Hz
Channel Separation f = 10 kHz 108 dB
Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.
Note
PC4741C (5), 4741G2 (5)
µµµµ
ELECTRICAL CHARACTERISTICS (T
= 25°C, V
A
±±±±
= ±±±±15 V)
µ
V/ V
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input Offset Voltage V
Input Offset Current
Input Bias Current
Note
Note
Large Signal Voltage Gain A
IO
RS ≤ 100 Ω±1.0 ±2.0 mV
IO
I
B
I
V
RL ≥ 2 kΩ , VO = ±10 V 28,000 50,000
±30 ±50 nA
100 nA
Power Consumption Pd IO = 0 A, All Amplif i ers 150 210 mW
Common Mode Rejection Rati o CMR 85 90 dB
Supply Voltage Rejection Rat i o SVR 50
Maximum Output Voltage V
Maximum Output Voltage V
Common Mode Input Voltage Range V
om
RL ≥ 10 kΩ±12.5 ±13.7 V
om
RL ≥ 2 kΩ±11 ±12.5 V
ICM
±13 ±14 V
µ
V/ V
Slew Rate SR AV = 1 1.6 V/ µs
Input Equivalent Noise Vol t age Density e
n
f = 1 kHz 9 nV/ Hz
Channel Separation f = 10 kHz 108 dB
Note Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.
Data Sheet G16051EJ3V0DS
3
MEASUREMENT CIRCUIT
Fig.1 Channel Separation Measurement Circuit
50 kΩ
50 Ω
−
+
V
O2
Channel Separation
= 20 log
1
1000
µµµµ
PC4741
V
O2
V
O1
10 kΩ
10 kΩ
−
+
V
O1
4
Data Sheet G16051EJ3V0DS