NEC 78K0S/KA1+, mPD78F9221, mPD78F9222 User Manual

Download

Preliminary User’s Manual

www.DataSheet4U.com

78K0S/KA1+

8-Bit Single-Chip Microcontrollers

PD78F9221

PD78F9222

Document No. U16898EJ1V0UD00 (1st edition) Date Published November 2003 N CP(K)

Printed in Japan

2003

[MEMO]

www.DataSheet4U.com

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

DD or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash

is a registered trademark of Silicon Storage Technology, Inc. in several countries including the

United States and Japan.

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

Caution: This product uses SuperFlash

technology licensed from Silicon Storage Technology, inc.

•

The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production.

•

Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent

•

of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property

•

rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes

•

in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

•

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".

•

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard":

"Special":

"Specific":

Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note) (1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).

M5D 02. 11-1

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

[GLOBAL SUPPORT] http://www.necel.com/en/support/support.html

NEC Electronics America, Inc. (U.S.)

Santa Clara, California Tel: 408-588-6000 800-366-9782

EC Electronics (Europe) GmbH

Duesseldorf, Germany Tel: 0211-65 03 01

• Sucursal en España

Madrid, Spain Tel: 091-504 27 87

• Succursale Française

Vélizy-Villacoublay, France Tel: 01-30-67 58 00

• Filiale Italiana

Milano, Italy Tel: 02-66 75 41

• Branch The Netherlands

Eindhoven, The Netherlands Tel: 040-244 58 45

• Tyskland Filial

Taeby, Sweden Tel: 08-63 80 820

• United Kingdom Branch

Milton Keynes, UK Tel: 01908-691-133

NEC Electronics Hong Kong Ltd.

Hong Kong Tel: 2886-9318

NEC Electronics Hong Kong Ltd.

Seoul Branch Seoul, Korea Tel: 02-558-3737

NEC Electronics Shanghai, Ltd.

Shanghai, P.R. China Tel: 021-6841-1138

NEC Electronics Taiwan Ltd.

Taipei, Taiwan Tel: 02-2719-2377

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore Tel: 6253-8311

J03.4

Preliminary User’s Manual U16898EJ1V0UD

INTRODUCTION

www.DataSheet4U.com

Target Readers This manual is intended for user engineers who wish to understand the functions of

the 78K0S/KA1+ in order to design and develop its application systems and programs.

The target devices are the following subseries products.

• 78K0S/KA1+:

Purpose This manual is intended to give users on understanding of the functions described in

the Organization below.

Organization Two manuals are available for the 78K0S/KA1+: this manual and the Instruction

Manual (common to the 78K/0S Series).

PD78F9221, 78F9222

78K0S/KA1+

User’s Manual

78K/0S Series

Instructions

User’s Manual

• Pin functions

• Internal block functions

• Interrupts

• CPU function

• Instruction set

• Instruction description

• Other internal peripheral functions

• Electrical specifications (target)

How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

◊ To understand the overall functions of 78K0S/KA1+ → Read this manual in the order of the CONTENTS. ◊ How to read register formats → The name of a bit whose number is enclosed with <> is reserved in the

assembler and is defined in the C compiler by the header file sfrbit.h. ◊ To learn the detailed functions of a register whose register name is known → See APPENDIX C REGISTER INDEX. ◊ To learn the details of the instruction functions of the 78K/0S Series → Refer to 78K/0S Series Instructions User’s Manual (U11047E) separately

available. ◊ To learn the electrical specifications (target) of the 78K0S/KA1+ → See CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES).

Preliminary User’s Manual U16898EJ1V0UD

Conventions Data significance: Higher digits on the left and lower digits on the right

www.DataSheet4U.com

Active low representation: ××× (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... ×××× or ××××B Decimal ... ×××× Hexadecimal ... ××××H

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No. 78K0S/KA1+ Subseries User’s Manual This manual 78K/0S Series Instructions User’s Manual U11047E

Documents Related to Development Software Tools (User’s Manuals)

Document Name Document No. RA78K0S Assembler Package

ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (WindowsTM Based) U15185E Project Manager Ver. 3.12 or Later (Windows Based) U14610E

Operation U14876E Language U14877E Structured Assembly Language U11623E Operation U14871E CC78K0S C Compiler Language U14872E

Documents Related to Development Hardware Tools (User’s Manuals)

Document Name Document No. IE-78K0S-NS In-Circuit Emulator U13549E IE-78K0S-NS-A In-Circuit Emulator U15207E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

Preliminary User’s Manual U16898EJ1V0UD

Documents Related to Flash Memory Writing

www.DataSheet4U.com

Document Name Document No.

PG-FP4 Flash Memory Programmer User’s Manual U15260E

CHAPTER 1 OVERVIEW

www.DataSheet4U.com

1.3 Ordering Information

Part Number Package Internal ROM

PD78F9221MC-5A4 20-pin plastic SSOP (7.62 mm (300)) Flash memory

PD78F9222MC-5A4 20-pin plastic SSOP (7.62 mm (300)) Flash memory

1.4 Pin Configuration (Top View)

20-pin plastic SSOP (7.62 mm (300))

PD78F9221MC-5A4

PD78F9222MC-5A4

Note

P121/X1 P122/X2

P123

RESET/P34

P31/TI010/TO00/INTP2

P30/TI000/INTP0

P40

P41/INTP3

Note VSS and AVSS are internally connected in the 78K0S/KA1+. Be sure to connect VSS to a stabilized GND in

order to stabilize V

SS via GND (= 0 V).

ANI0 to ANI3: Analog input RESET: Reset AV

REF: Analog reference voltage RxD6: Receive data

RxD6: Receive data TI000, TI010: Timer input INTP0 to INTP3: External interrupt input TO00, TOH1: Timer output P20 to P23: Port 2 TxD6: Transmit data P30, P31, P34: Port 3 V P40 to P45: Port 4 V P121 to P123: Port 12 X1, X2: Crystal oscillator (X1 input clock) P130: Port 13

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

REF

P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P130 P45 P44/RxD6 P43/TxD6/INTP1

P42/TOH1

DD: Power supply SS: Ground

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 1 OVERVIEW

www.DataSheet4U.com

1.5 78K0S/Kx1+ Product Lineup

The following table shows the product lineup of the 78K0S/Kx1+.

Part Number

Item Number of pins 8 pins 16 pins 20 pins 30 pins

Flash memory 1 KB, 2 KB, 4 KB 1 KB, 2 KB, 4 KB 2 KB 4 KB 4 KB, 8 KB Internal

memory

Supply voltage VDD = 2.0 to 5.5 V Minimum instruction

execution time

System clock (oscillation frequency)

Clock for TMH1 and WDT (oscillation frequency)

Port

Timer

Serial interface A/D converter 8 bits: 4 ch (2.7 to 5.5V) 10 bits: 4 ch (2.7 to 5.5V)

Reset

Operating temperature range −40 to +85°C

RAM 128 bytes 128 bytes 128 bytes 256

CMOS I/O 5 13 15 24 CMOS input 1 1 1 1 CMOS output 16-bit (TM0) 1 ch 8-bit (TMH) 1 ch 8-bit (TM8) WDT 1 ch

External 2 4 Interrupts Internal 6 10 RESET pin Provided POC 2.1 V ±0.1 V LVI Provided (selectable by software) WDT Provided

78K0S/KU1+ 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+

256 bytes

bytes

0.20 µs (10 MHz, VDD = 4.0 to 5.5 V)

s (6 MHz, VDD = 3.0 to 5.5 V)

0.33

s (5 MHz, VDD = 2.7 to 5.5 V)

0.40

s (500 kHz, VDD = 2.0 to 5.5 V)

4.0

Internal high-speed Ring-OSC oscillation (8 MHz (TYP.))

Crystal/ceramic oscillation (1 to 10 MHz)

X1 external clock input oscillation (1 to 10 MHz)

Internal low-speed Ring-OSC oscillation (240 kHz (TYP.))

− −

−

1 1

1 ch

LIN-Bus-supporting UART: 1 ch

Preliminary User’s Manual U16898EJ1V0UD

1.6 Block Diagram

www.DataSheet4U.com

CHAPTER 1 OVERVIEW

TO00/TI010/P31

TI000/P30

TOH1/P42

RxD6/P44 TxD6/P43

ANI0/P20 to

ANI3/P23

REF

16-bit timer event

8-bit timer

Watchdog timer

Serial interface

A/D converter

counter

Low-speed

Ring-OSC

UART6

78K0S

CPU core

Internal

high-speed

RAM

Flash

memory

Port 2

Port 3

Port 4

Port 12

Port 13 P130

Power on clear/

low voltage

indicator

Reset control

P20 to P23

P30, P31 P34

P40 to P45

P121 to P123

POC/LVI

control

INTP0/P30 INTP1/P43 INTP2/P31 INTP3/P41

Note V

SS and AVSS are internally connected in the 78K0S/KA1+. Be sure to connect VSS to stabilized GND in

order to stabilize V

Interrupt control

SS via GND (= 0 V).

System control

X1/P121 X2/P122

High-speed

Ring-OSC

RESET/P34

Note

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 1 OVERVIEW

www.DataSheet4U.com

1.7 Functional Outline

Item

Flash memory 2 KB 4 KB Internal

memory

Memory space 64 KB X1 input clock (oscillation frequency) Crystal/ceramic/external clock input:

clock

General-purpose registers 8 bits × 8 registers Minimum instruction execution time 0.2 µs/0.8 µs (X1 input clock: fX = 10 MHz) Instruction set • 16-bit operation

I/O port Total: 17 pins

Timer • 16-bit timer/event counter: 1 channel

Timer output 2 pins (PWM: 1 pin) A/D converter 10-bit resolution × 4 channels Serial interface LIN-bus-supporting UART mode: 1 channel

interrupt sources

Reset

High-speed RAM 128 bytes 256 bytes

10 MHz (V 500 kHz (V

High speed (oscillation frequency)

Low speed (for TMH1 and WDT)

External 4 Vectored Internal 10

Internal Ring oscillation: 8 MHz (TYP.) Ring-OSC

Internal Ring oscillation: 240 kHz (TYP.)

• Bit manipulation (set, reset, test), etc.

CMOS I/O: 15 pins CMOS input: 1 pin CMOS output: 1 pin

• 8-bit timer (timer H1): 1 channel

• 8-bit timer (timer 80): 1 channel

• Watchdog timer: 1 channel

• Reset by RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on clear

• Internal reset by low-voltage detector

Supply voltage VDD = 2.0 to 5.5 V Operating temperature range TA = −40 to +85°C Package 20-pin plastic SSOP (7.62 mm (300))

PD78F9221

DD = 4.0 to 5.5 V), 6 MHz (VDD = 3.0 to 5.5 V), 5 MHz (VDD = 2.7 to 5.5 V),

DD = 2.0 to 5.5 V)

Note

PD78F9222

Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-

clear (POC) circuit is 2.1 V ±0.1 V.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 2 PIN FUNCTIONS

www.DataSheet4U.com

2.1 Pin Function List

(1) Port pins

Pin Name I/O Function After Reset Alternate-

Function Pin

P20 to P23 I/O Port 2.

4-bit I/O port. Can be set to input or output mode in 1-bit units.

An on-chip pull-up resistor can be connected by setting software. P30 TI000/INTP0 P31

P34 Input P40 P41 INTP3 P42 TOH1 P43 TxD6/INTP1 P44 RxD6 P45 P121 X1 P122 X2 P123

P130 Output Port 13.

I/O Can be set to input or output mode in 1-

I/O Port 4.

I/O Port 12.

Port 3

bit units. An on-chip pull-up resistor can be connected by setting software.

Input only Input RESET

6-bit I/O port.

Can be set to input or output mode in 1-bit units.

An on-chip pull-up resistor can be connected by setting software.

3-bit I/O port.

Can be set to input or output mode in 1-bit units.

An on-chip pull-up resistor can be connected only to P123 by

setting software.

1-bit output-only port

Input ANI0 to ANI3

Input

TI010/TO00/ INTP2

Input

Output

−

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 2 PIN FUNCTIONS

www.DataSheet4U.com

(2) Non-port pins

Pin Name I/O Function After Reset Alternate-

Function Pin INTP0 P30/TI000 INTP1 P43/TxD6 INTP2 P31/TI010/TO00 INTP3 RxD6 Input Serial data input for asynchronous serial interface Input P44 TxD6 Output Serial data output for asynchronous serial interface Input P43/INTP1 TI000 External count clock input to 16-bit timer/event counter 00.

TI010

TO00 Output 16-bit timer/event counter 00 output Input P31/TI010/INTP2 TOH1 Output 8-bit timer H1 output Input P42 ANI0 to ANI3 Input Analog input of A/D converter Input P20 to P23 AVREF RESET Input System reset input X1 Input

VDD VSS

Input External interrupt input for which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

Input

Capture trigger input to capture registers (CR000 and CR010) of 16-bit timer/event counter 00

Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00

Reference voltage of A/D converter

−

Connection of crystal/ceramic oscillator for system clock oscillation.

External clock input Connection of crystal/ceramic oscillator for system clock

− oscillation.

Positive power supply

− Ground potential

−

Input

− −

−

− −

P41

P30/INTP0

P31/TO00/INTP2

P121

P122

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 2 PIN FUNCTIONS

www.DataSheet4U.com

2.2 Pin Functions

2.2.1 P20 to P23 (Port 2)

P20 to P23 constitute a 4-bit I/O port, port 2. In addition to I/O port pins, these pins also have a function to input

analog signals to the A/D converter. These pins can be set to the following operation modes in 1-bit units.

(1) Port mode

P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 2 (PU2).

(2) Control mode

P20 to P23 function as the analog input pins (ANI0 to ANI3) of the A/D converter. When using these pins as analog input pins, refer to 10.6 Cautions for A/D converter (5) ANI0/P20 to ANI3/P23.

2.2.2 P30, P31, and P34 (Port 3)

P30, P31 and P34 constitute a 2-bit I/O port, port 3. In addition to I/O port pins, these pins also have functions to

input/output a timer signal, and input an external interrupt request signal.

P34 is a 1-bit input-only port. This pin is also used as a RESET pin. P30 and P31 can be set to the following operation modes in 1-bit units.

(1) Port mode

P30 and P31 function as a 2-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 3 (PU3). P34 functions as a 1-bit input-only port.

(2) Control mode

P30, P31, and P34 function to input/output signals to/from internal timers, and to input an external interrupt request signal.

(a) INTP0 and INTP2

These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.

(b) TI000

This pin inputs an external count clock to 16-bit timer/event counter 00, or a capture trigger signal to the capture registers (CR000 and CR010) of 16-bit timer/event counter 00.

This pin inputs a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00.

(d) TO00

This pin outputs a signal from 16-bit timer/event counter 00.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 2 PIN FUNCTIONS

www.DataSheet4U.com

2.2.3 P40 to P45 (Port 4)

P40 to P45 constitute a 6-bit I/O port, port 4. In addition to I/O port pins, these pins also have functions to output a

timer signal, input external interrupt request signals, and input/output the data of the serial interface.

These pins can be set to the following operation modes in 1-bit units.

(1) Port mode

P40 and P45 function as a 6-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pullup resistor option register 4 (PU4).

(2) Control mode

P40 and 45 function to output a signal from an internal timer, input external interrupt request signals, and input/output data of the serial interface.

(a) INTP1 and INTP3

These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.

(b) TOH1

This is the output pin of 8-bit timer H1.

This pin outputs serial data from the asynchronous serial interface.

(d) RxD6

This pin inputs serial data to the asynchronous serial interface.

2.2.4 P121 to P123 (Port 12)

P121 to P123 constitute a 3-bit I/O port, port 12. Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). An on-chip pull-

up resistor can be connected to P123 by using pull-up resistor option register 12 (PU12).

P121 and P122 also function as the X1 and X2 pins, respectively.

2.2.5 P130 (Port 13)

This is a 1-bit output-only port.

2.2.6 RESET

This pin inputs an active-low system reset signal.

2.2.7 X1 and X2

These pins connect an oscillator to oscillate the X1 input clock. Supply an external clock to X1.

2.2.8 AV

REF

This pin inputs a reference voltage to the internal A/D converter. When the A/D converter is not used, connect this

pin to V

DD.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 2 PIN FUNCTIONS

www.DataSheet4U.com

2.2.9 VDD

This is the positive power supply pin.

2.2.10 V

This is the ground pin.

2.3 Pin I/O Circuits and Connection of Unused Pins

Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1.

Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pin P20/ANI0 to P23/ANI3 11 P30/TI000/INTP0 P31/TI010/TO00/INTP2 P34/RESET 2 Input Directly connect to VDD or VSS. P40 P41/INTP3 P42/TOH1 P43/TxD6/INTP1 P44/RxD6 P45 P121/X1 P122/X2 P123 8-A P130 3-C Output Leave open. AVREF

8-A

16-B

−

I/O

Input Directly connect to VDD.

Input: Independently connect to V Output: Leave open.

Input: Individually connect to V Output: Leave open.

DD or VSS via resistor.

DD or VSS via a resistor.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 2 PIN FUNCTIONS

www.DataSheet4U.com

Figure 2-1. Pin I/O Circuits

Type 2

Type 11

Schmitt-triggered input with hysteresis characteristics

Type 3-C

P-ch

Data

N-ch

OUT

Pull up enable

Data

Output disable

Comparator

(Threshold voltage)

Input enable

Type 16-B

X1,

IN/OUT

P-ch

REF

P-ch

IN/OUT

N-ch

REF

OSC

enable

Feedback cut-off

P-ch

P-ch N-ch

X2,

IN/OUT

Type 8-A

Pull up enable

Data

Output disable

Data

P-ch

IN/OUT

N-ch

Output disable

Data

Output Disable

P-ch

N-ch

P-ch

N-ch

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.1 Memory Space

The 78K0S/KA1+ can access up to 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps.

Figure 3-1. Memory Map (

FFFFH

PD78F9221)

Special function registers

256 × 8 bits

FF00H FEFFH

Internal high-speed RAM

256 × 8 bits

FE00H FDFFH

Use prohibited

Data memory

space

1000H 0FFFH

Program memory

space

0000H

Flash memory

4,096 × 8 bits

Remark The option byte is one byte at 0080H.

(SFR)

0FFFH

0082H 0081H 0080H 007FH

0040H 003FH

0022H 0021H

0000H

Program area

Option byte area

CALLT table area

Program area

Vector table area

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

Figure 3-2. Memory Map (µPD78F9222)

FFFFH

Special function registers

256 × 8 bits

FF00H FEFFH

Internal high-speed RAM

256 × 8 bits

FE00H FDFFH

Use prohibited

Data memory

space

1000H 0FFFH

Program memory

space

0000H

Flash memory

4,096 × 8 bits

Remark The option byte is one byte at 0080H.

(SFR)

0FFFH

0082H 0081H

0080H 007FH

0040H 003FH

0022H 0021H

0000H

Program area

Option byte area

CALLT table area

Program area

Vector table area

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the

program counter (PC).

The 78K0S/KA1+ provides the following internal ROMs (or flash memory) containing the following capacities.

Table 3-1. Internal ROM Capacity

Internal ROM Part Number

Structure Capacity

PD78F9221 2,048 × 8 bits

PD78F9222

Flash memory

4,096 × 8 bits

The following areas are allocated to the internal program memory space.

(1) Vector table area

The 34-byte area of addresses 0000H to 0021H is reserved as a vector table area. This area stores program

start addresses to be used when branching by RESET input or interrupt request generation. Of a

16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd

address.

Table 3-2. Vector Table

Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H Reset input 0014H INTFLC 0006H INTLVI 0016H INTP2 0008H INTP0 0018H INTP3 000AH INP1 001AH INTTM80 000CH INTTMH1 001CH INTSRE6 000EH INTTM000 001EH INTSR6 0010H INTTM010 0020H INTST6 0012H INTAD

(2) CALLT instruction table area

The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH.

(3) Option byte area

The option byte area is the 1-byte area of address 0080H. For details, refer to CHAPTER 17 OPTION BYTE.

3.1.2 Internal data memory space

128-byte internal high-speed RAM is provided in the µPD78F9221 and 256-byte in the µPD78F9222. The internal high-speed RAM can also be used as a stack memory.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.1.3 Special function register (SFR) area

Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see

Table 3-3).

3.1.4 Data memory addressing

The 78K0S/KA1+ is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. The data memory area (FE80H to FFFFH or FE00H to FFFFH) can be accessed using a unique addressing mode according to its use, such as a special function register (SFR). Figures 3-3 and 3-4 illustrate the data memory addressing.

Figure 3-3. Data Memory Addressing (

PD78F9221)

FFFFH

FF20H FE1FH

FF00H FEFFH

FE80H FE7FH

Special function registers (SFR)

256 × 8 bits

Internal high-speed RAM

128 × 8 bits

Use prohibted

SFR addressing

Short direct addressing

Direct addressing

Based addressing

0800H 07FFH

0000H

Flash memory

2,048 × 8 bits

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

FFFFH

FF20H FE1FH

FF00H FEFFH

FE20H FE1FH

FE00H FDFFH

CHAPTER 3 CPU ARCHITECTURE

Figure 3-4. Data Memory Addressing (µPD78F9222)

Special function registers (SFR)

256 × 8 bits

Internal high-speed RAM

256 × 8 bits

SFR addressing

Short direct addressing

Direct addressing

1000H 0FFFH

0000H

Use prohibited

Based addressing

Flash memory

4,096 × 8 bits

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.2 Processor Registers

The 78K0S/KA1+ provides the following on-chip processor registers.

3.2.1 Control registers

The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-5. Program Counter Configuration

015

PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets PSW to 02H.

Figure 3-6. Program Status Word Configuration

PSW

(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledge operations of the CPU. When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt are disabled. When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources. This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases.

Z 0 AC 0 0 1 CY

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

(d) Carry flag (CY)

This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area.

SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented before writing (saving) to the stack memory and is incremented after reading (restoring) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.

Caution Since reset input makes SP contents undefined, be sure to initialize the SP before

instruction execution.

PUSH rp instruction

CHAPTER 3 CPU ARCHITECTURE

Figure 3-7. Stack Pointer Configuration

Figure 3-8. Data to Be Saved to Stack Memory

CALL, CALLT instructions

SP SP _ 3

015

Interrupt

SP SP _ 2

SP _ 2

SP _ 1

SP + 1

SP SP + 2

SP SP _ 2

Lower half register pairs

Upper half register pairs

SP _ 2

SP _ 1

PC7 to PC0

PC15 to PC8

Figure 3-9. Data to Be Restored from Stack Memory

instruction

Lower half register pairs

Upper half register pairs

SP + 1

SP SP + 2

RET instructionPOP rp

PC7 to PC0

PC15 to PC8

SP _ 3

SP _ 2

SP _ 1

SP + 1

SP + 2

SP SP + 3

PC7 to PC0

PC15 to PC8

PSW

RETI instruction

PC7 to PC0

PC15 to PC8

PSW

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.2.2 General-purpose registers

A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).

In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).

Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3).

Figure 3-10. General-Purpose Register Configuration

(a) Absolute names

16-bit processing 8-bit processing

RP3

RP2

RP1

RP0

15 0 7 0

(b) Function names

16-bit processing 8-bit processing

15 0 7 0

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.2.3 Special function registers (SFRs)

Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH.

The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address.

• 8-bit manipulation Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address.

• 16-bit manipulation Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying an address, describe an even address.

Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:

• Symbol Indicates the addresses of the implemented special function registers. The symbols shown in this column are reserved words in the assembler, and have already been defined in a header file called “sfrbit.h” in the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used.

• R/W Indicates whether the special function register can be read or written. R/W: Read/write R: Read only W: Write only

• Number of bits manipulated simultaneously Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.

• After reset Indicates the status of the special function register when a reset is input.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

Table 3-3. Special Function Registers (1/2)

Address Special Function Register (SFR) Name Symbol R/W

FF02H Port register 2 P2 FF03H Port register 3 P3

R/W

Note 1

FF04H Port register 4 P4 FF0CH Port register 12 P12 FF0DH Port register 13 P13 W FF0EH 8-bit timer H compare register 01 CMP01

R/W FF0FH 8-bit timer H compare register 11 CMP11 FF12H

16-bit timer counter 00 TM00 R FF13H FF14H

16-bit timer capture/compare register 000 CR000

R/W FF15H FF16H

16-bit timer capture/compare register 010 CR010 FF17H FF18H

10-bit A/D conversion result register ADCR

R FF19H FF1AH 8-bit A/D conversion result register ADCRH FF22H Port mode register 2 PM2

R/W FF23H Port mode register 3 PM3 FF24H Port mode register 4 PM4 FF2CH Port mode register 12 PM12 FF32H Pull-up resistance option register 2 PU2 FF33H Pull-up resistance option register 3 PU3 FF34H Pull-up resistance option register 4 PU4 FF3CH Pull-up resistance option register 12 PU12 FF48H Watchdog timer mode register WDTM FF49H Watchdog timer enable register WDTE FF50H Low voltage detect register LVIM FF51H Low voltage detection level select register LVIS FF54H Reset control flag register RESF R FF58H Low-speed Ring-OSC mode register LSRCM

R/W FF5AH High-speed Ring-OSC mode register HSRCM FF60H 16-bit timer mode control register 00 TMC00 FF61H Prescaler mode register 00 PRM00 FF62H Capture/compare control register 00 CRC00 FF63H 16-bit timer output control register 00 TOC00 FF70H 8-bit timer H mode register 1 TMHMD1

Number of Bits Manipulated

Simultaneously

1 Bit 8 Bits 16 Bits

√ √ − √ √ − √ √ − √ √ − √ √ −

− √ −

− −

− √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ −

− √ −

− √ − √ √ − √ √ − √ √ − √ √ − √ √ −

Note 2

√

0000H

Note 2

√

0000H

Note 2

√

0000H

Note 2

√

After Reset

00H

Undefined

FFH

00H

67H 9AH 00H

Note 3

00H 00H

Notes 1. Only P34 is an input-only port.

2. A 16-bit access is possible only by the short direction addressing.

3. Varies depending on the reset cause.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

Table 3-3. Special Function Registers (2/2)

Address Special Function Register (SFR) Name Symbol R/W

FF80H A/D converter mode register ADM FF81H Analog input channel specify register ADS FF84H Port mode control register 2 PMC2 FF8CH Input switching control register ISC FF90H Asynchronous serial interface operation mode

status register 6 FF94H Transmission buffer register 6 TXB6 R/W FF95H Asynchronous serial interface transmission status

register 6 FF96H Clock selection register 6 CKSR6 FF97H Baud rate generator control register 6 BRGC6 FF98H Asynchronous serial interface control register 6 ASICL6 FFCCH 8-bit timer mode control register 80 TMC80 FFCDH 8-bit compare register 80 CR80 W FFCEH 8-bit timer counter 80 TM80 R FFE0H Interrupt request flag register 0 IF0 FFE1H Interrupt request flag register 1 IF1 FFE4H Interrupt mask flag register 0 MK0 FFE5H Interrupt mask flag register 1 MK1 FFECH External interrupt mode register 0 INTM0 FFFDH External interrupt mode register 1 INTM1 FFF3H Preprocessor clock control register PPCC FFF4H Oscillation stabilization time selection register OSTS

FFFBH Processor clock control register PCC

ASIM6

ASIS6

ASIF6 R

R/W

Number of Bits Manipulated

Simultaneously

1 Bit 8 Bits 16 Bits

√ √ − √ √ − √ √ − √ √ − √ √ −

− √ −

− √ − √ √ − √ √ −

− √ −

− √ − √ √ − √ √ − √ √ − √ √ −

− √ −

− √ − √ √ −

− √ −

√ √ −

After Reset

00H

01H

FFH 00H

FFH 16H 00H Undefined 00H

FFH

00H

02H Undefined

Note

02H

Note The oscillation stabilization time that elapses after release of reset is selected by the option byte. For

details, refer to CHAPTER 17 OPTION BYTE.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.3 Instruction Address Addressing

An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination address information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S

Series Instructions User’s Manual (U11047E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) to branch. The displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes the sign bit. In other words, the range of branch in relative addressing is between –128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15 0

...

PC is the start address of the next instruction of a BR instruction.

15 0

When S = 0, α indicates that all bits are “0”. When S = 1, α indicates that all bits are “1”.

876

jdisp8

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces.

[Illustration]

In case of CALL !addr16 and BR !addr16 instructions

CALL or BR

Low addr.

High addr.

15 0

3.3.3 Table indirect addressing

[Function]

The table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH.

[Illustration]

765 10

Instruction code

Effective address

ta4–0

15 1

00000000

001

65 0

Effective address + 1

Memory (Table)

Low addr.

High addr.

15 0

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.3.4 Register addressing

[Function]

The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed.

[Illustration]

15 0

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.4 Operand Address Addressing

The following methods (addressing) are available to specify the register and memory to undergo manipulation

during instruction execution.

3.4.1 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier Description

addr16 Label or 16-bit immediate data

[Description example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code 0 0 1 0 1 0 0 1 OP Code

0 0 0 0 0 0 0 000H

1 1 1 1 1 1 1 0FEH

[Illustration]

OP code addr16 (low) addr16 (high)

Memory

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal highspeed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to FF1FH. The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below.

[Operand format]

Identifier Description

saddr Label or FE20H to FF1FH immediate data

saddrp Label or FE20H to FF1FH immediate data (even address only)

[Description example]

MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H

Instruction code 1 1 1 1 0 1 0 1 OP code

1 0 0 1 0 0 0 0 90H (saddr-offset)

0 1 0 1 0 0 0 0 50H (immediate data)

[Illustration]

OP code

saddr-offset

Effective address

111111

Short direct memory

When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1.

Preliminary User’s Manual U16898EJ1V0UD

α α

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.4.3 Special function register (SFR) addressing

[Function]

A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH are accessed with short direct addressing.

[Operand format]

Identifier Description

sfr Special function register name

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code 1 1 1 0 0 1 1 1

0 0 1 0 0 0 0 0

[Illustration]

Effective address

OP code sfr-offset

111111

SFR

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.4.4 Register addressing

[Function]

A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

[Operand format]

Identifier Description

r X, A, C, B, E, D, L, H

rp AX, BC, DE, HL

‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code 0 0 0 0 1 0 1 0

0 0 1 0 0 1 0 1

INCW DE; When selecting the DE register pair for rp

Instruction code 1 0 0 0 1 0 0 0

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.4.5 Register indirect addressing

[Function]

The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

−

[DE], [HL]

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Instruction code 0 0 1 0 1 0 1 1

[Illustration]

15 0

The contents of addressed memory are transferred

7 0

Memory address specified by register pair DE

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 3 CPU ARCHITECTURE

www.DataSheet4U.com

3.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

−

[HL+byte]

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction code 0 0 1 0 1 1 0 1

0 0 0 1 0 0 0 0

3.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE

Instruction code 1 0 1 0 1 0 1 0

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

CHAPTER 4 PORT FUNCTIONS

4.1 Functions of Ports

The 78K0S/KA1+ has the ports shown in Figure 4-1, whic h can be used for various c ontrol operations. Table 4- 1

shows the functions of each port.

In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to

CHAPTER 2 PIN FUNCTIONS.

Figure 4-1. Port Functions

Port 4

Port 12

Port 13

P40

P45

P121

P123

P130

P20

Port 2

P23

P30 P31 P34

Port 3

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

Table 4-1. Port Functions

Pin Name I/O Function After Reset Alternate-

Function Pin

P20 to P23 I/O Port 2.

4-bit I/O port. Can be set to input or output mode in 1-bit units.

On-chip pull-up resistor can be connected by setting software. P30 TI000/INTP0 P31

P34 Input P40 P41 INTP3 P42 TOH1 P43 TxD6/INTP1 P44 RxD6 P45 P121 X1 P122 X2 P123

P130 Output Port 13.

I/O Can be set to input or output mode in 1-

I/O Port 4.

I/O Port 12.

Port 3

bit units. On-chip pull-up resistor can be connected by setting software.

Input only Input RESET

6-bit I/O port.

Can be set to input or output mode in 1-bit units.

On-chip pull-up resistor can be connected setting software.

3-bit I/O port.

Can be set to input or output mode in 1-bit units.

On-chip pull-up resistor can be connected only to P123 by

setting software.

1-bit output-only port.

Input ANI0 to ANI3

Input

TI010/TO00/ INTP2

Input

Output

−

Remarks 1. P121 and P122 can be allocated when the high-speed Ring-OSC is selected as the system clock.

2. P121 can be allocated when an external clock is selected as the system clock.

4.2 Port Configuration

Ports consist of the following hardware units.

Table 4-2. Configuration of Ports

Item Configuration

Control registers Port mode registers (PM2, PM3, PM4, PM12)

Port mode control register 2 (PMC2)

Port registers (P2, P3, P4, P12, P13)

Pull-up resistor option registers (PU2, PU3, PU4, PU12) Ports Total: 17 (CMOS I/O: 15, CMOS input: 1, CMOS output: 1) Pull-up resistor Total: 13

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

4.2.1 Port 2

Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor c an be connected in 1-bit units by using pull-up resistor option register 2 (PU2).

This port is also used as the analog input pins of the internal A/D converter.

Reset input sets port 2 to the input mode.

Figure 4-2 shows the block diagram of port 2.

Figure 4-2. Block Diagram of P20 to P23

VDD

PU2

PU20 to PU23

PMC2

PMC20 to PMC23

Internal bus

WRPORT

Output latch

(P20 to P23)

WRPM

PM2

PM20 to PM23

A/D converter

PU2: Pull-up resistor option register 2 PM2: Port mode register 2 PMC2: Port mode control register 2 RD: Read signal WR××: Write signal

P-ch

Selector

P20/ANI0 to P23/ANI3

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

4.2.2 Port 3

Pins P30 and P31 constitute a 2-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). When the P3 0 to P31 pins are used as an input port, an on-c hip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3). This port is also used as external interrupt request input pins.

The P34 pin is a 1-bit input-only port and functions alternately as the RESET pin.

Reset input sets port 3 to the input mode.

Figures 4-3 and 4-4 show the block diagrams of port 3.

Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the

function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. If a low level is input to the RESET pin before the option byte is referenced again after reset is released by the POC circuit, the 78K0S/KA1+ is reset and is held in the reset state until a high level is input to the RESET pin.

Figure 4-3. Block Diagram of P30 and P31

PU3

PU30, PU31

Alternate

function

PORT

Internal bus

Output latch

(P30, P31)

PM3

PM30, PM31

Alternate

function

PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR××: Write signal

P-ch

Selector

P30/TI000/INTP0, P31/TI010/TO00/INTP2

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

Figure 4-4. Block Diagram of P34

P34/RESET

Internal bus

Reset

Option

byte

RD: Read signal

4.2.3 Port 4

Port 4 is a 6-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). When the P40 to P45 pins are used as an input port, an on-chip pull-up resistor c an be connected in 1-bit units by using pull-up resistor option register 4 (PU4).

Alternate functions include external interrupt request input, serial interface data I/O, and timer output.

Reset input sets port 4 to the input mode.

Figures 4-5 to 4-8 show the block diagrams of port 4.

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

CHAPTER 4 PORT FUNCTIONS

Figure 4-5. Block Diagram of P40 and P45

PU4

PU40, PU45

Internal bus

PORT

Output latch

(P40, P45)

PM4

PM40, PM45

PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal

P-ch

Selector

P40, P45

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

CHAPTER 4 PORT FUNCTIONS

Figure 4-6. Block Diagram of P41 and P44

PU4

PU41, PU44

Alternate

function

Internal bus

PORT

Output latch

(P41, P44)

PM4

PM41, PM44

PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal

P-ch

Selector

P41/INTP3, P44/RxD6

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

CHAPTER 4 PORT FUNCTIONS

Figure 4-7. Block Diagram of P42

PU4

PU42

PORT

Internal bus

Output latch

(P42)

PM4

PM42

Alternate

function

PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal

P-ch

Selector

P42/TOH1

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

CHAPTER 4 PORT FUNCTIONS

Figure 4-8. Block Diagram of P43

PU4

PU43

Alternate

function

Internal bus

PORT

Output latch

(P43)

PM4

PM43

Alternate

function

PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal

P-ch

Selector

P43/Tx6/INTP1

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

4.2.4 Port 12

Port 12 is a 3-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). When the P123 pin is used as an input port, an on-chip pull-up resistor can be connected by using pull-up resistor option register 12 (PU12).

Reset input sets port 12 to the input mode.

The P121 and P122 pins are also used as the X1 and X2 pins of the system clock oscillator. The functions of the P121 and P122 pins differ, therefore, depending on the selected system c lock oscillator. The following three system clock oscillators can be used.

(1) High-speed Ring-OSC circuit

The P121 and P122 pins can be used as I/O port pins.

(2) Crystal/ceramic oscillator

The P121 and P122 pins cannot be used as I/O port pins because they are used as the X1 and X2 pins.

(3) External clock input

The P121 pin is used as the X1 pin to input an external clock, and therefore it cannot be used as an I/O port pin. The P122 pin can be used as an I/O port pin.

The system clock oscillation is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.

Figures 4-9 to 4-10 show the block diagrams of port 12.

Figure 4-9. Block Diagram of P121 and P122

PORT

Internal bus

WRPM

PM12: Port mode register 12 RD: Read signal WR××: Write signal

Output latch

(P121, P122)

PM12

PM121, PM122

Selector

Clock input

P121/X1, P122/X2

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

CHAPTER 4 PORT FUNCTIONS

Figure 4-10. Block Diagram of P123

PU12

PU123

Internal bus

PORT

Output latch

(P123)

PM12

PM123

PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WR××: Write signal

P-ch

Selector

P123

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

4.2.5 Port 13

This is a 1-bit output-only port.

Figure 4-11 shows the block diagram of port 13.

Figure 4-11. Block Diagram of P130

Internal bus

PORT

Output latch

(P130)

RD: Read signal WR××: Write signal

Remark When a reset is input, P130 outputs a low level. If P130 outputs a high level immediately after

reset is released, the output signal of P130 can be used as a dummy CPU reset signal.

4.3 Registers Controlling Port Functions

The ports are controlled by the following four types of registers.

• Port mode registers (PM2, PM3, PM4, PM12)

• Port registers (P2, P3, P4, P12, P13)

• Port mode control register 2 (PMC2)

• Pull-up resistor option registers (PU2, PU3, PU4, PU12)

(1) Port mode registers (PM2, PM3, PM4, PM12)

These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets these registers to FFH. When a port pin is used as an alternate-function pin, set it s port mode register and output latch as shown in Table 4-3.

Caution Because P30, P31, and P43 are also used as external interrupt pins, the corresponding

interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. To use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance.

P130

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

Figure 4-12. Format of Port Mode Register

Address: FF22H, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0

PM2 1 1 1 1 PM23 PM22 PM21 PM20

Address: FF23H, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0

PM3 1 1 1 1 1 1 PM31 PM30

Address: FF24H, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0

PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40

Address: FF2CH, After reset: FFH, R/W Symbol 7 6 5 4 3 2 1 0

PM12 1 1 1 1 PM123 PM122 PM121 1

PMmn Selection of I/O mode of Pmn pin (m = 2, 3, 4, or 12; n = 0 to 7) 0 Output mode (output buffer ON) 1 Input mode (output buffer OFF)

(2) Port registers (P2, P3, P4, P12, P13)

These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read in the input mode, and the value of the output l atch of the port is read in the output mode. P20 to P23, P30, P31, P34, P40 to P45, P121 to P123, and P130 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset input sets these registers to 00H.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

Figure 4-13. Format of Port Register

Address: FF02H, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0

P2 0 0 0 0 P23 P22 P21 P20

Address: FF03H, After reset: 00H Symbol 7 6 5 4 3 2 1 0

P3 0 0 0 P34 0 0 P31 P30

Note

(Output latch) R/W

Note

Address: FF04H, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0

P4 0 0 P45 P44 P43 P42 P41 P40

Address: FF0CH, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0

P12 0 0 0 0 P123 P122 P121 0

Address: FF0DH, After reset: 00H (Output latch) R/W Symbol 7 6 5 4 3 2 1 0

P13 0 0 0 0 0 0 0 P130

m = 2, 3, 4, 12, or 13; n = 0-7 Pmn

Controls of output data (in output mode) Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level

Note Because P34 is read-only, its reset value is undefined.

(3) Port mode control register 2 (PMC2)

This register specifies the port mode or alternate function (A/D converter) of port 2. Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units. PMC2 is set by using a 1-bit or 8-bit memory manipulation instruction. Reset input sets PMC2 to 00H.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

Figure 4-14. Format of Port Mode Control Register 2

Address: FF84H, After reset: R/W

Symbol 7 6 5 4 3 2 1 0

PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20

PMC2n Specification of operation mode (n = 0 to 3)

0 Port mode 1 Alternate-function mode (A/D converter)

Table 4-3. Setting of Port Mode Register, Port Register (Output Latch), and Port Mode Control Register

When Alternate Function Is Used

Pin Name

P20 to P23 ANI0 to ANI3 Input 1 P30

P31

P41 INTP3 Input 1 P42 TOH1 Output 0 0 P43

P44 RxD6 Input 1

TI000 Input 1 INTP0 Input 1 TO00 Output 0 0 TI010 Input 1 INTP2 Input 1

TxD6 Output 0 1 INTP1 Input 1

Alternate-Function Pin

Name I/O

PM×× P×× PMC2n

(n = 0 to 3)

× × − × −

× − × − × −

× − × −

Remark ×: don’t care

PM××: Port mode register, P××: Port register (output latch of port) PMC2×: Port mode control register

−

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

(4) Pull-up resistor option registers (PU2, PU3, PU4, PU12)

These registers are used to specify whether an on-chip pull -up resistor is connected to P20 to P 23, P30, P31, P40 to P45, and P123. By setting PU2, PU3, PU4, or PU12, an on-chip pull-up resistor can be conn ected to the port pin corresponding to the bit of PU2, PU3, PU4, or PU12. PU2, PU3, PU4, and PU12 are set by using a 1-bit or 8-bit memory manipulation instruction. Reset input set these registers to 00H.

Figure 4-15. Format of Pull-up Resistor Option Register

Address: FF32H, After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0

PU2 0 0 0 0 PU23 PU22 PU21 PU20

Address: FF33H, After reset: 00H R/W

Symbol

PU3

Address: FF34H, After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0

PU4 0 0 PU45 PU44 PU43 PU42 PU41 PU40

Address: FF3CH, After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0

PU12 0 0 0 0 PU123 0 0 0

7 6 5 4 3 2 1 0 0 0 0 0 0 0 PU31 PU30

PUmn Selection of connection of on-chip pull-up resistor of Pmn (m = 2, 3, 4, or 12; n = 0 to 7)

0 Does not connect on-chip pull-up resistor 1 Connects on-chip pull-up resistor

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 4 PORT FUNCTIONS

www.DataSheet4U.com

4.4 Operation of Port Function

The operation of a port differs, as follows, depending on the setting of the I/O mode.

Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit

units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs.

4.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch by a transfer instruction. In addition, the contents of the output latch are output from the pin. Once data is written to the output latch, it is retained until new data is written to t he output latch. Reset input cleans the data in the output latch.

(2) In input mode

A value can be written to the output latch by a transfer instruction. Because the output buffer is off, however, the pin status remains unchanged. Once data is written to the output latch, it is retained until new data is written to the output latch.

4.4.2 Reading from I/O port

(1) In output mode

The contents of the output latch can be read by a transfer instruction. The contents of the output latch remain unchanged.

(2) In input mode

The pin status can be read by a transfer instruction. The contents of the output latch remain unchanged.

4.4.3 Operations on I/O port

(1) In output mode

An operation is performed on the contents of the output latch and the result is written to the output latch. The contents of the output latch are output from the pin. Once data is written to the output latch, it is retained until new data is written to the output latch. Reset input clears the data in the output latch.

(2) In input mode

The pin level is read and an operation is p erformed on its contents. The operation resul t is written to the output latch. However, the pin status remains unchanged because the output buffer is off.

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

CHAPTER 5 CLOCK GENERATORS

5.1 Functions of Clock Generators

The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the watchdog timer and 8-bit timer H1 (TMH1).

5.1.1 System clock oscillators

The following three types of system clock oscillators are used.

• High-speed Ring-OSC oscillator

This circuit internally oscillates a clock of 8 MHz (TYP.). Its oscillation can be stopped by execution of the STOP

instruction.

If the high-speed Ring-OSC oscillator is selected to supply the system clock, the X1 and X2 pins can be used as

I/O port pins.

• Crystal/ceramic oscillator

This circuit oscillates a clock with a crystal/ceramic oscillator connected across the X1 and X2 pins. It can

oscillate a clock of 500 kHz to 10 MHz. Oscillation of this circuit can be stopped by execution of the STOP instruction.

• External clock input circuit

This circuit supplies a clock from an external IC to the X1 pin. A clock of 500 kHz to 10 MHz can be supplie d.

Internal clock supply can be stopped by execution of the STOP instruction.

If the external clock input is selected as the system clock, the X2 pin can be used as an I/O port pin.

The system clock source is selected by using the option byte. For details, refer to CHAPTER 17 OPTION BYTE.

When using the X1 and X2 pins as I/O port pins, refer to CHAPTER 4 PORT FUNCTIONS for details.

5.1.2 Clock oscillator for interval time generation

The following circuit is used as a clock oscillator for interval time generation.

• Low-speed Ring-OSC oscillator

This circuit oscillates a clock of 240 kHz (TYP.). Its oscillation can be stop ped by usi ng t he low-s pee d R ing-OSC

mode register (LSRCM) when it is specified by the option byte that its oscillation can be stopped by software.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

5.2 Configuration of Clock Generators

The clock generators consist of the following hardware.

Table 5-1. Configuration of Clock Generators

Item Configuration

Control registers Processor clock control register (PCC)

Preprocessor clock control register (PPCC) Low-speed Ring-OSC mode register (LSRCM) High-speed Ring-OSC mode register (HSRCM) Oscillation stabilization time select register (OSTS)

Oscillators Crystal/ceramic oscillator

High-speed Ring-OSC oscillator External clock input circuit Low-speed Ring-OSC oscillator

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

Figure 5-1. Block Diagram of Clock Generators

Internal bus

X1/P121

X2/P122

System clock oscillation stabilization time counter

STOP

System clock

Note

oscillator

Crystal/ceramic

oscillation

External clock

input

High-speed

Ring-OSC

oscillation

Oscillation stabilization time select register (OSTS)

Clock for flash memory self programming control

Prescaler

Preprocessor clock control register (PPCC)

PPCC1 PPCC0OSTS1 OSTS0

Selector

Low-speed Ring-OSC

oscillator

Prescaler

Processor clock control register (PCC)

PCC1

Selector

Clock to peripheral hardware (f

)

8-bit timer H1, watchdog timer

Controller

CPU

CPU clock

CPU

)

High-speed Ring-OSC is selected as system clock source

High-speed Ring-OSC mode register (HSRCM)

HSRSTOP

Option byte 1: Cannot be stopped. 0: Can be stopped.

Low-speed Ring-OSC mode register (LSRCM)

LSRSTOP

Internal bus

Note Select the high-speed Ring-OSC oscillator, crystal/ceramic oscillator, or external clock input as the system

clock source by using the option byte.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

5.3 Registers Controlling Clock Generators

The clock generators are controlled by the following five registers.

• Processor clock control register (PCC)

• Preprocessor clock control register (PPCC)

• Low-speed Ring-OSC mode register (LSRCM)

• High-speed Ring-OSC mode register (HSRCM)

• Oscillation stabilization time select register (OSTS)

(1) Processor clock control register (PCC) and pre-processor clock control register (PPCC)

These registers are used to specify the division ratio of the system clock. PCC and PPCC are set by using a 1-bit or 8-bit memory manipulation instruction. Reset input sets PCC and PPCC to 02H.

Figure 5-2. Format of Processor Clock Control Register (PCC)

Address: FFFBH, After reset: 02H, R/W Symbol 7 6 5 4 3 2 1 0

PCC 0 0 0 0 0 0 PCC1 0

Figure 5-3. Format of Preprocessor Clock Control Register (PPCC)

Address: FFF3H, After reset: 02H, R/W Symbol 7 6 5 4 3 2 1 0 PPCC 0 0 0 0 0 0 PPCC1 PPCC0

PPCC1 PPCC0 PCC1 Selection of CPU clock (fCPU) 0 0 0 fX 0 1 0 fX/2 0 0 1 fX/22 1 0 0 fX/22 0 1 1 fX/23 1 0 1 fX/24 Other than above Setting prohibited

Note 1

Note 2

Note 1

Note 2

Notes 1. If PPCC = 01H, the clock (f

2. If PPCC = 02H, the clock (f

XP) supplied to the peripheral hardware is fX/2. XP) supplied to the peripheral hardware is fX/2

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

The fastest instruction of the 78K0S/KA1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f

CPU) and the minimum instruction execution time is as shown in Table 5-2.

Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time

Note

High-speed Ring-OSC clock

(at 8.0 MHz (TYP.))

Minimum Instruction Execution Time: 2/fCPU CPU Clock (fCPU)

Crystal/ceramic oscillation clock

or external clock input (at 10.0 MHz) fX 0.25 fX/2 0.5 fX/22 1.0 fX/23 2.0 fX/24 4.0

s 0.2

s 0.4

s 0.8

s 1.6

s 3.2

Note The CPU clock (high-speed Ring-OSC clock, crystal/ceramic oscillation clock, or external clock input) is

selected by the option byte.

(2) Low-speed Ring-OSC mode register (LSRCM)

This register is used to select the operation mode of the low-speed Ring-OSC oscillator (240 kHz (TYP.)). This register is valid when it is specified by the option byte that the low-speed Ring-OSC oscillator can be stopped by software. If it is specified by the option byte that the low-speed Ring-OSC oscillator cannot be stopped by software, setting of this register is invalid, and the low-speed Ring-OSC oscillator continues oscillating. In addition, the source clock of WDT is fixed to the low-speed Ring-OSC oscillator. For details, refe r to CHAPTER 9 WATCHDOG TIMER. LSRCM can be set by using an 8-bit memory manipulation instruction. Reset input sets LSRCM to 00H.

Figure 5-4. Format of Low-Speed Ring-OSC Mode Register (LSRCM)

Address: FF58H, After reset: 00H, R/W Symbol 7 6 5 4 3 2 1 0 LSRCM 0 0 0 0 0 0 0 LSRSTOP

(3) High-speed Ring-OSC mode register (HSRCM)

This register is used to select the operation mode of the high-speed Ring-OSC oscill ator that gener ates a clock (8 MHz (TYP.)) for controlling self programming of the flash memory. This register is valid when crystal/ceramic oscillation or external clock input is selected as the system clock source by the option byte. Setting of this register is invalid when the high-speed Ring-OSC oscillator is selected by the option byte.

LSRSTOP

Low-speed Ring-OSC oscillates Low-speed Ring-OSC stops

Oscillation/stop of low-speed Ring-OSC

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

If crystal/ceramic oscillation or external clock input is selected as the system clock source, the high-speed RingOSC oscillator must be oscillated during self-programming of the fl ash memory. While self-programming is not executed, stop oscillation of the high-speed Ring-OSC os cillator to reduce the current consumption. For selfprogramming of the flash memory, refer to CHAPTER 18 FLASH MEMORY. HSRCM is set by using an 8-bit memory manipulation instruction. Reset input sets HSRCM to 00H.

Figure 5-5. Format of High-Speed Ring-OSC Mode Register (HSRCM)

Address: FF5AH, After reset: 00H, R/W Symbol 7 6 5 4 3 2 1 0 HSRCM 0 0 0 0 0 0 0 HSRSTOP

HSRSTOP Oscillation/stops of high-speed Ring-OSC 0 High-speed Ring-OSC oscillates 1 High-speed Ring-OSC oscillates stops

(4) Oscillation stabilization time select register (OSTS)

This register is used to select oscillation stabilization time of the clock supplied from the oscillator whe n the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released. If the high-speed Ring-OSC oscillator or external clock input is selected as the system clock source, no wait time elapses. The system clock oscillator and the oscillation stabilization time that elapses after power application or releas e of reset are selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE. OSTS is set by using an 8-bit memory manipulation instruction.

Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS)

Address: FFF4H, After reset: Undefined, R/W

Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0

OSTS1 OSTS0 Selection of oscillation stabilization time

0 0 0 1 1 0 1 1

/fX（102.4 µs）

/fX（409.6 µs）

/fX（3.27 ms）

/fX（13.1 ms）

Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows. Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time set by

OSTS

2. The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation (“a” in the figure below), regardless of whether STOP mode was released by reset input or interrupt generation.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

STOP mode is released

Voltage

waveform

of X1 pin

Caution 3. The oscillation stabilization time that elapses on power application or after release of reset is

selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.

Remarks 1. ( ): f

X = 10 MHz

2. Determine the oscillation stabilizati on time of the resonator by checking the characteristics of the resonator to be used.

5.4 System Clock Oscillators

The following three types of system clock oscillators are available.

• High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.).

• Crystal/ceramic oscillator: Oscillates a clock of 500 kHz to 10 MHz.

• External clock input circuit: Supplies a clock of 500 kHz to 10 MHz to the X1 pin.

5.4.1 High-speed Ring-OSC oscillator

The 78K0S/KA1+ includes a high-speed Ring-OSC oscillator (8 MHz (TYP.)). If the high-speed Ring-OSC is selected by the option byte as the clock source, the X1 and X2 pins can be used as

I/O port pins.

For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4

PORT FUNCTIONS.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

5.4.2 Crystal/ceramic oscillator

The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2

pins.

If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are

used as crystal or ceramic resonator connection pins.

For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4

PORT FUNCTIONS.

Figure 5-7 shows the external circuit of the crystal/ceramic oscillator.

Figure 5-7. External Circuit of Crystal/Ceramic Oscillator

Crystal resonator or ceramic resonator

Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken

lines in Figure 5-7 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the osc illator capacitor the same potential as V

SS. Do not

ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

Figure 5-8 shows examples of incorrect resonator connection.

Figure 5-8. Examples of Incorrect Resonator Connection (1/2)

(a) Too long wiring of connected circuit (b) Crossed signal lines

PORT

VSS

X1 X2

VSS

X1 X2

(d) Current flowing through ground line of oscillator

(Potential at points A, B, and C fluctuates.)

PORT

X1 X2

High current

AB C

High current

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

Figure 5-8. Examples of Incorrect Resonator Connection (2/2)

(e) Signals are fetched

X1 X2

5.4.3 External clock input circuit

This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by the option byte as the system clock source, the X2 pin ca n be used as an I/O

port pin.

For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4

PORT FUNCTIONS.

Figure 5-9 shows an external circuit of the external clock input circuit.

Figure 5-9. External Circuit of External Clock Input Circuit

External clock

5.4.4 Prescaler

The prescaler divides the clock (f

X) output by the system clock oscillator to generate a clock (fXP) to be supplied to

the peripheral hardware. It also divides the clock to peripheral hardware (f XP) to generat e a clock t o be suppl ie d to the CPU.

Remark The clock output by the oscillator selected by the option byte (high-speed Ring-OSC oscillator,

crystal/ceramic oscillator, or external clock input circuit) is divided. For details of the option byte, refer to CHAPTER 17 OPTION BYTE.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

5.5 Operation of CPU Clock Generator

A clock (fCPU) is supplied to the CPU from the system clock (fX) oscillated by one of the following three types of

oscillators.

• High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.).

• Crystal/ceramic oscillator: Oscillates a clock of 500 kHz to 10 MHz.

• External clock input circuit: Supplies a clock of 500 kHz to 10 MHz to X1 pin.

The system clock oscillator is selected by the option byte. For details of the option byte, refer to CHAPTER 17

OPTION BYTE.

(1) High-speed Ring-OSC oscillator

When the high-speed Ring-OSC oscillator is selected by the option byte, the following is possible.

• Shortening of start time If the high-speed Ring-OSC oscillator is selected as the oscillator, the C PU can be started without having to wait for the oscillation stabilization time of the system clock. Therefore, the start time can be shortened.

• Improvement of expandability If the high-speed Ring-OSC oscillator is selected as the oscillator, the X1 and X2 pins can be used as I/O port pins. For details, refer to CHAPTER 4 PORT FUNCTIONS.

Figures 5-10 and 5-11 show the timing chart and status transition diagram of the default start by the high-speed Ring-OSC oscillator.

Remark When the hi gh-speed Ring-OSC oscillator is used, the clock accuracy is ±5%.

Figure 5-10. Timing Chart of Default Start by High-Speed Ring-OSC Oscillator

(a)

Remark f f

RESET

Internal reset

System clock

CPU clock

RL: Low-speed Ring-OSC clock oscillation frequency RH: High-speed Ring-OSC clock oscillation frequency

Option byte is read.

System clock is selected.

(Operation stops: 8/f

Preliminary User’s Manual U16898EJ1V0UD

+ 96/fRH)

(b)

High-speed Ring-OSC clock

PCC = 02H, PPCC = 02H

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

(a) The internal re set signal is generated by the power-on cl ear function on power applic ation, the option byte is

referenced after reset, and the system clock is selected.

(b) The option byte is referenced and the system clock is selected. Then the high-speed Ring-OSC clock

operates as the system clock.

Figure 5-11. Status Transition of Default Start by High-Speed Ring-OSC

Power

application

VDD > 2.1 V ±0.1 V

Reset by

power-on clear

Reset signal

High-speed Ring-OSC selected by option byte

Start with PCC = 02H, PPCC = 02H

Clock division ratio

variable during

CPU operation

Interrupt

HALT STOP

HALT

instruction

STOP

instruction

Interrupt

Remark PCC: Processor clock control register PPCC: Preprocessor clock control register

(2) Crystal/ceramic oscillator

If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 500 kHz to 10 MHz can be selected and the accuracy of processing is improved becau se the frequency deviation i s small, as compared wit h high-speed Ring-OSC oscillation (8 MHz (TYP.)). Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by the crystal/ceramic oscillator.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

Figure 5-12. Timing Chart of Default Start by Crystal/Ceramic Oscillator

(a)

RESET

Internal reset

(b)

System clock

(c)

CPU clock

Option byte is read.

System clock is selected.

(Operation stops: 8/f

+ 96/fRH)

Clock oscillation

stabilization

Note

time

Crystal/ceramic

oscillator clock

PCC = 02H, PPCC = 02H

Note The clock oscillation stabiliz ation time for default start is selected by the option byte. For details, refer to

CHAPTER 17 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is

released is selected by the oscillation stabilization time select register (OSTS).

Remark f f

RL: Low-speed Ring-OSC clock oscillation frequency RH: High-speed Ring-OSC clock oscillation frequency

(a) The internal reset signal is generated by the power- on clear function on power applic ation, the option byte is

referenced after reset, and the system clock is selected.

(b) After high-speed Ring-OSC clock is generated, the option byte is referenced and the system clock is

selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.

oscillation is stabilized. The wait time is selected by th e option byte. For details, refer to CHAPTER 17

OPTION BYTE.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

Figure 5-13. Status Transition of Default Start by Crystal/Ceramic Oscillation

Power

application

> 2.1 V ±0.1 V

Reset by

power-on clear

Reset signal

Crystal/ceramic

oscillation selected

by option byte

Start with PCC = 02H, PPCC = 02H

Wait for clock

oscillation stabilization

Clock division ratio

variable during

CPU operation

Interrupt

HALT STOP

HALT

instruction

STOP

instruction

Interrupt

Remark PCC: Processor clock control register PPCC: Preprocessor clock control register

(3) External clock input circuit

If external clock input is selected by the option byte, the following is possible.

• High-speed operation The accuracy of processing is improved as compared with high-speed Ring-OSC osci llation (8 MHz (TYP.)) because an oscillation frequency of 500 kHz to 10 MHz can be selected and an external clock with a smal l frequency deviation can be supplied.

• Improvement of expandability If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For details, refer to CHAPTER 4 PORT FUNCTIONS.

Figures 5-14 and 5-15 show the timing chart and status transition diagram of default start by external clock input.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

Figure 5-14. Timing of Default Start by External Clock Input

(a)

RESET

Internal reset

System clock

CPU clock

(b)

External clock input

PCC = 02H, PPCC = 02H

Option byte is read.

System clock is selected.

(Operation stops: 8/f

+ 96/fRH)

Remark f

RL: Low-speed Ring-OSC clock oscillation frequency

fRH: High-speed Ri ng-OSC clock oscillation frequency

(a) The internal reset signal is generated by the power- on clear function on power applic ation, the option byte is

referenced after reset, and the system clock is selected.

(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the

system clock.

Figure 5-15. Status Transition of Default Start by External Clock Input

Power

application

Reset by

power-on clear

External clock input

selected by option byte

Clock division ratio

variable during

CPU operation

Interrupt

HALT

instruction

Remark PCC: Processor clock control register PPCC: Preprocessor clock control register

> 2.1 V ±0.1 V

Start with PCC = 02H, PPCC = 02H

Interrupt

STOP

instruction

STOP

Reset signal

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware

The following two types of clocks are supplied to the peripheral hardware.

• Clock to peripheral hardware (f

• Low-speed Ring-OSC clock (fRL)

(1) Clock to peripheral hardware

The clock to the peripheral hardware is supplied by dividing the system clock (f by the pre-processor clock control register (PPCC). Three types of frequencies are selectable: “f peripheral hardware.

PPCC1 PPCC0 Selection of clock to peripheral hardware (fXP)

0 0 fX 0 1 fX/2 1 0 fX/22 1 1 Setting prohibited

XP)

X”, “fX/2”, and “fX/2

”. Table 5-3 lists the clocks supplied to the

Table 5-3. Clocks to Peripheral Hardware

X). The division ratio is selected

(2) Low-speed Ring-OSC clock

The low-speed Ring-OSC oscillator of the clock oscillator for interval time generation is always started after release of reset, and oscillates at 240 kHz (TYP.). It can be specified by the option byte whether the low-s peed Ring-OSC oscillator can or cannot be stopped by software. If it is specified that the low-speed Ring-OSC oscillator can be stopped by software, oscillation can be started or stopped by using the low-speed Ring-OSC mode register (LSRCM). If it is specified that it cannot be stopped by software, the clock source of WDT is fixed to the low-speed Ring-OSC clock (fRL). The low-speed Ring-OSC oscillator is independent of the CPU clock. If it is used as the source clock of WDT, therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-spee d Ring-OSC oscillator is used as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status. Table 5-4 shows the operation status of the low-speed Ring-OSC oscillator when it is selected as the source clock of WDT and the count clock of 8-bit timer H1. Figure 5-16 shows the status transition of the low-speed Ring-OSC oscillator.

Table 5-4. Operation Status of Low-Speed Ring-OSC Oscillator

Option Byte Setting CPU Status WDT Status TMH1 Status

Can be stopped by software

LSRSTOP = 1 Stopped Stopped

LSRSTOP = 0

LSRSTOP = 1 Stopped Stopped

LSRSTOP = 0

Operation mode

Standby

Operation mode Cannot be stopped Standby

Operates Operates

Stopped Operates Operates

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 5 CLOCK GENERATORS

www.DataSheet4U.com

Figure 5-16. Status Transition of Low-Speed Ring-OSC Oscillator

Power

application

> 2.1 V ±0.1 V

Reset by

power-on clear

Reset signal

Select by option byte

if low-speed Ring-OSC

can be stopped or not

Clock source of WDT is selected by software

Note

Can be stopped

Low-speed Ring-OSC

oscillator can be stopped

Cannot be stopped

Low-speed Ring-OSC

oscillator cannot be stopped

Clock source of WDT is fixed to f

LSRSTOP = 1

LSRSTOP = 0

Low-speed Ring-OSC

oscillator stops

Note The clock source of the watchdog timer (WDT) is selected from f XP or fRL, or it may be stopped. For details,

refer to CHAPTER 9 WATCHDOG TIMER.

Preliminary User’s Manual U16898EJ1V0UD

www.DataSheet4U.com

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.1 Functions of 16-Bit Timer/Event Counter 00

16-bit timer/event counter 00 has the following functions.

(1) Interval timer

16-bit timer/event counter 00 generates interrupt requests at the preset time interval.

• Number of counts: 2 to 65536

(2) External event counter

16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of a signal inpu t externally.

• Valid level pulse width: 16/f

(3) Pulse width measurement

16-bit timer/event counter 00 can measure the pulse width of an externally input signal.

• Valid level pulse width: 2/f

(4) Square-wave output

16-bit timer/event counter 00 can output a square wave with any selected frequency.

• Cycle: (2 × 2 to 65536 × 2) × count clock cycle

(5) PPG output

16-bit timer/event counter 00 can output a square wave that have arbitrary cycle and pulse width.

• 2 < Pulse width < Cycle ≤ (FFFF + 1) H

(6) One-shot pulse output

16-bit timer/event counter 00 can output a one-shot pulse for which output pulse width can be set to any desired value.

XP or more

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

6.2 Configuration of 16-Bit Timer/Event Counter 00

16-bit timer/event counter 00 consists of the following hardware.

Table 6-1. Configuration of 16-Bit Timer/Event Counter 00

Item Configuration Timer counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010 Timer output TO00, output controller Control registers

Figures 6-1 shows a block diagram of these counters.

Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00

Capture/compare control register 00 (CRC00)

CRC002CRC001 CRC000

16-bit timer mode control register 00 (TMC00) Capture/compare control register 00 (CRC00) 16-bit timer output control register 00 (TOC00) Prescaler mode register 00 (PRM00) Port mode register 3 (PM3) Port register 3 (P3)

Internal bus

TI010/TO00/ INTP2/P31

TI000/INTP0/P30

Prescaler mode register 00 (PRM00)

INTTM000

Output latch

LVS00 LVR00

16-bit timer output control register 00 (TOC00)

(P31)

INTTM010

TOC001

TO00/TI010/ INTP2/P31

PM31

TOE00

Clear

OSPT00

Selector

OSPE00

Output controller

TOC004

Noise eliminator

fXP/2

Noise eliminator

PRM001

Selector

Noise eliminator

PRM000

16-bit timer capture/compare register 000 (CR000)

Selector

16-bit timer counter 00 (TM00)

16-bit timer capture/compare register 010 (CR010)

CRC002

TMC003 TMC002

Internal bus

Match

TMC001

OVF00

16-bit timer mode control register 00 (TMC00)

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

(1) 16-bit timer counter 00 (TM00)

TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.

Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)

Address: FF12H, FF13H After reset: 0000H R

Symbol

FF13H FF12H

TM00

The count value is reset to 0000H in the following cases.

<1> At reset input <2> If TMC003 and TMC002 are cleared <3> If the valid edge of TI000 is input in the clear & start mode entered by inputting the valid edge of TI000 <4> If TM00 and CR000 match in the clear & start mode entered on a match between TM00 and CR000 <5> If OSPT00 is set in the one-shot pulse output mode

(2) 16-bit timer capture/compare register 000 (CR000)

CR000 is a 16-bit register which has the functions of both a capture reg ister and a compare register. Whether it is used as a capture register or as a compare regist er is set by bit 0 (CRC000) of capture/compare c ontrol register 00 (CRC00). CR000 is set by 16-bit memory manipulation instruction. A reset clears CR000 to 0000H.

Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000)

Address: FF14H, FF15H After reset: 0000H R/W Symbol

FF15H FF14H

CR000

• When CR000 is used as a compare register

The value set i n CR000 is co nstantly compa red with th e 16-bit timer/count er 00 (TM 00) c ount val ue, an d an

interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the interval time then TM00 is set to interval timer operation.

• When CR000 is used as a capture register

It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the

TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 6-

2).

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins

(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)

CR000 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Rising edge 0 1 Rising edge Falling edge 0 0 No capture operation Both rising and falling edges 1 1

(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)

CR000 Capture Trigger TI010 Pin Valid Edge ES110 ES100 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1

Remarks 1. Setting ES010, ES000 = 1, 0 and ES1 10, ES100 = 1, 0 is prohibited.

2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) ES110, ES100: Bits 7 and 6 of prescaler mode register 00 (PRM00) CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)

Cautions 1. Set CR000 to a value other than 0000H in the clear & start mode entered on a match

between TM00 and CR000. However, in the free-running mode and in the clear & start mode using the valid edge of TI000, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H following overflow (FFFFH).

2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00 continues counting, overflows, and then starts counting from 0 again. If the new value of CR000 is less than the old value, therefore, the timer must be reset to be restarted after the value of CR000 is changed.

3. When P31 is used as the input pin for the valid edge of TI010, it cannot be used as a timer output (TO00). Moreover, when P31 is used as TO00, it cannot be used as the input pin for the valid edge of TI010.

4. If the register read period and the input of the capture trigger conflict when CR000 is used as a capture register, the read data is undefined (the capture data itself is a normal value). Also, if the count stop input and the input of the capture trigger conflict, the capture trigger is undefined.

5. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (11) Changing compare register during timer operation.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

(3) 16-bit capture/compare register 010 (CR010)

CR010 is a 16-bit register which has the functions of both a capture regis ter and a compare register. Whether it is used as a capture register or a compare regist er is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00). CR010 is set by 16-bit memory manipulation instruction. Reset input clears CR010 to 0000H.

Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)

Address: FF16H, FF17H After reset: 0000H R/W Symbol

FF17H FF16H

CR010

• When CR010 is used as a compare register

The value set i n CR010 is co nstantly comp a red with the 16-bit timer counter 00 (TM00) count value, and an

interrupt request (INTTM010) is generated if they match.

• When CR010 is used as a capture register

It is possible to select the valid edge of the TI000 pin as the capture trigg er. The TI000 valid edge is set by

means of prescaler mode register 00 (PRM00) (refer to Table 6-3).

Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)

CR010 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1

Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited.

2. ES010, ES000: Bits 5 and 4 of prescal er mode register 00 (PRM00) CRC002: Bit 2 of capture/compare control register 00 (CRC00)

Cautions 1. Set CR010 to other than 0000H in the clear & start mode entered on a match between

TM00 and CR000. However, in the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010 changes from 0000H to 0001H following overflow (FFFFH).

2. If the register read period and the input of the capture trigger conflict when CR010 is used as a capture register, the read data is undefined (the capture data itself is a normal value). Also, if the count stop input and the input of the capture trigger conflict, the capture data is undefined.

3 Changing the CR010 setting during TM00 operation may cause a malfunction. To change

the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (11) Changing compare register during timer operation.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

6.3 Registers to Control 16-Bit Timer/Event Counter 00

The following six types of registers are used to control 16-bit timer/event counter 00.

• 16-bit timer mode control register 00 (TMC00)

• Capture/compare control register 00 (CRC00)

• 16-bit timer output control register 00 (TOC00)

• Prescaler mode register 00 (PRM00)

• Port mode register 3 (PM3)

• Port register 3 (P3)

(1) 16-bit timer mode control register 00 (TMC00)

This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output timing, and detects an overflow. TMC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of TMC00 to 00H.

Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003

(operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the operation.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)

Address: FF60H After reset: 00H R/W

Symbol

<0>

TMC00

TMC0032TMC0021TMC001

OVF00

TMC003 TMC002 TMC001

0 0 0 0 0 1 0 1 0 Free-running mode

0 1 1

1 0 0 1 0 1 1 1 0

1 1 1

Operating mode and clear

mode selection

Operation stop (TM00 cleared to 0)

Clear & start occurs on valid edge of TI000 pin

Clear & start occurs on match between TM00 and CR000

TO00 inversion timing selection Interrupt request generation

No change Not generated

Match between TM00 and CR000 or match between TM00 and CR010

Match between TM00 and CR000, match between TM00 and CR010 or TI000 valid edge

−

Match between TM00 and CR000 or match between TM00 and CR010

Match between TM00 and CR000, match between TM00 and CR010 or TI000 valid edge

Generated on match between TM00 and CR000, or match between TM00 and CR010

OVF00 Overflow detection of 16-bit timer counter 00 (TM00)

0 Overflow not detected 1 Overflow detected

Cautions 1. To write different data to TMC00, stop the timer operation before writing.

2. The timer operation must be stopped before writing to bits other than the OVF00 flag.

3. Set the valid edge of the TI000/INTP0/P30 pin with prescaler mode register 00 (PRM00).

4. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at the valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1.

Remark TM00: 16-bit timer counter 00

CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

(2) Capture/compare control register 00 (CRC00)

This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of CRC00 to 00H.

Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)

Address: FF62H After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0 CRC00 0 0 0 0 0 CRC002 CRC001 CRC000

CRC002 CR010 operating mode selection 0 Operate as compare register 1 Operate as capture register

CRC001 CR000 capture trigger selection 0 Capture on valid edge of TI010 pin 1 Capture on valid edge of TI000 pin by reverse phase

CRC000 CR000 operating mode selection 0 Operate as compare register 1 Operate as capture register

Cautions 1. The timer operation must be stopped before setting CRC00.

2. When the clear & start mode entered on a match between TM00 and CR000 is selected by 16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a capture register.

3. If both the rising and falling edges have been selected as the valid edges of the TI000 pin, capture is not performed.

4. To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (PRM00) (refer to Figure 6-17).

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

(3) 16-bit timer output control register 00 (TOC00)

This register controls the operation of the 16-bit timer/event counter output contro ller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-sh ot pulse output operation enable/disable, and output trigger of one-shot pulse by software. TOC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of TOC00 to 00H.

Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)

Address: FF63H After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0>

TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

OSPT00 One-shot pulse output trigger control via software

0 No one-shot pulse trigger 1 One-shot pulse trigger

OSPE00 One-shot pulse output operation control

0 Successive pulse output mode 1 One-shot pulse output mode

Note

TOC004 Timer output F/F control using match of CR010 and TM00

0 Disables inversion operation 1 Enables inversion operation

LVS00 LVR00 Timer output F/F status setting

0 0 No change 0 1 Timer output F/F reset (0) 1 0 Timer output F/F set (1) 1 1 Setting prohibited

TOC001 Timer output F/F control using match of CR000 and TM00

0 Disables inversion operation 1 Enables inversion operation

TOE00 Timer output control

0 Disables output (output fixed to level 0) 1 Enables output

Note The one-sh ot pulse output mode operates correctly only in the free-running mode and the mode in which

clear & start occurs at the TI000 pin valid edge. In the mode in whic h clear & start occurs on a match between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur.

Cautions 1. Timer operation must be stopped before setting other than OSPT00.

2. If LVS00 and LVR00 are read, 0 is read.

3. OSPT00 is automatically cleared after data is set, so 0 is read.

4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.

5. A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00) is required to write to OSPT00 successively.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

(4) Prescaler mode register 00 (PRM00)

This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges. PRM00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of PRM00 to 00H.

Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)

Address: FF61H After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0 PRM00 ES110 ES100 ES010 ES000 0 0 PRM001 PRM000

ES110 ES100 TI010 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges

ES010 ES000 TI000 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges

PRM001 PRM000 Count clock selection 0 0 fXP (10 MHz) 0 1 fXP/22 (2.5 MHz) 1 0 fXP/28 (39.06 kHz) 1 1 TI000 pin valid edge

Note The external clock requires a pulse longer than two cycles of the internal count clock (f

Cautions 1. Always set data to PRM00 after stopping the timer operation.

2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin.

3. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00). Be careful when pulling up the TI000 pin or the TI010 pin. However, when re-enabling operation after the operation has been stopped once, the rising edge is not detected.

4. When using P31 as the input pin of the TI010 pin valid edge, it cannot be used as a timer output (TO00). When using P31 as the TO00 pin, it cannot be used as the input pin of the TI010 pin valid edge.

Remarks 1. f

2. ( ): f

XP: Oscillation frequency of clock supplied to peripheral hardware

XP = 10 MHz

Note

XP).

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

(5) Port mode register 3 (PM3)

This register sets port 3 input/output in 1-bit units. When using the P31/TO00/TI010/INTP2 pin for timer output, set PM31 and the output latch of P31 to 0. When using the P30/TI000/INTP0 and P31/TO00/TI010/INTP2 pins as a timer input, set PM30 and PM31 to 1. At this time, the output latches of P30 and P31 can be either 0 or 1. PM3 is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets the value of PM3 to FFH.

Figure 6-9. Format of Port Mode Register 3 (PM3)

Address: FF23H After reset: FFH R/W

Symbol

PM3

PM3n

P3n pin I/O mode selection (n = 0 or 1)

Output mode (output buffer on)

Input mode (output buffer off)

11PM310PM30

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

6.4 Operation of 16-Bit Timer/Event Counter 00

6.4.1 Interval timer operation

Setting 16-bit timer mode control register 00 (TMC00) and capture/compar e control register 00 (CRC00) as shown

in Figure 6-10 allows operation as an interval timer.

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-10 for the set value). <2> Set any value to the CR000 register. <3> Set the count clock by using the PRM00 register. <4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value).

Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the

setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (11) Changing compare register during timer operation.

Remark For how to ena ble the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS.

Interrupt requests are generated repeatedly using the count value s et in 16-bit timer capture/compare register 000

(CR000) beforehand as the interval.

When the count value of 16-bit timer counter 00 (TM00) matches the v alue set to CR000, counting continues with

the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.

The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM000, PRM001) of

prescaler mode register 00 (PRM00).

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

Figure 6-10. Control Register Settings for Interval Timer Operation

(a) 16-bit timer mode control register 00 (TMC00)

40TMC0031TMC0021TMC001

0/1

OVF00

0TMC00

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

30CRC002

0/1

CRC001

0/1

CRC000

0CRC00

CR000 used as compare register

ES110

ES100

ES010

0/1

ES000

0/130

2 0

PRM001

0/1

PRM000

0/1PRM00

Selects count clock.

Setting invalid (setting “10” is prohibited.) Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the

description of the respective control registers for details.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

Figure 6-11. Interval Timer Configuration Diagram

16-bit timer capture/compare register 000 (CR000)

fXP/2 fXP/2

TI000/INTP0/P30

Noise eliminator

Selector

16-bit timer counter 00 (TM00)

Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.

Figure 6-12. Timing of Interval Timer Operation

INTTM000

Note

OVF00

Clear circuit

Count clock

TM00 count value

CR000

INTTM000

0000H

Timer operation enabled Clear Clear

0001H

0000H 0001H

Interrupt acknowledged Interrupt acknowledged

0000H 0001H

NNNN

Remark Interval time = (N + 1) × t N = 0001H to FFFFH

When the compare register is changed during timer count operati on, if the value after 16- bit timer captur e/compare register 000 (CR000) is changed is smalle r than that of 16-bit timer counter 00 (TM00), TM00 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is sm aller than that (N) before the change, it is necessary to restart the timer after changing CR000.

Figure 6-13. Timing After Change of Compare Register During Timer Count Operation

Count clock

Remark N > X > M

CR000

TM00 count value

X – 1 X FFFFH 0000H 0001H 0002H

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

6.4.2 External event counter operation

Setting The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-14 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set any value to the CR000 register (0000H cannot be set). <4> Set the TMC00 register to start the operation (see Figure 6-14 for the set value).

Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 3 (PM3).

2. For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS.

The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit

timer counter 00 (TM00).

TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is

cleared to 0 and the interrupt request signal (INTTM000) is generated.

Input a value other than 0000H to CR000. (A count operation with a pulse cannot be carried out.) The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of

prescaler mode register 00 (PRM00).

Because an operation is carried out only when the valid edge of the TI000 pin is detec ted twice after sampling with

the internal clock (f

XP), noise with a short pulse width can be removed.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

Figure 6-14. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

40TMC0031TMC0021TMC001

0/1

OVF00

0TMC00

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

30CRC002

0/1

CRC001

0/1

CRC000

0CRC00

CR000 used as compare register

ES110

ES100

0/1

ES0100ES000

0/1

PRM0011PRM000

2 0

1PRM00

Selects external clock. Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.

See the description of the respective control registers for details.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

Figure 6-15. External Event Counter Configuration Diagram

Internal bus

16-bit timer capture/compare

Match

Clear

Valid edge of TI000

Noise eliminator

16-bit timer counter 00 (TM00)

Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.

Figure 6-16. External Event Counter Operation Timing (with Rising Edge Specified)

TI000 pin input

TM00 count value

CR000

INTTM000

0000H 0001H 0002H 0003H 0004H 0005H

N–1 N

0000H 0001H 0002H 0003H

Caution When reading the external event counter count value, TM00 should be read.

OVF00

INTTM000

Note

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

6.4.3 Pulse width measurement operations

It is possible to measure the pulse width of the signals input to th e TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00).

There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.

When an interrupt occurs, read the valid value of the capture regist er, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it.

The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width.

Figure 6-17. CR010 Capture Operation with Rising Edge Specified

Count clock

TM00

TI000

Rising edge detection

CR010

INTTM010

N − 3N − 2N − 1 N N + 1

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value).

<2> Set the count clock by using the PRM00 register.

<3> Set the TMC00 register to start the operation (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value).

Caution To use two capture registers, set the TI000 and TI010 pins.

Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 3 (PM3).

2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

(1) Pulse width measurement with free-running counter and one capture register

When 16-bit timer counter 00 (TM00) is operated in free-runni ng mode, and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set. Specify both the rising and falling edges by using bits 4 and 5 (ES000 and ES010) of PRM00. Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.

Figure 6-18. Control Register Settings for Pulse Width Measurement with Free-Running Counter

and One Capture Register (When TI000 and CR010 Are Used)

(a) 16-bit timer mode control register 00 (TMC00)

40TMC0030TMC0021TMC001

0/1

OVF00

0TMC00

Free-running mode

(b) Capture/compare control register 00 (CRC00)

30CRC0021CRC001

0/1

CRC000

0CRC00

CR000 used as compare register CR010 used as capture register

ES101

0/1

ES100

0/1

ES0101ES000

PRM001

PRM000

0/1

0/1PRM00

Selects count clock (setting “11” is prohibited). Specifies both edges for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter

fXP/2 fXP/2

Selector

16-bit timer/counter 00

(TM00)

OVF00

Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified)

Count clock

TM00 count value

TI000 pin input

CR010 capture value

INTTM010

OVF00

TI000/INTP0/P30

0000H 0000H

0001H

D0 + 1

16-bit timer capture/compare register 010 (CR010)

Internal bus

D1 + 1

D1 D2 D3

FFFFH

INTTM010

D2 D3

Note

Note OVF00 must be cleared by software.

(D1 − D0) × t (D3 − D2) × t(10000H − D1 + D2) × t

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

(2) Measurement of two pulse widths with free-running counter

When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (E S000 and ES010) of prescaler mode reg ister 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the edge specified by bits 6 and 7 (ES100 and ES110) of PRM00 is input to the TI010 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal (INTTM000) is set. Specify both the rising and falling edges as the e dges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000 and ES010) and bits 6 and 7 (ES100 and ES110) of PRM00. Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width.

Figure 6-21. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter

(a) 16-bit timer mode control register 00 (TMC00)

40TMC0030TMC0021TMC001

0/1

OVF00

0TMC00

Free-running mode

(b) Capture/compare control register 00 (CRC00)

30CRC0021CRC0010CRC000

1CRC00

CR000 used as capture register Captures valid edge of TI010 pin to CR000. CR010 used as capture register

ES1101ES1001ES0101ES000

PRM001

PRM000

0/1

0/1PRM00

Selects count clock (setting “11” is prohibited). Specifies both edges for pulse width detection. Specifies both edges for pulse width detection.

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

Preliminary User’s Manual U16898EJ1V0UD

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

www.DataSheet4U.com

Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified)

Count clock

0000H 0000H

TM00 count value

TI000 pin input

CR010 capture value

INTTM010

TI010 pin input

CR000 capture value

INTTM000

OVF00

0001H

Note OVF00 must be cleared by software.

D0 + 1

(D1 − D0) × t (D3 − D2) × t(10000H − D1 + D2) × t

D1 + 1 D2 + 1 D2 + 2

(10000H − D1 + (D2 + 1)) × t

FFFFH

D2 D3

D2 + 1D1

Note

100

Preliminary User’s Manual U16898EJ1V0UD

NEC 78K0S/KA1+, mPD78F9221, mPD78F9222 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CHAPTER 1 OVERVIEW

CHAPTER 2 PIN FUNCTIONS

CHAPTER 3 CPU ARCHITECTURE

CHAPTER 4 PORT FUNCTIONS

CHAPTER 5 CLOCK GENERATORS

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00