NEC mPD780208 Sub, mPD780204, mPD780206, mPD780208, mPD78P0208 User Manual

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PD780208 Subseries

8-Bit Single-Chip Microcontrollers

PD780204

PD780204A

PD780205

PD780205A

PD780206

PD780208

PD78P0208

Document No. U11302EJ4V0UM00 (4th edition) Date Published July 2003 N CP(K)

Printed in Japan

User’s Manual

User’s Manual U11302EJ4V0UM

[MEMO]

User’s Manual U11302EJ4V0UM

FIP and IEBus are trademarks of NEC Electronics Corporation.

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TRON stands for The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

User’s Manual U11302EJ4V0UM

The information in this document is current as of January, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

•

M8E 02. 11-1

These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.

User’s Manual U11302EJ4V0UM

Regional Information

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

[GLOBAL SUPPORT] http://www.necel.com/en/support/support.html

NEC Electronics America, Inc. (U.S.)

Santa Clara, California Tel: 408-588-6000 800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong Tel: 2886-9318

NEC Electronics Hong Kong Ltd.

Seoul Branch Seoul, Korea Tel: 02-558-3737

NEC Electronics Shanghai, Ltd.

Shanghai, P.R. China Tel: 021-6841-1138

NEC Electronics Taiwan Ltd.

Taipei, Taiwan Tel: 02-2719-2377

NEC Electronics Singapore Pte. Ltd.

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EC Electronics (Europe) GmbH

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• Sucursal en España

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• Succursale Française

• Filiale Italiana

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• Branch The Netherlands

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• Tyskland Filial

Taeby, Sweden Tel: 08-63 80 820

• United Kingdom Branch

Milton Keynes, UK Tel: 01908-691-133

Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:

User’s Manual U11302EJ4V0UM

Major Revisions in This Edition

Page Description

Throughout Addition of the following products to target products

•

PD780204A

• µPD780205A Deletion of the following package from target products

• µPD78P0208KL-T (100-pin ceramic WQFN)

CHAPTER 1 OUTLINE

p.29 • Update of 1.6 78K/0 Series Lineup p.32 • Addition of Note in 1.8 Overview of Functions p.33 • Addition of Caution in Table 1-1 Mask Options in Mask ROM Versions

CHAPTER 2 PIN FUNCTIONS

p.42 • Addition of 2.2.12 VLOAD p.43 • Modification of Table 2-1 Types of Pin I/O Circuits

CHAPTER 3 CPU ARCHITECTURE

p.48 • Addition of Caution in 3.1 Memory Space p.67 • Modification of Note in Table 3-3 Special-Function Register List

CHAPTER 4 PORT FUNCTIONS

p.90 • Addition of Caution in 4.2.6 Port 8 p.91 • Addition of Caution in 4.2.7 Port 9 p.92 • Addition of Caution in 4.2.8 Port 10 p.93 • Addition of Caution in 4.2.9 Port 11 p.94 • Addition of Caution in 4.2.10 Port 12

CHAPTER 5 CLOCK GENERATOR

p.103 • Addition of Note in Figure 5-3 Format of Processor Clock Control Register

CHAPTER 6 16-BIT TIMER/EVENT COUNTER

p.133 • Modification of Caution in Figure 6-8 Format of External Interrupt Mode Register p.144 • Modification of 6.6 (5) Valid edge setting

CHAPTER 8 WATCH TIMER

p.171 • Modification of Caution in Figure 8-2 Format of Timer Clock Select Register 2

CHAPTER 9 WATCHDOG TIMER

p.178 • Modification of Caution in Figure 9-2 Format of Timer Clock Select Register 2

CHAPTER 11 BUZZER OUTPUT CONTROLLER

p.188 • Modification of Caution in Figure 11-2 Format of Timer Clock Select Register 2

CHAPTER 16 INTERRUPT AND TEST FUNCTIONS

p.340 • Addition of Caution in Figure 16-2 Format of Interrupt Request Flag Register p.343 • Modification of Caution in Figure 16-5 Format of External Interrupt Mode Register

CHAPTER 17 STANDBY FUNCTION

p.361 • Addition of description in Table 17-1 HALT Mode Operating Status p.364 • Addition of description in Table 17-3 STOP Mode Operating Status

CHAPTER 19 µPD78P0208

p.373 • Modification of Table 19-2 Internal Memory Size Switching Register Setting Values

APPENDIX A DIFFERENCES BETWEEN µPD78044H, 780228, AND 780208 SUBSERIES

p.398 • Modification of description in Table A-1 Major Differences Between µPD78044H, 780228, and

780208 Subseries

APPENDIX B DEVELOPMENT TOOLS

p.399 • Modification of description

The mark shows major revised points.

User’s Manual U11302EJ4V0UM

INTRODUCTION

Readers This manual has been prepared for user engineers who wish to understand the functions of the

PD780208 Subseries and design and develop its application systems and programs.

Purpose This manual is intended to give users an understanding of the functions described in the Organization

below.

Organization The

PD780208 Subseries manual consists of two parts: this manual and Instructions (common to

the 78K/0 Series)

PD780208 Subseries 78K/0 Series

User’s Manual Instructions

(This manual) User’s Manual

• Pin functions • CPU functions

• Internal block functions • Instruction set

• Interrupts • Explanation of each instruction

• Other on-chip peripheral functions

How to Read This Manual

It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers.

• For an understanding of functions in general:

→ Read this manual in the order of the CONTENTS.

• For how to interpret the register format:

→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the

RA78K0, and is defined in the header file named sfrbit.h in the CC78K0.

• To confirm the details of a register whose register name is known:

→ Refer to APPENDIX C REGISTER INDEX.

• For the details of

PD780208 Subseries instruction functions:

→ Refer to 78K/0 Series Instructions User’s Manual (U12326E).

• For the electrical specifications of the

PD780208 Subseries:

→ Refer to the separate

PD780204, 780205, 780206, 780208 Data Sheet (U10436E) and

PD78P0208 Data Sheet (U11295E).

• For application examples of the

PD780208 Subseries:

→ Refer to the separate 78K/0 Series Basics (II) Application Note (U10121E).

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representation: xxx (overscore over pin or signal name)

Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information

Numerical representation: Binary .................. xxxx or xxxxB

Decimal ............... xxxx

Hexadecimal ....... xxxxH

User’s Manual U11302EJ4V0UM

Other Related Documents

Document Name Document No.

SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X

Semiconductor Device Mount Manual Note

Quality Grades on NEC Semiconductor Devices C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

User’s Manual U11302EJ4V0UM

CONTENTS

CHAPTER 1 OUTLINE ......................................................................................................................... 24

1.1 Features ............................................................................................................................... 24

1.2 Applications ......................................................................................................................... 25

1.3 Ordering Information .......................................................................................................... 25

1.4 Quality Grade ...................................................................................................................... 25

1.5 Pin Configuration (Top View) ............................................................................................ 26

1.6 78K/0 Series Lineup ........................................................................................................... 29

1.7 Block Diagram ..................................................................................................................... 31

1.8 Overview of Functions ....................................................................................................... 32

1.9 Mask Options ...................................................................................................................... 33

CHAPTER 2 PIN FUNCTIONS .............................................................................................................. 34

2.1 Pin Function List ................................................................................................................. 34

2.1.1 Normal operating mode pins .................................................................................................. 34

2.1.2 PROM programming mode pins (

PD78P0208 only) ........................................................... 37

2.2 Description of Pin Functions ............................................................................................ 38

2.2.1 P00 to P04 (Port 0) ................................................................................................................. 38

2.2.2 P10 to P17 (Port 1) ................................................................................................................. 38

2.2.3 P20 to P27 (Port 2) ................................................................................................................. 39

2.2.4 P30 to P37 (Port 3) ................................................................................................................. 39

2.2.5 P70 to P74 (Port 7) ................................................................................................................. 40

2.2.6 P80 to P87 (Port 8) ................................................................................................................. 40

2.2.7 P90 to P97 (Port 9) ................................................................................................................. 40

2.2.8 P100 to P107 (Port 10) ........................................................................................................... 41

2.2.9 P110 to P117 (Port 11) ........................................................................................................... 41

2.2.10 P120 to P127 (Port 12) ........................................................................................................... 41

2.2.11 FIP0 to FIP12 .......................................................................................................................... 41

2.2.12 V

LOAD ........................................................................................................................................ 42

2.2.13 AVREF ....................................................................................................................................... 42

2.2.14 AV

DD ......................................................................................................................................... 42

2.2.15 AVSS ......................................................................................................................................... 42

2.2.16 RESET ..................................................................................................................................... 42

2.2.17 X1 and X2 ................................................................................................................................42

2.2.18 XT1 and XT2 ........................................................................................................................... 42

2.2.19 V

DD ........................................................................................................................................... 42

2.2.20 V

SS ............................................................................................................................................ 42

2.2.21 VPP (µPD78P0208 only) .......................................................................................................... 42

2.2.22 IC (mask ROM version only) .................................................................................................. 42

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................... 43

CHAPTER 3 CPU ARCHITECTURE ....................................................................................................48

3.1 Memory Space ..................................................................................................................... 48

3.1.1 Internal program memory space ............................................................................................ 53

3.1.2 Internal data memory space ................................................................................................... 54

3.1.3 Special-function register (SFR) area ...................................................................................... 54

User’s Manual U11302EJ4V0UM

3.1.4 Data memory addressing ........................................................................................................ 55

3.2 Processor Registers ........................................................................................................... 60

3.2.1 Control registers ...................................................................................................................... 60

3.2.2 General-purpose registers ...................................................................................................... 63

3.2.3 Special-function registers (SFRs)........................................................................................... 64

3.3 Instruction Address Addressing ...................................................................................... 68

3.3.1 Relative addressing................................................................................................................. 68

3.3.2 Immediate addressing ............................................................................................................. 69

3.3.3 Table indirect addressing........................................................................................................ 70

3.3.4 Register addressing ................................................................................................................ 71

3.4 Operand Address Addressing .......................................................................................... 72

3.4.1 Implied addressing .................................................................................................................. 72

3.4.2 Register addressing ................................................................................................................ 73

3.4.3 Direct addressing .................................................................................................................... 74

3.4.4 Short direct addressing ........................................................................................................... 75

3.4.5 Special-function register (SFR) addressing ........................................................................... 76

3.4.6 Register indirect addressing ................................................................................................... 77

3.4.7 Based addressing.................................................................................................................... 78

3.4.8 Based indexed addressing ..................................................................................................... 79

3.4.9 Stack addressing ..................................................................................................................... 79

CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 80

4.1 Port Functions ..................................................................................................................... 80

4.2 Port Configuration .............................................................................................................. 83

4.2.1 Port 0 ....................................................................................................................................... 83

4.2.2 Port 1 ....................................................................................................................................... 85

4.2.3 Port 2 ....................................................................................................................................... 86

4.2.4 Port 3 ....................................................................................................................................... 88

4.2.5 Port 7 ....................................................................................................................................... 89

4.2.6 Port 8 ....................................................................................................................................... 90

4.2.7 Port 9 ....................................................................................................................................... 91

4.2.8 Port 10 ..................................................................................................................................... 92

4.2.9 Port 11 ..................................................................................................................................... 93

4.2.10 Port 12 ..................................................................................................................................... 94

4.3 Port Function Control Registers ...................................................................................... 95

4.4 Port Function Operations .................................................................................................. 98

4.4.1 Writing to I/O port .................................................................................................................... 98

4.4.2 Reading from I/O port ............................................................................................................. 98

4.4.3 Operations on I/O port ............................................................................................................ 98

4.5 Selection of Mask Option .................................................................................................. 99

CHAPTER 5 CLOCK GENERATOR .................................................................................................... 100

5.1 Clock Generator Functions ............................................................................................... 100

5.2 Clock Generator Configuration ......................................................................................... 100

5.3 Clock Generator Control Registers .................................................................................. 102

5.4 System Clock Oscillator .................................................................................................... 109

5.4.1 Main system clock oscillator ................................................................................................... 109

5.4.2 Subsystem clock oscillator ..................................................................................................... 110

User’s Manual U11302EJ4V0UM

5.4.3 Divider ...................................................................................................................................... 113

5.4.4 When subsystem clock is not used ........................................................................................ 113

5.5 Clock Generator Operations ............................................................................................. 114

5.5.1 Main system clock operations ................................................................................................ 115

5.5.2 Subsystem clock operations ................................................................................................... 116

5.6 Changing System Clock and CPU Clock Settings ......................................................... 117

5.6.1 Time required for switchover between system clock and CPU clock .................................. 117

5.6.2 System clock and CPU clock switching procedure ............................................................... 118

CHAPTER 6 16-BIT TIMER/EVENT COUNTER ................................................................................... 119

6.1 Outline of Timers Incorporated in µPD780208 Subseries ............................................ 119

6.2 16-Bit Timer/Event Counter Functions ............................................................................ 120

6.3 16-Bit Timer/Event Counter Configuration ..................................................................... 122

6.4 16-Bit Timer/Event Counter Control Registers .............................................................. 127

6.5 16-Bit Timer/Event Counter Operations .......................................................................... 135

6.5.1 Interval timer operations ......................................................................................................... 135

6.5.2 PWM output operations .......................................................................................................... 137

6.5.3 Pulse width measurement operations .................................................................................... 138

6.5.4 External event counter operation ........................................................................................... 140

6.5.5 Square-wave output operation ............................................................................................... 142

6.6 16-Bit Timer/Event Counter Operating Precautions ...................................................... 143

CHAPTER 7 8-BIT TIMER/EVENT COUNTER .................................................................................... 145

7.1 8-Bit Timer/Event Counter Functions .............................................................................. 145

7.1.1 8-bit timer/event counter mode............................................................................................... 145

7.1.2 16-bit timer/event counter mode ............................................................................................ 148

7.2 8-Bit Timer/Event Counter Configuration ....................................................................... 150

7.3 8-Bit Timer/Event Counter Control Registers ................................................................. 153

7.4 8-Bit Timer/Event Counter Operations ............................................................................ 158

7.4.1 8-bit timer/event counter mode............................................................................................... 158

7.4.2 16-bit timer/event counter mode ............................................................................................ 162

7.5 8-Bit Timer/Event Counter Operating Precautions ........................................................ 166

CHAPTER 8 WATCH TIMER ............................................................................................................... 168

8.1 Watch Timer Functions ...................................................................................................... 168

8.2 Watch Timer Configuration ............................................................................................... 169

8.3 Watch Timer Control Registers ........................................................................................ 169

8.4 Watch Timer Operations .................................................................................................... 173

8.4.1 Watch timer operation ............................................................................................................. 173

8.4.2 Interval timer operation ........................................................................................................... 173

CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 174

9.1 Watchdog Timer Functions ............................................................................................... 174

9.2 Watchdog Timer Configuration ........................................................................................ 175

9.3 Watchdog Timer Control Registers ................................................................................. 177

9.4 Watchdog Timer Operations ............................................................................................. 180

9.4.1 Watchdog timer operation....................................................................................................... 180

9.4.2 Interval timer operation ........................................................................................................... 181

User’s Manual U11302EJ4V0UM

CHAPTER 10 CLOCK OUTPUT CONTROLLER ................................................................................. 182

10.1 Clock Output Controller Functions .................................................................................. 182

10.2 Clock Output Controller Configuration ........................................................................... 183

10.3 Clock Output Function Control Registers ...................................................................... 183

CHAPTER 11 BUZZER OUTPUT CONTROLLER .............................................................................. 186

11.1 Buzzer Output Controller Functions ................................................................................ 186

11.2 Buzzer Output Controller Configuration ......................................................................... 186

11.3 Buzzer Output Function Control Registers .................................................................... 187

CHAPTER 12 A/D CONVERTER ......................................................................................................... 190

12.1 A/D Converter Functions ................................................................................................... 190

12.2 A/D Converter Configuration ............................................................................................ 190

12.3 A/D Converter Control Registers ..................................................................................... 194

12.4 A/D Converter Operations ................................................................................................. 197

12.4.1 Basic operations of A/D converter ......................................................................................... 197

12.4.2 Input voltage and conversion results ..................................................................................... 199

12.4.3 A/D converter operating mode ............................................................................................... 200

12.5 A/D Converter Precautions ............................................................................................... 202

CHAPTER 13 SERIAL INTERFACE CHANNEL 0 ............................................................................... 205

13.1 Functions of Serial Interface Channel 0.......................................................................... 206

13.2 Configuration of Serial Interface Channel 0 ................................................................... 207

13.3 Control Registers of Serial Interface Channel 0 ............................................................ 211

13.4 Operations of Serial Interface Channel 0 ........................................................................ 217

13.4.1 Operation stop mode .............................................................................................................. 217

13.4.2 3-wire serial I/O mode operation ............................................................................................ 218

13.4.3 SBI mode operation ................................................................................................................ 223

13.4.4 2-wire serial I/O mode operation ............................................................................................ 249

13.4.5 SCK0/P27 pin output manipulation ........................................................................................ 255

CHAPTER 14 SERIAL INTERFACE CHANNEL 1 ............................................................................... 256

14.1 Functions of Serial Interface Channel 1.......................................................................... 256

14.2 Configuration of Serial Interface Channel 1 ................................................................... 257

14.3 Control Registers of Serial Interface Channel 1 ............................................................ 260

14.4 Operations of Serial Interface Channel 1 ........................................................................ 268

14.4.1 Operation stop mode .............................................................................................................. 268

14.4.2 3-wire serial I/O mode operation ............................................................................................ 269

14.4.3 3-wire serial I/O mode operation with automatic transmit/receive function ......................... 272

CHAPTER 15 VFD CONTROLLER/DRIVER ........................................................................................ 299

15.1 VFD Controller/Driver Functions ...................................................................................... 299

15.2 VFD Controller/Driver Configuration ............................................................................... 301

15.3 VFD Controller/Driver Control Registers ........................................................................ 303

15.3.1 Control registers ...................................................................................................................... 303

15.3.2 One-display period and cut width ........................................................................................... 310

15.4 Selecting Display Mode ..................................................................................................... 311

15.5 Display Mode and Display Output.................................................................................... 312

15.6 Display Data Memory ......................................................................................................... 313

User’s Manual U11302EJ4V0UM

15.7 Key Scan Flag and Key Scan Data .................................................................................. 314

15.7.1 Key scan flag ........................................................................................................................... 314

15.7.2 Key scan data .......................................................................................................................... 314

15.8 Light Leakage of VFD ......................................................................................................... 315

15.9 Display Examples ............................................................................................................... 317

15.9.1 Segment type (display mode 1: DSPM05 = 0) ...................................................................... 318

15.9.2 Dot type (display mode 1: DSPM05 = 0) ............................................................................... 320

15.9.3 Display type in which a segment spans two or more grids

(display mode 2: DSPM05 = 1) .............................................................................................. 322

15.10 Calculating Total Power Dissipation............................................................................... 326

15.10.1 Segment type (display mode 1: DSPM05 = 0) ...................................................................... 326

15.10.2 Dot type (display mode 1: DSPM05 = 0) ............................................................................... 329

15.10.3 Display type in which a segment spans two or more grids

(display mode 2: DSPM05 = 1) .............................................................................................. 332

CHAPTER 16 INTERRUPT AND TEST FUNCTIONS .......................................................................... 335

16.1 Interrupt Function Types ................................................................................................... 335

16.2 Interrupt Sources and Configuration ............................................................................... 336

16.3 Interrupt Function Control Registers .............................................................................. 339

16.4 Interrupt Servicing Operations ......................................................................................... 347

16.4.1 Non-maskable interrupt request acknowledgment operation ................................................ 347

16.4.2 Maskable interrupt request acknowledgment operation ........................................................ 350

16.4.3 Software interrupt request acknowledgment operation ......................................................... 352

16.4.4 Multiple interrupt servicing ...................................................................................................... 353

16.4.5 Interrupt request hold .............................................................................................................. 356

16.5 Test Functions .................................................................................................................... 357

16.5.1 Test function control registers ................................................................................................ 357

16.5.2 Test input signal acknowledgment operation ........................................................................ 358

CHAPTER 17 STANDBY FUNCTION ................................................................................................... 359

17.1 Standby Function and Configuration .............................................................................. 359

17.1.1 Standby function ...................................................................................................................... 359

17.1.2 Standby function control register ............................................................................................ 360

17.2 Standby Function Operations ........................................................................................... 361

17.2.1 HALT mode ............................................................................................................................. 361

17.2.2 STOP mode ............................................................................................................................. 364

CHAPTER 18 RESET FUNCTION ........................................................................................................ 367

18.1 Reset Function .................................................................................................................... 367

CHAPTER 19 µPD78P0208 .................................................................................................................. 371

19.1 Internal Memory Size Switching Register ....................................................................... 372

19.2 Internal Expansion RAM Size Switching Register ......................................................... 374

19.3 PROM Programming ........................................................................................................... 375

19.3.1 Operating modes ..................................................................................................................... 375

19.3.2 PROM write procedure ........................................................................................................... 377

19.3.3 PROM read procedure ............................................................................................................ 381

19.4 Screening of One-Time PROM Version ........................................................................... 382

User’s Manual U11302EJ4V0UM

CHAPTER 20 INSTRUCTION SET ....................................................................................................... 383

20.1 Conventions ........................................................................................................................ 384

20.1.1 Operand identifiers and description methods ........................................................................ 384

20.1.2 Description of “operation” column .......................................................................................... 385

20.1.3 Description of “flag operation” column ................................................................................... 385

20.2 Operation List...................................................................................................................... 386

20.3 Instructions Listed by Addressing Type ......................................................................... 394

APPENDIX A DIFFERENCES BETWEEN µPD78044H, 780228, AND 780208 SUBSERIES ............ 398

APPENDIX B DEVELOPMENT TOOLS .............................................................................................. 399

B.1 Software Package ............................................................................................................... 401

B.2 Language Processing Software ........................................................................................ 401

B.3 Control Software ................................................................................................................. 402

B.4 PROM Programming Tools ................................................................................................ 403

B.4.1 Hardware ................................................................................................................................. 403

B.4.2 Software................................................................................................................................... 403

B.5 Debugging Tools (Hardware) ............................................................................................ 404

B.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A ................................................ 404

B.5.2 When using in-circuit emulator IE-78001-R-A ....................................................................... 405

B.6 Debugging Tools (Software) ............................................................................................. 406

B.7 Embedded Software ........................................................................................................... 407

B.8 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to

IE-78001-R-A ........................................................................................................................ 408

B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended

Footprint............................................................................................................................... 409

B.10 Notes on Target System Design ....................................................................................... 411

APPENDIX C REGISTER INDEX ......................................................................................................... 413

C.1 Register Index (by Register Name) .................................................................................. 413

C.2 Register Index (by Register Symbol) ............................................................................... 415

APPENDIX D REVISION HISTORY ....................................................................................................... 417

User’s Manual U11302EJ4V0UM

LIST OF FIGURES (1/6)

Figure No. Title Page

2-1 Pin I/O Circuits ................................................................................................................................45

3-1 Memory Map (

PD780204 and µPD780204A) .............................................................................. 48

3-2 Memory Map (

PD780205 and µPD780205A) .............................................................................. 49

3-3 Memory Map (

PD780206)............................................................................................................. 50

3-4 Memory Map (

PD780208)............................................................................................................. 51

3-5 Memory Map (

PD78P0208) .......................................................................................................... 52

3-6 Data Memory Addressing (

PD780204 and µPD780204A) .......................................................... 55

3-7 Data Memory Addressing (

PD780205 and µPD780205A) .......................................................... 56

3-8 Data Memory Addressing (

PD780206) ........................................................................................ 57

3-9 Data Memory Addressing (

PD780208) ........................................................................................ 58

3-10 Data Memory Addressing (µPD78P0208) ...................................................................................... 59

3-11 Program Counter Format ................................................................................................................ 60

3-12 Program Status Word Format ......................................................................................................... 60

3-13 Stack Pointer Format ...................................................................................................................... 61

3-14 Data to Be Saved to Stack Memory ............................................................................................... 62

3-15 Data to Be Reset from Stack Memory ........................................................................................... 62

3-16 General-Purpose Register Configuration ....................................................................................... 63

4-1 Port Types ....................................................................................................................................... 80

4-2 Block Diagram of P00 and P04 ...................................................................................................... 84

4-3 Block Diagram of P01 to P03 ......................................................................................................... 84

4-4 Block Diagram of P10 to P17 ......................................................................................................... 85

4-5 Block Diagram of P20, P21, P23 to P26 ........................................................................................ 86

4-6 Block Diagram of P22 and P27 ...................................................................................................... 87

4-7 Block Diagram of P30 to P37 ......................................................................................................... 88

4-8 Block Diagram of P70 to P74 ......................................................................................................... 89

4-9 Block Diagram of P80 to P87 ......................................................................................................... 90

4-10 Block Diagram of P90 to P97 ......................................................................................................... 91

4-11 Block Diagram of P100 to P107 ..................................................................................................... 92

4-12 Block Diagram of P110 to P117 ..................................................................................................... 93

4-13 Block Diagram of P120 to P127 ..................................................................................................... 94

4-14 Format of Port Mode Register ........................................................................................................ 96

4-15 Format of Pull-up Resistor Option Register ................................................................................... 97

5-1 Clock Generater Block Diagram ..................................................................................................... 101

5-2 Feedback Resistor of Subsystem Clock ........................................................................................ 102

5-3 Format of Processor Clock Control Register ................................................................................. 103

5-4 Format of Display Mode Register 0 ............................................................................................... 105

5-5 Format of Display Mode Register 1 ............................................................................................... 108

5-6 External Circuit of Main System Clock Oscillator .......................................................................... 109

5-7 External Circuit of Subsystem Clock Oscillator ............................................................................. 110

5-8 Examples of Incorrect Resonator Connection ............................................................................... 111

5-9 Main System Clock Stop Function ................................................................................................. 115

5-10 System Clock and CPU Clock Switching ....................................................................................... 118

User’s Manual U11302EJ4V0UM

LIST OF FIGURES (2/6)

Figure No. Title Page

6-1 Block Diagram of 16-Bit Timer/Event Counter (Timer Mode) ....................................................... 123

6-2 Block Diagram of 16-Bit Timer/Event Counter (PWM Mode) ........................................................ 124

6-3 Block Diagram of 16-Bit Timer/Event Counter Output Controller ................................................. 125

6-4 Format of Timer Clock Select Register 0 ....................................................................................... 128

6-5 Format of 16-Bit Timer Mode Control Register ............................................................................. 130

6-6 Format of 16-Bit Timer Output Control Register ........................................................................... 131

6-7 Format of Port Mode Register 3 ..................................................................................................... 132

6-8 Format of External Interrupt Mode Register .................................................................................. 133

6-9 Format of Sampling Clock Select Register .................................................................................... 134

6-10 Interval Timer Configuration Diagram ............................................................................................ 135

6-11 Interval Timer Operation Timing ..................................................................................................... 136

6-12 Example of D/A Converter Configuration with PWM Output......................................................... 137

6-13 TV Tuner Application Circuit Example ........................................................................................... 138

6-14 Configuration Diagram for Pulse Width Measurement in Free-Running Mode............................ 139

6-15 Timing of Pulse Width Measurement Operation in Free-Running Mode

(with Both Edges Specified) ........................................................................................................... 139

6-16 Timing of Pulse Width Measurement Operation by Means of Restart

(with Both Edges Specified) ........................................................................................................... 140

6-17 External Event Counter Configuration Diagram ............................................................................ 141

6-18 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 141

6-19 Square-Wave Output Operation Timing ......................................................................................... 142

6-20 16-Bit Timer Register Start Timing ................................................................................................. 143

6-21 Timing After Compare Register Change During Timer Count Operation..................................... 143

6-22 Capture Register Data Retention Timing ....................................................................................... 144

7-1 Block Diagram of 8-Bit Timer/Event Counter ................................................................................. 151

7-2 Block Diagram of 8-Bit Timer/Event Counter Output Controller 1 ................................................ 152

7-3 Block Diagram of 8-Bit Timer/Event Counter Output Controller 2 ................................................ 152

7-4 Format of Timer Clock Select Register 1 ....................................................................................... 154

7-5 Format of 8-Bit Timer Mode Control Register ............................................................................... 155

7-6 Format of 8-Bit Timer Output Control Register .............................................................................. 156

7-7 Format of Port Mode Register 3 ..................................................................................................... 157

7-8 Interval Timer Operation Timing ..................................................................................................... 158

7-9 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 160

7-10 Square-Wave Output Operation Timing ......................................................................................... 161

7-11 Interval Timer Operation Timing ..................................................................................................... 162

7-12 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 164

7-13 Square-Wave Output Operation Timing ......................................................................................... 165

7-14 8-Bit Timer Register Start Timing ................................................................................................... 166

7-15 External Event Counter Operation Timing ..................................................................................... 166

7-16 Timing After Compare Register Change During Timer Count Operation..................................... 167

User’s Manual U11302EJ4V0UM

LIST OF FIGURES (3/6)

Figure No. Title Page

8-1 Watch Timer Block Diagram ........................................................................................................... 170

8-2 Format of Timer Clock Select Register 2 ....................................................................................... 171

8-3 Format of Watch Timer Mode Control Register ............................................................................. 172

9-1 Watchdog Timer Block Diagram ..................................................................................................... 176

9-2 Format of Timer Clock Select Register 2 ....................................................................................... 178

9-3 Format of Watchdog Timer Mode Register .................................................................................... 179

10-1 Remote Controlled Output Application Example ........................................................................... 182

10-2 Clock Output Controller Block Diagram ......................................................................................... 183

10-3 Format of Timer Clock Select Register 0....................................................................................... 184

10-4 Format of Port Mode Register 3 ..................................................................................................... 185

11-1 Buzzer Output Controller Block Diagram ....................................................................................... 186

11-2 Format of Timer Clock Select Register 2....................................................................................... 188

11-3 Format of Port Mode Register 3 ..................................................................................................... 189

12-1 A/D Converter Block Diagram ........................................................................................................ 191

12-2 Format of A/D Converter Mode Register ....................................................................................... 195

12-3 Format of A/D Converter Input Select Register ............................................................................. 196

12-4 Basic Operation of A/D Converter .................................................................................................. 198

12-5 Relationship Between Analog Input Voltage and A/D Conversion Result ................................... 199

12-6 A/D Conversion by Hardware Start ................................................................................................ 200

12-7 A/D Conversion by Software Start ................................................................................................. 201

12-8 Example of Method of Reducing Power Consumption in Standby Mode .................................... 202

12-9 Analog Input Pin Processing .......................................................................................................... 203

12-10 A/D Conversion End Interrupt Request Generation Timing .......................................................... 204

12-11 AV

DD Pin Connection....................................................................................................................... 204

13-1 Block Diagram of Serial Interface Channel 0 ................................................................................ 208

13-2 Format of Timer Clock Select Register 3....................................................................................... 212

13-3 Format of Serial Operating Mode Register 0 ................................................................................. 213

13-4 Format of Serial Bus Interface Control Register ........................................................................... 214

13-5 Format of Interrupt Timing Specification Register ......................................................................... 216

13-6 3-Wire Serial I/O Mode Timing ....................................................................................................... 221

13-7 RELT and CMDT Operations .......................................................................................................... 222

13-8 Circuit for Switching Transfer Bit Order ......................................................................................... 222

13-9 Example of Serial Bus Configuration with SBI .............................................................................. 224

13-10 SBI Transfer Timing ........................................................................................................................ 226

13-11 Bus Release Signal ......................................................................................................................... 227

13-12 Command Signal ............................................................................................................................. 227

13-13 Address ............................................................................................................................................ 228

13-14 Slave Selection by Address ............................................................................................................ 228

13-15 Commands ....................................................................................................................................... 229

User’s Manual U11302EJ4V0UM

LIST OF FIGURES (4/6)

Figure No. Title Page

13-16 Data .................................................................................................................................................. 229

13-17 Acknowledge Signal ........................................................................................................................ 230

13-18 BUSY and READY Signals ............................................................................................................. 231

13-19 RELT, CMDT, RELD, and CMDD Operations (Master) ................................................................ 236

13-20 RELD and CMDD Operations (Slave) ............................................................................................ 236

13-21 ACKT Operation .............................................................................................................................. 237

13-22 ACKE Operations ............................................................................................................................ 238

13-23 ACKD Operations ............................................................................................................................ 239

13-24 BSYE Operation .............................................................................................................................. 239

13-25 Pin Configuration ............................................................................................................................. 242

13-26 Address Transmission from Master Device to Slave Device (WUP = 1) ..................................... 244

13-27 Command Transmission from Master Device to Slave Device .................................................... 245

13-28 Data Transmission from Master Device to Slave Device.............................................................. 246

13-29 Data Transmission from Slave Device to Master Device.............................................................. 247

13-30 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode................................................ 249

13-31 2-Wire Serial I/O Mode Timing ....................................................................................................... 253

13-32 RELT and CMDT Operations .......................................................................................................... 254

13-33 SCK0/P27 Pin Configuration .......................................................................................................... 255

14-1 Block Diagram of Serial Interface Channel 1 ................................................................................ 258

14-2 Format of Timer Clock Select Register 3....................................................................................... 261

14-3 Format of Serial Operating Mode Register 1 ................................................................................. 262

14-4 Format of Automatic Data Transmit/Receive Control Register ..................................................... 264

14-5 Format of Automatic Data Transmit/Receive Interval Specification Register .............................. 265

14-6 3-Wire Serial I/O Mode Timing ....................................................................................................... 270

14-7 Circuit for Switching Transfer Bit Order ......................................................................................... 271

14-8 Basic Transmission/Reception Mode Operation Timing ............................................................... 279

14-9 Basic Transmission/Reception Mode Flowchart ............................................................................ 280

14-10 Buffer RAM Operation in 6-Byte Transmission/Reception

(in Basic Transmission/Reception Mode)....................................................................................... 281

14-11 Basic Transmission Mode Operation Timing ................................................................................. 283

14-12 Basic Transmission Mode Flowchart.............................................................................................. 284

14-13 Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode) ........................... 285

14-14 Repeat Transmission Mode Operation Timing .............................................................................. 287

14-15 Repeat Transmission Mode Flowchart ........................................................................................... 288

14-16 Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) ........................ 289

14-17 Automatic Transmission/Reception Suspension and Restart ....................................................... 291

14-18 System Configuration with Busy Control Option ........................................................................... 292

14-19 Operation Timing When Using Busy Control Option (BUSY0 = 0) .............................................. 293

14-20 Busy Signal and Clearing Wait (BUSY0 = 0) ................................................................................ 293

14-21 Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0) ............................... 294

14-22 Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1) ............. 295

14-23 Automatic Transmit/Receive Interval .............................................................................................. 296

14-24 Operation Timing When Automatic Transmit/Receive Function Is Operating with

Internal Clock................................................................................................................................... 297

User’s Manual U11302EJ4V0UM

LIST OF FIGURES (5/6)

Figure No. Title Page

15-1 VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0) ........................................... 300

15-2 VFD Controller/Driver Block Diagram ............................................................................................ 302

15-3 Format of Display Mode Register 0 ............................................................................................... 305

15-4 Format of Display Mode Register 1 ............................................................................................... 307

15-5 Format of Display Mode Register 2 ............................................................................................... 308

15-6 Cut Width of Segment/Digit Signal ................................................................................................. 310

15-7 VFD Controller Display Start Timing .............................................................................................. 310

15-8 Selection of Display Mode .............................................................................................................. 311

15-9 Pin Configuration for 14-Segment Display ..................................................................................... 312

15-10 Relationship Between Display Data Memory Contents and Segment Output ............................. 313

15-11 Light Leakage due to Short Blanking Time.................................................................................... 315

15-12 Light Leakage due to C

SG ............................................................................................................... 316

15-13 Waveform of Light Leakage due to CSG ......................................................................................... 316

15-14 Display Data Memory Configuration and Segment Data Reading Order

(Segment Type) ............................................................................................................................... 318

15-15 Relationship Between Display Data Memory Contents and Segment Outputs

in 10-Segment x 11-Digit Display Mode ........................................................................................ 319

15-16 Display Data Memory Configuration and Segment Data Reading Order (Dot Type) .................. 320

15-17 Relationship Between Display Data Memory Contents and Segment Outputs

in 35-Segment x 16-Digit Display Mode ........................................................................................ 321

15-18 Display Data Memory Configuration and Data Reading Order (Display Mode 2) ....................... 322

15-19 Segment Connection Example ....................................................................................................... 323

15-20 Grid Driving Timing ......................................................................................................................... 324

15-21 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 325

15-22 Allowable Total Power Dissipation P

T (TA = –40 to +85°C) .......................................................... 326

15-23 Relationship Between Display Data Memory Contents and Segment Outputs

in 10-Segment x 11-Digit Display Mode ........................................................................................ 328

15-24 Relationship Between Display Data Memory Contents and Segment Outputs

in 35-Segment x 16-Digit Display Mode ........................................................................................ 331

15-25 Grid Driving Timing ......................................................................................................................... 333

15-26 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 334

16-1 Basic Configuration of Interrupt Function ...................................................................................... 337

16-2 Format of Interrupt Request Flag Register .................................................................................... 340

16-3 Format of Interrupt Mask Flag Register ......................................................................................... 341

16-4 Format of Priority Specification Flag Register ............................................................................... 342

16-5 Format of External Interrupt Mode Register .................................................................................. 343

16-6 Format of Sampling Clock Select Register .................................................................................... 344

16-7 Noise Eliminator I/O Timing (When Rising Edge Is Detected) ..................................................... 345

16-8 Format of Program Status Word .................................................................................................... 346

16-9 Non-Maskable Interrupt Request Acknowledgment Flowchart ..................................................... 348

16-10 Non-Maskable Interrupt Request Acknowledgment Timing .......................................................... 348

16-11 Non-Maskable Interrupt Request Acknowledgment Operation ..................................................... 349

User’s Manual U11302EJ4V0UM

LIST OF FIGURES (6/6)

Figure No. Title Page

16-12 Interrupt Request Acknowledge Processing Algorithm ................................................................. 351

16-13 Interrupt Request Acknowledgment Timing (Minimum Time) ....................................................... 352

16-14 Interrupt Request Acknowledgment Timing (Maximum Time) ...................................................... 352

16-15 Multiple Interrupt Servicing Example .............................................................................................. 354

16-16 Interrupt Request Hold .................................................................................................................... 356

16-17 Basic Configuration of Test Function ............................................................................................. 357

16-18 Format of Interrupt Request Flag Register 0H .............................................................................. 358

16-19 Format of Interrupt Mask Flag Register 0H ................................................................................... 358

17-1 Format of Oscillation Stabilization Time Select Register .............................................................. 360

17-2 HALT Mode Release by Interrupt Request Generation ................................................................ 362

17-3 HALT Mode Release by RESET Input ........................................................................................... 363

17-4 STOP Mode Release by Interrupt Request Generation ................................................................ 365

17-5 STOP Mode Release by RESET Input .......................................................................................... 366

18-1 Block Diagram of Reset Function ................................................................................................... 367

18-2 Timing of Reset by RESET Input ................................................................................................... 368

18-3 Timing of Reset due to Watchdog Timer Overflow ....................................................................... 368

18-4 Timing of Reset by RESET Input in STOP Mode.......................................................................... 368

19-1 Format of Internal Memory Size Switching Register (IMS) ........................................................... 373

19-2 Format of Internal Expansion RAM Size Switching Register........................................................ 374

19-3 Page Program Mode Flowchart ...................................................................................................... 377

19-4 Page Program Mode Timing ........................................................................................................... 378

19-5 Byte Program Mode Flowchart ....................................................................................................... 379

19-6 Byte Program Mode Timing ............................................................................................................ 380

19-7 PROM Read Timing ........................................................................................................................ 381

B-1 Configuration of Development Tools .............................................................................................. 400

B-2 EV-9200GF-100 Package Drawing (for Reference Purposes only) ............................................. 409

B-3 Recommended Footprint for EV-9200GF-100 (for Reference Purposes only) ............................ 410

B-4 Distance Between IE System and Conversion Adapter ................................................................ 411

B-5 Connection Conditions of Target System (When NP-100GF-TQ Is Used) .................................. 412

B-6 Connection Conditions of Target System (When NP-H100GF-TQ Is Used) ............................... 412

User’s Manual U11302EJ4V0UM

LIST OF TABLES (1/2)

Table No. Title Page

1-1 Mask Options in Mask ROM Versions ........................................................................................... 33

2-1 Types of Pin I/O Circuits ................................................................................................................. 43

3-1 Internal ROM Capacity .................................................................................................................... 53

3-2 Vector Table .................................................................................................................................... 53

3-3 Special-Function Register List ........................................................................................................ 65

4-1 Port Functions ................................................................................................................................. 81

4-2 Port Configuration ........................................................................................................................... 83

4-3 Port Mode Register and Output Latch Setting When Alternate Function Is Used ...................... 95

4-4 Comparison Between Mask Option of Mask ROM Version and

PD78P0208............................ 99

5-1 Clock Generator Configuration ....................................................................................................... 100

5-2 Relationship Between CPU Clock and Minimum Instruction Execution Time ............................. 104

5-3 Maximum Time Required for CPU Clock Switchover .................................................................... 117

6-1 Timer/Event Counter Operations .................................................................................................... 120

6-2 16-Bit Timer/Event Counter Interval Time ..................................................................................... 121

6-3 16-Bit Timer/Event Counter Square-Wave Output Ranges .......................................................... 121

6-4 16-Bit Timer/Event Counter Configuration ..................................................................................... 122

6-5 16-Bit Timer/Event Counter Interval Time ..................................................................................... 136

6-6 16-Bit Timer/Event Counter Square-Wave Output Ranges .......................................................... 142

7-1 8-Bit Timer/Event Counter Interval Time ........................................................................................ 146

7-2 8-Bit Timer/Event Counter Square-Wave Output Ranges ............................................................ 147

7-3 Interval Time When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter ........... 148

7-4 Square-Wave Output Ranges When 8-Bit Timer/Event Counter

Is Used as 16-Bit Timer/Event Counter ......................................................................................... 149

7-5 8-Bit Timer/Event Counter Configuration ....................................................................................... 150

7-6 8-Bit Timer/Event Counter 1 Interval Time .................................................................................... 159

7-7 8-Bit Timer/Event Counter 2 Interval Time .................................................................................... 159

7-8 8-Bit Timer/Event Counter Square-Wave Output Ranges ............................................................ 161

7-9 Interval Time When 2-Channel 8-Bit Timer/Event Counter

(TM1 and TM2) Is Used as 16-Bit Timer/Event Counter .............................................................. 163

7-10 Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters

(TM1 and TM2) Are Used as 16-Bit Timer/Event Counter ........................................................... 165

8-1 Interval Timer Interval Time ............................................................................................................ 168

8-2 Watch Timer Configuration ............................................................................................................. 169

8-3 Interval Timer Interval Time ............................................................................................................ 173

9-1 Watchdog Timer Program Loop Detection Time ........................................................................... 174

9-2 Interval Time .................................................................................................................................... 174

9-3 Watchdog Timer Configuration ....................................................................................................... 175

9-4 Watchdog Timer Program Loop Detection Time ........................................................................... 180

User’s Manual U11302EJ4V0UM

LIST OF TABLES (2/2)

Table No. Title Page

9-5 Interval Timer Interval Time ............................................................................................................ 181

10-1 Clock Output Controller Configuration ........................................................................................... 183

11-1 Buzzer Output Controller Configuration ......................................................................................... 186

12-1 A/D Converter Configuration ........................................................................................................... 190

13-1 Differences Between Channels 0 and 1......................................................................................... 205

13-2 Modes of Serial Interface Channel 0.............................................................................................. 206

13-3 Configuration of Serial Interface Channel 0................................................................................... 207

13-4 Signals in SBI Mode ........................................................................................................................ 240

14-1 Modes of Serial Interface Channel 1.............................................................................................. 256

14-2 Configuration of Serial Interface Channel 1................................................................................... 257

14-3 Interval Determined by CPU Processing (with Internal Clock Operation) .................................... 297

14-4 Interval Determined by CPU Processing (with External Clock Operation) .................................. 298

15-1 Relationship Between Display Output Pins and Port Pins ............................................................ 301

15-2 VFD Controller/Driver Configuration ............................................................................................... 301

15-3 Segment Lighting Timing ................................................................................................................ 324

16-1 Interrupt Source List ........................................................................................................................ 336

16-2 Various Flags Corresponding to Interrupt Request Sources ........................................................ 339

16-3 Times from Maskable Interrupt Request Generation to Interrupt Servicing................................. 350

16-4 Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing ................................ 353

17-1 HALT Mode Operating Status......................................................................................................... 361

17-2 Operation After HALT Mode Release ............................................................................................ 363

17-3 STOP Mode Operating Status ........................................................................................................ 364

17-4 Operation After STOP Mode Release ............................................................................................ 366

18-1 Hardware Status After Reset .......................................................................................................... 369

19-1 Differences Between

PD78P0208 and Mask ROM Versions ..................................................... 371

19-2 Internal Memory Size Switching Register Setting Values ............................................................. 373

19-3 Internal Expansion RAM Size Switching Register Setting Values................................................ 374

19-4 PROM Programming Operating Modes ......................................................................................... 375

20-1 Operand Identifiers and Description Methods ............................................................................... 384

A-1 Major Differences Between µPD78044H, 780228, and 780208 Subseries ................................. 398

B-1 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A ....... 408

B-2 Distance Between IE System and Conversion Adapter ................................................................ 411

User’s Manual U11302EJ4V0UM

CHAPTER 1 OUTLINE

1.1 Features

Internal high-capacity ROM and RAM

Item Program Memory Data Memory

Part

ROM PROM Internal High- Buffer RAM VFD Display Internal

Number Speed RAM RAM

Expansion RAM

PD780204 32 KB — 1024 bytes 64 bytes 80 bytes None

PD780204A

PD780205 40 KB —

PD780205A

PD780206 48 KB — 1024 bytes

PD780208 60 KB —

PD78P0208 — 60 KB

Note 1

1024 bytes

Note 2

Notes 1. 32, 40, 48, or 60 KB can be selected by setting the internal memory size switching register (IMS).

2. 0 or 1024 bytes can be selected by setting the internal expansion RAM size switching register (IXS).

Minimum instruction execution time can be changed from high speed (0.4 µs: @ 5.0 MHz operation with main

system clock) to ultra-low speed (122 µs: @ 32.768 kHz operation with subsystem clock)

74 I/O ports VFD controller/driver: 53 display outputs in total

• Segments: 9 to 40

• Digits: 2 to 16 8-bit resolution A/D converter: 8 channels

• Power supply voltage (AVDD = 4.0 to 5.5 V)

Serial interface: 2 channels

• 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel

• 3-wire serial I/O mode (automatic transmit/receive function): 1 channel

Timer: 5 channels

• 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

15 vectored interrupt sources

One test input Two types of on-chip clock oscillators (for main and subsystem clocks)

Power supply voltage: VDD = 2.7 to 5.5 V

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

1.2 Applications

Compact home stereo sets, cassette decks, tuners, CD players, VCRs, etc.

1.3 Ordering Information

Part Number Package Internal ROM

PD780204GF-xxx-3BA 100-pin plastic QFP (14 x 20) Mask ROM

PD780204AGF-xxx-3BA 100-pin plastic QFP (14 x 20) Mask ROM

PD780205GF-xxx-3BA 100-pin plastic QFP (14 x 20) Mask ROM

PD780205AGF-xxx-3BA 100-pin plastic QFP (14 x 20) Mask ROM

PD780206GF-xxx-3BA 100-pin plastic QFP (14 x 20) Mask ROM

PD780208GF-xxx-3BA 100-pin plastic QFP (14 x 20) Mask ROM

PD78P0208GF-3BA 100-pin plastic QFP (14 x 20) One-time PROM

Remark xxx indicates ROM code suffix.

1.4 Quality Grade

Part Number Package Quality Grade

PD780204GF-xxx-3BA 100-pin plastic QFP (14 x 20) Standard

PD780204AGF-xxx-3BA 100-pin plastic QFP (14 x 20) Standard

PD780205GF-xxx-3BA 100-pin plastic QFP (14 x 20) Standard

PD780205AGF-xxx-3BA 100-pin plastic QFP (14 x 20) Standard

PD780206GF-xxx-3BA 100-pin plastic QFP (14 x 20) Standard

PD780208GF-xxx-3BA 100-pin plastic QFP (14 x 20) Standard

PD78P0208GF-3BA 100-pin plastic QFP (14 x 20) Standard

Remark xxx indicates ROM code suffix.

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

1.5 Pin Configuration (Top View)

(1) Normal operating mode

• 100-pin plastic QFP (14 x 20)

PD780204GF-xxx-3BA, 780204AGF-xxx-3BA, 780205GF-xxx-3BA, 780205AGF-xxx-3BA,

PD780206GF-xxx-3BA, 780208GF-xxx-3BA, 78P0208GF-3BA

Cautions 1. Connect the IC (Internally Connected) pin directly to V

SS.

2. Connect the AVDD pin to VDD.

3. Connect the AVSS pin to VSS.

Remark The pin connection in parentheses is intended for the

PD78P0208.

FIP0

FIP1

FIP2

FIP3

FIP4

FIP5

FIP6

FIP7

FIP8

FIP9

FIP10

FIP11

FIP12

P80/FIP13

P81/FIP14

P82/FIP15

P83/FIP16

P84/FIP17

P85/FIP18

P86/FIP19

100

99989796959493929190898887868584838281

P37 P36/BUZ P35/PCL

P34/TI2

P33/TI1 P32/TO2 P31/TO1 P30/TO0

RESET

X2 X1

IC (V

)

XT2

P04/XT1

P27/SCK0

P26/SO0/SB1

P25/SI0/SB0

P24/BUSY

P23/STB

P22/SCK1

P21/SO1

P20/SI1

P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P87/FIP20 V

LOAD

P90/FIP21 P91/FIP22 P92/FIP23 P93/FIP24 P94/FIP25 P95/FIP26 P96/FIP27 P97/FIP28 P100/FIP29 P101/FIP30 P102/FIP31 P103/FIP32 P104/FIP33 P105/FIP34 P106/FIP35 P107/FIP36 P110/FIP37 P111/FIP38 P112/FIP39 P113/FIP40 P114/FIP41 P115/FIP42 P116/FIP43 P117/FIP44 P120/FIP45 P121/FIP46 P122/FIP47 P123/FIP48

31323334353637383940414243444546474849

P12/ANI2

P11/ANI1

P10/ANI0

REF

P03/INTP3

P02/INTP2

P01/INTP1

P00/INTP0/TI0

P74

P73

P72

P71

P70

P127/FIP52

P126/FIP51

P125/FIP50

P124/FIP49

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

P110 to P117: Port 11

P120 to P127: Port 12 PCL: Programmable clock

RESET: Reset

SB0, SB1: Serial bus SCK0, SCK1: Serial clock

SI0, SI1: Serial input

SO0, SO1: Serial output STB: Strobe

TI0 to TI2: Timer input

TO0 to TO2: Timer output V

DD: Power supply

LOAD: Negative power supply

VPP: Programming power supply V

SS: Ground

X1, X2: Crystal (main system clock)

XT1, XT2: Crystal (subsystem clock)

ANI0 to ANI7: Analog input

DD: Analog power supply

REF: Analog reference voltage

SS: Analog ground

BUSY: Busy BUZ: Buzzer clock

FIP0 to FIP52: Fluorescent indicator panel

IC: Internally connected INTP0 to INTP3: External interrupt input

P00 to P04: Port 0

P10 to P17: Port 1 P20 to P27: Port 2

P30 to P37: Port 3

P70 to P74: Port 7 P80 to P87: Port 8

P90 to P97: Port 9

P100 to P107: Port 10

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

(2) PROM programming mode

• 100-pin plastic QFP (14 x 20)

PD78P0208GF-3BA

Cautions 1. (L): Connect independently to V

SS via a pull-down resistor.

2. (D): Connect via a driver.

3. V

SS: Connect to ground.

4. RESET: Set to low level.

5. Open: Do not connect to anything.

A0 to A16: Address bus OE: Output enable V

DD: Power supply

CE: Chip enable PGM: Program VPP: Programming power supply D0 to D7: Data bus RESET: Reset V

SS: Ground

D7 D6 D5 D4 D3 D2 D1 D0

RESET

Open

(L)

Open

(L)

A7 A6 A5 A4 A3 A2 A1 A0

(L)

(D)

(L)

(D)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

(L) V

A8 A16 A10 A11 A12 A13 A14 A15

(L)

(D)

100

99989796959493929190898887868584838281

31323334353637383940414243444546474849

(L)

(D) PGM

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

1.6 78K/0 Series Lineup

The 78K/0 Series product lineup is illustrated below. The part numbers in boxes indicate subseries names.

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP

(Fluorescent Indicator Panel) in some

documents, but the functions of the two are the same.

PD78083

PD78018F

PD78018FY

PD78014H

EMI-noise reduced version of the PD78018F

Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)

µ µ µ

42/44-pin

64-pin

52-pin

52-pin version of the PD780024A

PD780024AS

52-pin

52-pin version of the PD780034A

PD780034AS

PD78054 with IEBusTM controller

PD78054 with enhanced serial I/O

PD78078Y with enhanced serial I/O and limited functions

PD78054 with timer and enhanced external interface

64-pin

80-pin

EMI-noise reduced version of the PD78054

PD78018F with UART and D/A converter, and enhanced I/O

PD780034A

PD780988

PD780034AY

64-pin

PD780024A with expanded RAM

PD780024A with enhanced A/D converter

On-chip inverter controller and UART. EMI-noise reduced.

PD78064

PD78064B

PD780308

100-pin

PD780308Y

PD78064Y

80-pin

78K/0 Series

LCD drive

PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064

Basic subseries for driving LCDs, on-chip UART

Bus interface supported

PD78018F with enhanced serial I/O

80-pin

100-pin

Products in mass production

Products under development

Y subseries products are compatible with I

C bus.

ROMless version of the PD78078

100-pin

EMI-noise reduced version of the PD78078

Inverter control

PD780208100-pin

VFD drive

PD78044F with enhanced I/O and VFD C/D. Display output total: 53

PD78098B

100-pin

PD780024A

PD780024AY

80-pin

PD780852

PD780828B

For automobile meter driver. On-chip CAN controller

100-pin

PD780958

For industrial meter control

On-chip automobile meter controller/driver

Meter control

80-pin

On-chip IEBus controller

80-pin

On-chip controller compliant with J1850 (Class 2)

PD780833Y

PD780948

On-chip CAN controller

64-pin

PD780078

PD780078Y

PD780034A with timer and enhanced serial I/O

PD78054

PD78054Y

PD78058F

PD78058FY

µ µ

PD780058

PD780058Y

PD78070A

PD78070AY

PD78078 PD78078Y

PD780018AY

µ µ

Control

PD78075B

PD780065

PD78044H

PD780232

80-pin

For panel control. On-chip VFD C/D. Display output total: 53

PD78044F with N-ch open-drain I/O. Display output total: 34

PD78044F

80-pin

Basic subseries for driving VFD. Display output total: 34

120-pin

PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.

PD780318

PD780328

120-pin

PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.

µ µ

PD780338

PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.

µ µ

On-chip CAN controller

Specialized for CAN controller function

80-pin

PD780703AY

PD780702Y

64-pin

PD780816

PD780344 with enhanced A/D converter

100-pin

PD780344

PD780344Y

PD780354 PD780354Y

µ µ

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

The following lists the main functional differences between subseries products.

• Non-Y subseries

Function ROM Timer 8-Bit 10-Bit 8-Bit Serial Interface I/O

External

Subseries Name

8-Bit 16-Bit Watch WDT A/D A/D D/A

Expansion

Control PD78075B

32 K to 40 K

4 ch 1 ch 1 ch 1 ch 8 ch – 2 ch 3 ch (UART: 1 ch) 88 1.8 V

PD78078

48 K to 60 K

PD78070A – 61 2.7 V

PD780058

24 K to 60 K

2 ch

3 ch (time-division UART: 1 ch)

68 1.8 V

PD78058F

48 K to 60 K

3 ch (UART: 1 ch) 69 2.7 V

PD78054

16 K to 60 K

2.0 V

PD780065

40 K to 48 K

– 4 ch (UART: 1 ch) 60 2.7 V

PD780078

48 K to 60 K

2 ch – 8 ch 3 ch (UART: 2 ch) 52 1.8 V

PD780034A

8 K to 32 K

1 ch 3 ch (UART: 1 ch) 51

PD780024A

8 ch –

PD780034AS

– 4 ch 39 –

PD780024AS

4 ch –

PD78014H 8 ch 2 ch 53

PD78018F

8 K to 60 K

PD78083

8 K to 16 K

–– 1 ch (UART: 1 ch) 33 –

Inverter PD780988

16 K to 60 K

3 ch Note – 1 ch – 8 ch – 3 ch (UART: 2 ch) 47 4.0 V

control

VFD PD780208

32 K to 60 K

2 ch 1 ch 1 ch 1 ch 8 ch ––2 ch 74 2.7 V –

drive

PD780232

16 K to 24 K

3 ch –– 4 ch 40 4.5 V

PD78044H

32 K to 48 K

2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 V

PD78044F

16 K to 40 K

2 ch

LCD PD780354

24 K to 32 K

4 ch 1 ch 1 ch 1 ch – 8 ch – 3 ch (UART: 1 ch) 66 1.8 V –

drive

PD780344 8 ch –

PD780338

48 K to 60 K

3 ch 2 ch – 10 ch 1 ch 2 ch (UART: 1 ch) 54

PD780328 62

PD780318 70

PD780308

48 K to 60 K

2 ch 1 ch 8 ch ––

3 ch (time-division UART: 1 ch)

57 2.0 V

PD78064B 32 K 2 ch (UART: 1 ch)

PD78064

16 K to 32 K

Bus PD780948 60 K 2 ch 2 ch 1 ch 1 ch 8 ch ––3 ch (UART: 1 ch) 79 4.0 V

interface

PD78098B

40 K to 60 K

1 ch 2 ch 69 2.7 V –

supported

PD780816

32 K to 60 K

2 ch 12 ch – 2 ch (UART: 1 ch) 46 4.0 V

Meter PD780958

48 K to 60 K

4 ch 2 ch – 1 ch –––2 ch (UART: 1 ch) 69 2.2 V –

control

Dash- PD780852

32 K to 40 K

3 ch 1 ch 1 ch 1 ch 5 ch ––3 ch (UART: 1 ch) 56 4.0 V – board control

PD780828B

32 K to 60 K

Note 16-bit timer: 2 channels

10-bit timer: 1 channel

VDD

MIN.

Value

Capacity

(Bytes)

√

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

1.7 Block Diagram

Remarks 1. The internal ROM and RAM capacities vary depending on the product.

2. Pin names in parentheses only apply to the µPD78P0208.

16-bit timer/

event counter

8-bit timer/

event counter 1

8-bit timer/

event counter 2

Watchdog timer

Watch timer

Serial

interface 0

Serial

interface 1

A/D converter

Interrupt control

Clock output

control

Buzzer output

TO0/P30

TI0/P00

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

ANI0/P10 to

ANI7/P17

REF

INTP0/P00 to

INTP3/P03

BUZ/P36

PCL/P35

78K/0

CPU core

ROM

RAM

DDVSS

)

Port 0

Port 1

Port 2

Port 3

Port 7

Port 8

Port 9

Port 10

Port 11

Port 12

VFD

controller/

driver

System

control

P01 to P03

P00

P04

P10 to P17

P20 to P27

P30 to P37

P70 to P74

P80 to P87

P90 to P97

P100 to P107

P110 to P117

P120 to P127

FIP0 to FIP52

LOAD

RESET X1 X2 XT1/P04 XT2

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

1.8 Overview of Functions

ROM Mask ROM One-time

PROM

32 KB

Note 1

40 KB

Note 1

48 KB 60 KB 60 KB

Note 2

High-speed RAM 1024 bytes

Expansion RAM – 1024 bytes 1024 bytes

Note 3

Buffer RAM 64 bytes

VFD display RAM 80 bytes

General-purpose registers 8 bits x 8 x 4 banks

With main system 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (when operated at 5.0 MHz) clock selected

With subsystem 122 µs (when operated at 32.768 kHz)

clock selected

• 16-bit operation

• Multiply/divide (8 bits x 8 bits, 16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, and Boolean operation)

• BCD adjust, and other related operations

I/O ports (including VFD pins) Total: 74 pins

• CMOS input: 2 pins

• CMOS I/O: 27 pins

• N-ch open-drain I/O: 5 pins

• P-ch open-drain I/O: 24 pins

• P-ch open-drain output: 16 pins

VFD controller/driver Total of display output: 53 pins

• Segments: 9 to 40 pins

• Digits: 2 to 16 pins

A/D converter • 8-bit resolution x 8 channels

• Power supply voltage: AVDD = 4.0 to 5.5 V

Serial interface • 3-wire serial I/O/SBI/2-wire serial I/O mode selection

possible: 1 channel

• 3-wire serial I/O mode (maximum 64-byte on-chip automatic transmit/receive function): 1 channel

Notes 1. The initial value of the internal memory size switching register (IMS) in the µPD780204A and 780205A

is fixed to CFH (60 KB), regardless of the internal memory capacity. Therefore, set the values shown

below for each product before use.

PD780204A: C8H (32 KB)

PD780205A: CAH (40 KB)

2. 32, 40, 48, or 60 KB can be selected by the internal memory size switching register (IMS).

3. 0 or 1024 bytes can be selected by the internal expansion RAM size switching register (IXS).

Item

Part Number

Internal memory

Instruction set

Minimum instruction execution time

PD780204

PD780204A

PD780205

PD780205A

PD780206µPD780208µPD78P0208

CHAPTER 1 OUTLINE

User’s Manual U11302EJ4V0UM

Item

Part Number

Timer • 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

Timer output 3 outputs (14-bit PWM generation possible from one output)

Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz

(@ 5.0 MHz operation with main system clock)

32.768 kHz (@ 32.768 kHz operation with subsystem clock)

Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz

(@ 5.0 MHz operation with main system clock)

Vectored Maskable interrupts Internal: 9, external: 4 interrupt

sources

Non-maskable interrupts Internal: 1

Software interrupts 1

Test input Internal: 1

Power supply voltage VDD = 2.7 to 5.5 V

Package 100-pin plastic QFP (14 x 20)

1.9 Mask Options

The mask ROM versions (µPD780204, µPD780204A, µPD780205, µPD780205A, µPD780206, and µPD780208) have mask options. By specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed

in Table 1-1 can be incorporated. When these resistors are necessary, the number of external components and

mounting space can be saved by utilizing the mask options.

Table 1-1 shows the mask options provided in the

PD780208 Subseries products.

Table 1-1. Mask Options in Mask ROM Versions

Pin Name Mask Option

P30/TO0 to P32/TO2, P33/TI1, P34/TI2, On-chip pull-down resistor can be specified in 1-bit units. P35/PCL, P36/BUZ, P37

P70 to P74 On-chip pull-up resistor can be specified in 1-bit units.

FIP0 to FIP12 On-chip pull-down resistor can be specified in 1-bit units.

P80/FIP13 to P87/FIP20, P90/FIP21 to On-chip pull-down resistor can be specified in 1-bit units. P97/FIP28, P100/FIP29 to P107/FIP36, The connect destination of a pull-down resistor can be specified for VLOAD or P110/FIP37 to P117/FIP44, VSS in 4-bit units from P80. P120/FIP45 to P127/FIP52

Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10

Calculating Total Power Dissipation) is not exceeded.

PD780204

PD780204A

PD780205

PD780205A

PD780206µPD780208µPD78P0208

User’s Manual U11302EJ4V0UM

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

2.1.1 Normal operating mode pins

(1) Port pins (1/2)

Pin Name I/O Function

After Alternate

Reset Function

P00 Input Input only Input INTP0/TI0

P01 I/O Input INTP1

P02 INTP2

P03 INTP3

P04

Note 1

Input Input only Input XT1

P10 to P17 I/O Port 1. Input ANI0 to ANI7

8-bit I/O port. Input/output can be specified in 1-bit units. If used as an input port, use of an on-chip pull-up resistor can be specified by software settings

Note 2

P20 I/O Input SI1

P21 SO1

P22 SCK1

P23 STB

P24 BUSY

P25 SI0/SB0

P26 SO0/SB1

P27 SCK0

P30 I/O Input TO0

P31 TO1

P32 TO2

P33 TI1

P34 TI2

P35 PCL

P36 BUZ

P37 —

Notes 1. When the P04/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register

(PCC) to 1 (do not use the feedback resistor contained in the subsystem clock oscillator).

2. When the P10/ANI0 to P17/ANI7 pins are used as analog inputs of the A/D converter, set port 1 to

the input mode. In this case, its on-chip pull-up resistor will be automatically disabled.

Port 0. 5-bit I/O port.

Input/output can be specified in 1-bit units. If used as an input port, use of an on-chip pull-up resistor can be specified by software settings.

Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. If used as an input port, use of an on-chip pull-up resistor can be specified by software settings.

Port 3. 8-bit I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. If used as an input port, use of an on-chip pull-up resistor can be specified by software settings. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

(1) Port pins (2/2)

Pin Name I/O Function

After Alternate

Reset Function

P70 to P74 I/O Port 7. Input —

N-ch open-drain 5-bit I/O port. LEDs can be driven directly. Input/output can be specified in 1-bit units. In mask ROM versions, use of an on-chip pull-up resistor can be specified in 1-bit units with the mask option.

P80 to P87 Output Port 8. Output FIP13 to FIP20

P-ch open-drain 8-bit high-withstanding-voltage output port. LEDs can be driven directly. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option (connection to VLOAD or VSS is specifiable in 4-bit units).

P90 to P97 Output Port 9. Output FIP21 to FIP28

P100 to P107 I/O Port 10. Input FIP29 to FIP36

P-ch open-drain 8-bit high-withstanding-voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option (connection to VLOAD or VSS is specifiable in 4-bit units).

P110 to P117 I/O Port 11. Input FIP37 to FIP44

P120 to P127 I/O Port 12. Input FIP45 to FIP52

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

(2) Non-port pins (1/2)

Pin Name I/O Function

After Alternate

Reset Function

INTP0 Input Input P00/TI0

INTP1 P01

INTP2 P02

INTP3 External interrupt request input with falling edge detection P03

SI0 Input Serial interface serial data input Input P25/SB0

SI1 P20

SO0 Output Serial interface serial data output Input P26/SB1

SO1 P21

SB0 I/O Serial interface serial data input/output Input P25/SI0

SB1 P26/SO0

SCK0 I/O Serial interface serial clock input/output Input P27

SCK1 P22

STB Output Serial interface automatic transmit/receive strobe output Input P23

BUSY Input Serial interface automatic transmit/receive busy input Input P24

TI0 Input Input of external count clock to 16-bit timer (TM0) Input P00/INTP0

TI1 Input of external count clock to 8-bit timer (TM1) P33

TI2 Input of external count clock to 8-bit timer (TM2) P34

TO0 Output 16-bit timer (TM0) output (also used for 14-bit PWM output) Input P30

TO1 8-bit timer (TM1) output P31

TO2 8-bit timer (TM2) output P32

PCL Output Clock output (for trimming main system clock and subsystem clock) Input P35

BUZ Output Buzzer output Input P36

FIP0 to FIP12 Output High withstanding voltage and high current output for VFD controller/ Output —

driver display output. In mask ROM versions, use of an on-chip pull-down resistor can be specified with the mask option. The µPD78P0208 has on-chip pull-down resistors (connected to VLOAD).

FIP13 to FIP20

Output Output P80 to P87

FIP21 to FIP28

P90 to P97

FIP29 to FIP36

Input P100 to P107

FIP37 to FIP44

P110 to P117

FIP45 to FIP52

P120 to P127

VLOAD — Pull-down resistor connection for VFD controller/driver — —

ANI0 to ANI7 Input A/D converter analog input Input P10 to P17

AVREF Input A/D converter reference voltage input — —

AVDD — A/D converter analog power supply. Connect to VDD. — —

AVSS — A/D converter ground potential. Connect to VSS. — —

RESET Input System reset input — —

External interrupt request inputs for which the valid edges (rising edge, falling edge, or both rising and falling edges) can be specified.

High withstanding voltage and high current output for VFD controller/ driver display output. In mask ROM versions, use of an on-chip pull-down resistor can be specified with the mask option. The µPD78P0208 has no on-chip pull-down resistors.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

(2) Non-port pins (2/2)

Pin Name I/O Function

After Alternate

Reset Function

X1 Input

Crystal resonator connection for main system clock oscillation

— —

X2 — — —

XT1 Input Crystal resonator connection for subsystem clock oscillation Input P04

XT2 — — —

VDD — Positive power supply — —

VPP — High-voltage application for program write/verify. Connect — —

directly to VSS in normal operation mode.

VSS — Ground potential — —

IC — Internally connected. Connect directly to V

SS. — —

2.1.2 PROM programming mode pins (µPD78P0208 only)

Pin Name I/O Function

RESET Input PROM programming mode setting.

When +5 V or +12.5 V is applied to the VPP pin or a low-level voltage is applied to the RESET pin, the PROM programming mode is set.

VPP Input High-voltage application for PROM programming mode setting and program write/verify

A0 to A16 Input Address bus

D0 to D7 I/O Data bus

CE Input PROM enable input/program pulse input

OE Input Read strobe input to PROM

PGM Input Program/program inhibit input in PROM programming mode

VDD — Positive power supply

VSS — Ground potential

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

2.2 Description of Pin Functions

2.2.1 P00 to P04 (Port 0)

These pins constitute a 5-bit I/O port. Besides serving as I/O port pins, they function as external interrupt request

inputs, an external count clock input to the timer, a capture trigger signal input, and crystal resonator connection for subsystem clock oscillation.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P00 and P04 function as input-only port pins and P01 to P03 function as I/O port pins.

P01 to P03 can be specified in input or output mode in 1-bit units using port mode register 0 (PM0). When they are used as input port pins, an on-chip pull-up resistor can be used by setting the pull-up resistor option register

(PUO).

(2) Control mode

P00 to P04 function as external interrupt request inputs, an external count clock input to the timer, and crystal

connection for subsystem clock oscillation.

(a) INTP0 to INTP3

INTP0 to INTP2 are external interrupt request input pins for which valid edges can be specified (rising edge, falling edge, and both rising and falling edges). INTP0 becomes a 16-bit timer/event counter capture trigger

signal input pin with a valid edge input. INTP3 becomes a falling edge detection external interrupt request

input pin.

(b) TI0

TI0 is a pin for inputting the external count clock to the 16-bit timer/event counter.

Crystal connection pin for subsystem clock oscillation

2.2.2 P10 to P17 (Port 1)

These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as A/D converter analog

inputs.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P10 to P17 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port

mode register 1 (PM1). When they are used as input port pins, an on-chip pull-up resistor can be used by setting the pull-up resistor option register (PUO).

(2) Control mode

P10 to P17 function as A/D converter analog input pins (ANI0 to ANI7). The on-chip pull-up resistors are

automatically disabled when the pins are specified for analog input.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

2.2.3 P20 to P27 (Port 2)

These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as serial interface data I/

O, clock I/O, automatic transmit/receive busy input, and strobe output pins.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P20 to P27 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port

mode register 2 (PM2). When they are used as input port pins, an on-chip pull-up resistor can be used by setting the pull-up resistor option register (PUO).

(2) Control mode

P20 to P27 function as serial interface data I/O, clock I/O, automatic transmit/receive busy input, and strobe output

pins.

(a) SI0, SI1, SO0, SO1

Serial interface serial data I/O pins

(b) SCK0 and SCK1

Serial interface serial clock I/O pins

NEC Electronics standard serial bus interface I/O pins

(d) BUSY

Serial interface automatic transmit/receive busy input pin

(e) STB

Serial interface automatic transmit/receive strobe output pin

Caution If port 2 is used as serial interface pins, the I/O and output latches must be set according

to the function. For the setting method, refer to Figure 13-3 Format of Serial Operating

Mode Register 0 and Figure 14-3 Format of Serial Operating Mode Register 1.

2.2.4 P30 to P37 (Port 3)

These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as timer I/O, clock output,

and buzzer output pins.

In mask ROM versions, use of pull-down resistors can be specified with the mask option.

Port 3 can drive LEDs directly. The following operating modes can be specified in 1-bit units.

(1) Port mode

P30 to P37 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port

mode register 3 (PM3). When they are used as input port pins, an on-chip pull-up resistor can be used by setting

the pull-up resistor option register (PUO).

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

(2) Control mode

P30 to P37 function as timer I/O, clock output, and buzzer output pins.

(a) TI1 and TI2

Pins for external count clock input to the 8-bit timer/event counter.

(b) TO0 to TO2

Timer output pins

Clock output pin

(d) BUZ

Buzzer output pin

2.2.5 P70 to P74 (Port 7)

These pins constitute a 5-bit I/O port. They can be specified in input or output mode in 1-bit units using port

mode register 7 (PM7).

Port 7 can drive LEDs directly.

P70 to P74 are N-ch open-drain outputs. In mask ROM versions, use of pull-up resistors can be specified with

the mask option.

2.2.6 P80 to P87 (Port 8)

These pins constitute an 8-bit output-only port. Besides serving as output port pins, they function as display outputs

for the VFD controller/driver.

Port 8 can drive LEDs directly. The following operating modes can be specified in 1-bit units.

(1) Port mode

P80 to P87 function as an 8-bit output-only port.

P80 to P87 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified

with the mask option.

(2) Control mode

P80 to P87 function as the display output pins of the VFD controller/driver (FIP13 to FIP20).

2.2.7 P90 to P97 (Port 9)

These pins constitute an 8-bit output-only port. Besides serving as output port pins, they function as display outputs

for the VFD controller/driver.

Port 9 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P90 to P97 function as an 8-bit output-only port. P90 to P97 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified

with the mask option.

(2) Control mode

P90 to P97 function as the display output pins of the VFD controller/driver (FIP21 to FIP28).

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

2.2.8 P100 to P107 (Port 10)

These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as display outputs for the

VFD controller/driver.

Port 10 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P100 to P107 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 10 (PM10).

P100 to P107 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified

with the mask option.

(2) Control mode

P100 to P107 function as display output pins for the VFD controller/driver (FIP29 to FIP36).

2.2.9 P110 to P117 (Port 11)

These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as display outputs for the

VFD controller/driver.

Port 11 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P110 to P117 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 11 (PM11).

P110 to P117 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified

with the mask option.

(2) Control mode

P110 to P117 function as display output pins for the VFD controller/driver (FIP37 to FIP44).

2.2.10 P120 to P127 (Port 12)

These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as display outputs for the

VFD controller/driver.

Port 12 can drive LEDs directly.

The following operating modes can be specified in 1-bit units.

(1) Port mode

P120 to P127 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 12 (PM12).

P120 to P127 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified

with the mask option.

(2) Control mode

P120 to P127 function as display output pins for the VFD controller/driver (FIP45 to FIP52).

2.2.11 FIP0 to FIP12

These are display output pins for the VFD controller/driver. FIP0 to FIP12 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified

with the mask option. The

PD78P0208 contains pull-down resistors at FIP0 to FIP12 (connected to VLOAD).

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

2.2.12 VLOAD

This is the pull-down resistor connection pin of the VFD controller/driver.

2.2.13 AV

REF

The A/D converter’s reference voltage should be input from this pin.

2.2.14 AV

This pin supplies power for A/D converter operations.

Always make this pin the same potential as the VDD pin even if the A/D converter is not used.

2.2.15 AV

This pin is the ground for the A/D converter. Always make this pin the same potential as the V

SS pin even if the A/D converter is not used.

2.2.16 RESET

This is an active-low system reset input pin.

2.2.17 X1 and X2

These are crystal resonator connection pins for main system clock oscillation.

For external clock supply, input the clock to X1 and its inverted signal to X2.

2.2.18 XT1 and XT2

These are crystal resonator connection pins for subsystem clock oscillation.

For external clock supply, input the clock to XT1 and its inverted signal to XT2.

2.2.19 V

This is the positive power supply pin.

2.2.20 V

This is the ground potential pin.

2.2.21 V

PP (

PD78P0208 only)

A high-voltage should be applied to this pin during PROM programming mode setting and in program write/verify

mode. Connect directly to V

SS in normal operation mode.

2.2.22 IC (mask ROM version only)

The IC (Internally Connected) pin sets a test mode in which the

PD780204, 780204A, 780205, 780205A, 780206,

and 780208 are tested before shipment. In normal operation mode, connect the IC pin directly to the VSS pin with

as short a wiring length as possible.

If there is a potential difference between the IC and V

SS pins because the wiring length between the IC and VSS

pins is too long, or external noise is superimposed on the IC pin, the user program may not run correctly.

• Directly connect the IC pin to the V

SS pin.

VSSIC

Keep the wiring length as short as possible.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-1 shows the I/O circuit types of pins and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type.

Table 2-1. Types of Pin I/O Circuits (1/2)

Pin Name I/O I/O Recommended Connection of Unused Pins

Circuit Type

P00/INTP0/TI0 2 Input Connect to V

SS.

P01/INTP1 8-A I/O Input: Independently connect to VSS via a resistor.

P02/INTP2

Output: Leave open.

P03/INTP3

P04/XT1 16 Input Connect to VDD or VSS.

P10/ANI0 to P17/ANI7 11 I/O Input: Independently connect to V

DD or VSS via a resistor.

P20/SI1 8-A

Output: Leave open.

P21/SO1 5-A

P22/SCK1 8-A

P23/STB 5-A

P24/BUSY 8-A

P25/SI0/SB0 10-A

P26/SO0/SB1

P27/SCK0

Mask ROM version

P30/TO0 5-C I/O Input: Independently connect to VDD or VSS via a resistor

Note

P31/TO1

Output: Leave open.

P32/TO2

P33/TI1 8-B

P34/TI2

P35/PCL 5-C

P36/BUZ

P37

Note Leave open when an on-chip pull-down resistor is specified by the mask option.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

Table 2-1. Types of Pin I/O Circuits (2/2)

Pin Name I/O I/O Recommended Connection of Unused Pins

Circuit Type

PD78P0208

P30/TO0 5-A I/O Input: Independently connect to VDD or VSS via a resistor.

P31/TO1

Output: Leave open.

P32/TO2

P33/TI1 8-A

P34/TI2

P35/PCL 5-A

P36/BUZ

P37

Mask ROM version

P70 to P74 13-B I/O Input: Independently connect to VDD or VSS via a resistor

Note

Output: Leave open.

FIP0 to FIP12 14-A Output Leave open.

P80/FIP13 to P87/FIP20

P90/FIP21 to P97/FIP28

P100/FIP29 to P107/FIP36 15-C I/O Input: Independently connect to VDD or VSS via a resistor

Note

P110/FIP37 to P117/FIP44

Output: Leave open.

P120/FIP45 to P127/FIP52

IC ——Connect directly to VSS.

PD78P0208

P70 to P74 13-D I/O Input: Independently connect to VDD or VSS via a resistor.

Output: Leave open.

FIP0 to FIP12 14 Output Leave open.

P80/FIP13 to P87/FIP20 14-B Output Leave open.

P90/FIP21 to P97/FIP28

P100/FIP29 to P107/FIP36 15-B I/O Input: Independently connect to VDD or VSS via a resistor.

P110/FIP37 to P117/FIP44

Output: Leave open.

P120/FIP45 to P127/FIP52

VPP ——Connect directly to VSS.

RESET 2 Input —

XT2 16 — Leave open.

AVREF — Connect directly to VSS.

AVDD Connect directly to VDD.

AVSS Connect directly to VSS.

VLOAD

Note Leave open when an on-chip pull-up or pull-down resistor is specified by the mask option.

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

Figure 2-1. Pin I/O Circuits (1/3)

Pull-up enable

P-ch

IN/OUT

Input enable

Output disable

Data

VDD

P-ch

N-ch

Type 2

Type 5-A

Schmitt-triggered input with hysteresis characteristics

Type 5-C Type 10-A

Type 8-B

Type 8-A

Pull-up enable

P-ch

IN/OUT

Output disable

Data

VDD

P-ch

N-ch

Pull-up enable

VDD

P-ch

IN/OUT

Output disable

Data

VDD

P-ch

N-ch

Pull-up enable

P-ch

IN/OUT

Output

disable

Data

VDD

P-ch

N-ch

Mask option

Input enable

Pull-up enable

P-ch

IN/OUT

Open drain

Output disable

Data

VDD

P-ch

N-ch

Mask option

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

Figure 2-1. Pin I/O Circuits (2/3)

Type 11

Type 13-B

Type 13-D Type 14-B

Type 14-A

Type 14

Pull-up enable

P-ch

IN/OUT

Output disable

Data

P-ch

N-ch

P-ch

Comparator

N-ch

Input enable

REF

(Threshold voltage)

–

P-ch

N-ch

P-ch

Data

OUT

LOAD

P-ch

N-ch

P-ch

Data

OUT

LOAD

Mask option

P-ch

N-ch

P-ch

Data

OUT

Data

N-ch

P-ch

IN/OUT

Output disable

Mask option

Middle-voltage input buffer

Data

Output disable

IN/OUT

N-ch

P-ch

Middle-voltage input buffer

CHAPTER 2 PIN FUNCTIONS

User’s Manual U11302EJ4V0UM

Figure 2-1. Pin I/O Circuits (3/3)

Type 15-B

Type 15-C

Type 16

P-ch

XT2XT1

Feedback cut-off

P-ch

N-ch

P-ch

Data

IN/OUT

LOAD

Mask option

N-ch

P-ch

N-ch

P-ch

Data

IN/OUT

N-ch

User’s Manual U11302EJ4V0UM

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

Each product of the µPD780208 Subseries accesses a memory space of 64 KB. Figures 3-1 to 3-5 show memory

maps.

Caution The initial values of the internal memory size switching register (IMS) in the

PD780204A,

780205A, and 78P0208 are fixed to CFH, regardless of the internal memory capacity. Therefore,

set the values shown below for each product before use.

PD780204A: C8H

PD780205A: CAH

PD78P0208: Value corresponding to mask ROM version

Figure 3-1. Memory Map (

PD780204 and µPD780204A)

0000H

Data memory

space

Internal ROM 32768 x 8 bits

7FFFH

1000H 0FFFH

0800H 07FFH

0080H 007FH

0040H 003FH

0000H

CALLF entry area

CALLT table area

Program area

Internal high-speed RAM

1024 x 8 bits

Reserved

Program memory space

8000H 7FFFH

FFFFH

General-purpose

registers

32 x 8 bits

Special-function registers (SFRs) 256 x 8 bits

Vector table area

FA30H FA2FH

VFD display RAM

80 x 8 bits

FA80H FA7FH

FAC0H FABFH

Buffer RAM

64 x 8 bits

FB00H FAFFH

FEE0H FEDFH

FF00H FEFFH

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

Figure 3-2. Memory Map (µPD780205 and µPD780205A)

0000H

Data memory

space

Internal ROM

40960 x 8 bits

9FFFH

1000H 0FFFH

0800H 07FFH

0080H 007FH

0040H 003FH

0000H

CALLF entry area

CALLT table area

Program area

Internal high-speed RAM

1024 x 8 bits

Reserved

Program memory space

A000H 9FFFH

FFFFH

General-purpose

registers

32 x 8 bits

Special-function registers (SFRs) 256 x 8 bits

Vector table area

FA30H FA2FH

VFD display RAM

80 x 8 bits

FA80H FA7FH

FAC0H FABFH

Buffer RAM

64 x 8 bits

FB00H FAFFH

FEE0H FEDFH

FF00H FEFFH

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

Figure 3-3. Memory Map (µPD780206)

Data memory

space

Special-function

registers (SFRs)

256 x 8 bits

General-purpose

registers

32 x 8 bits

Internal high-speed RAM

1024 x 8 bits

Buffer RAM

64 x 8 bits

Reserved

VFD display RAM

80 x 8 bits

Reserved

Internal expansion RAM

1024 x 8 bits

Reserved

Internal ROM

49152 x 8 bits

Program area

CALLF entry area

Program area

CALLT table area

Vector table area

Program

memory space

0000H

0040H 003FH

0080H 007FH

0800H 07FFH

1000H 0FFFH

BFFFH

FFFFH

FF00H FEFFH

FEE0H FEDFH

FB00H FAFFH

FAC0H FABFH

FA80H FA7FH

FA30H FA2FH

F800H F7FFH

F400H F3FFH

C000H BFFFH

0000H

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

Figure 3-4. Memory Map (µPD780208)

Data memory

space

Special-function

registers (SFRs)

256 x 8 bits

General-purpose

registers

32 x 8 bits

Internal high-speed RAM

1024 x 8 bits

Buffer RAM

64 x 8 bits

Reserved

VFD display RAM

80 x 8 bits

Reserved

Internal expansion RAM

1024 x 8 bits

Reserved

Internal ROM

61440 x 8 bits

Program area

CALLF entry area

Program area

CALLT table area

Vector table area

Program

memory space

FFFFH

FF00H FEFFH

FEE0H FEDFH

FB00H FAFFH

FAC0H FABFH

FA80H FA7FH

FA30H FA2FH

F800H F7FFH

F400H F3FFH

F000H EFFFH

0000H

0040H 003FH

0080H 007FH

0800H 07FFH

1000H 0FFFH

EFFFH

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

Figure 3-5. Memory Map (µPD78P0208)

0000H

Data memory

space

Internal PROM

61440 x 8 bits

EFFFH

1000H 0FFFH

0800H 07FFH

0080H 007FH

0040H 003FH

0000H

CALLF entry area

CALLT table area

Program area

Internal high-speed RAM

1024 x 8 bits

Reserved

Program memory space

F000H EFFFH

FFFFH

General-purpose

registers

32 x 8 bits

Special-function registers (SFRs) 256 x 8 bits

Vector table area

FA30H FA2FH

VFD display RAM

80 x 8 bits

FA80H FA7FH

FAC0H FABFH

Buffer RAM

64 x 8 bits

FB00H FAFFH

FEE0H FEDFH

FF00H FEFFH

Internal expansion RAM

1024 x 8 bits

F800H F7FFH

F400H F3FFH

Reserved

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. Normally, this space is addressed using

the program counter (PC).

Each product in the

PD780208 Subseries contains internal ROM (or PROM) with the capacity shown below.

Table 3-1. Internal ROM Capacity

The following areas are allocated to the internal program memory space.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as vector table area. Program start addresses for branch upon RESET input or interrupt request generation are stored in the vector table area. Of the 16-bit address, the lower

8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.

Table 3-2. Vector Table

Vector Table Address Interrupt Source Vector Table Address Interrupt Source

0000H RESET input 0010H INTCSI1

0004H INTWDT 0012H INTTM3

0006H INTP0 0014H INTTM0

0008H INTP1 0016H INTTM1

000AH INTP2 0018H INTTM2

000CH INTP3 001AH INTAD

000EH INTCSI0 001CH INTKS

003EH BRK instruction

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

Internal ROM

Configuration

Mask ROM

PROM

Capacity

32768 x 8 bits

40960 x 8 bits

49152 x 8 bits

61440 x 8 bits

Part Number

PD780204

PD780204A

PD780205

PD780205A

PD780206

PD780208

PD78P0208

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

3.1.2 Internal data memory space

The µPD780208 Subseries units incorporate the following RAMs.

(1) Internal high-speed RAM

Internal high-speed RAM is allocated to the 1024-byte area from FB00H to FEFFH of the

PD780208 Subseries. Four banks of general-purpose registers, each bank consisting of eight 8-bit registers are allocated in the 32-

byte area FEE0H to FEFFH.

This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory.

(2) Internal expansion RAM

Internal expansion RAM is allocated to the 1024-byte area from F400H to F7FFH of the

PD780206, 780208,

and 78P0208.

This area can also be used as a normal data area similar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed.

The internal expansion RAM cannot be used as a stack memory.

(3) Buffer RAM

Buffer RAM is allocated to the 64-byte area from FAC0H to FAFFH. Buffer RAM is used for storing transmit/

receive data of serial interface channel 1 (3-wire serial I/O mode with automatic transmit/receive function). When not used in the 3-wire serial I/O mode with automatic transmit/receive function, buffer RAM can be used

as normal RAM.

(4) VFD display RAM

VFD display RAM is allocated to the 80-byte area from FA30H to FA7FH. VFD display RAM can also be used

as normal RAM.

3.1.3 Special-function register (SFR) area

On-chip peripheral hardware special-function registers (SFRs) are allocated to the area FF00H to FFFFH (see

Table 3-3 Special-Function Register List under 3.2.3 Special-function registers (SFRs)).

Caution Do not access addresses where SFRs are not assigned.

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

3.1.4 Data memory addressing

The method to specify the address of the instruction to be executed next or the address of a register or memory

area to be manipulated when an instruction is executed is called addressing.

The address of the instruction to be executed next is specified by the program counter (PC) (for details, refer

to 3.3 Instruction Address Addressing).

To address the memory area to be manipulated when an instruction is executed, the

PD780208 Subseries has

many addressing modes to improve the operability. Especially, in the areas to which the data memory is assigned

(addresses FB00H to FFFFH), the special-function registers (SFRs) and general-purpose registers can be addressed in accordance with thier function.

Data memory addressing is shown in Figures 3-6 to 3-10. For details of each addressing, refer to 3.4 Operand

Address Addressing.

Figure 3-6. Data Memory Addressing (

PD780204 and µPD780204A)

0000H

Internal ROM

32768 x 8 bits

Internal high-speed RAM

1024 x 8 bits

Buffer RAM

64 x 8 bits

Reserved

8000H 7FFFH

FFFFH

General-purpose registers

32 x 8 bits

Special-function registers (SFRs)

256 x 8 bits

FAC0H FABFH

FB00H FAFFH

FEE0H FEDFH

FF00H FEFFH

VFD display RAM

80 x 8 bits

FA80H FA7FH

FA30H FA2FH

Reserved

FF20H FF1FH

Direct addressing

Based addressing

Based indexed addressing

FE20H FE1FH

SFR addressing

Short direct addressing

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

Figure 3-7. Data Memory Addressing (µPD780205 and µPD780205A)

0000H

Internal ROM

40960 x 8 bits

Internal high-speed RAM

1024 x 8 bits

Buffer RAM

64 x 8 bits

Reserved

A000H 9FFFH

FFFFH

General-purpose registers

32 x 8 bits

Special-function registers (SFRs)

256 x 8 bits

FB00H FAFFH

FAC0H FABFH

FEE0H FEDFH

FF00H FEFFH

VFD display RAM

80 x 8 bits

FA80H FA7FH

FA30H FA2FH

Reserved

FF20H FF1FH

Direct addressing

Based addressing

Based indexed addressing

FE20H FE1FH

SFR addressing

Short direct addressing

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

Figure 3-8. Data Memory Addressing (µPD780206)

Special-function registers (SFRs)

256 x 8 bits

General-purpose registers

32 x 8 bits

Internal high-speed RAM

1024 x 8 bits

Buffer RAM

64 x 8 bits

Reserved

VFD display RAM

80 x 8 bits

Reserved

Internal expansion RAM

1024 x 8 bits

Reserved

Internal ROM

49152 x 8 bits

SFR addressing

Short direct addressing

Direct addressing

Based addressing

Based indexed addressing

FFFFH

FF20H FF1FH

FF00H FEFFH

FEE0H FEDFH

FE20H FE1FH

FB00H FAFFH

FAC0H FABFH

FA80H FA7FH

FA30H FA2FH

F800H F7FFH

F400H F3FFH

C000H BFFFH

0000H

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

Figure 3-9. Data Memory Addressing (µPD780208)

Special-function registers (SFRs)

256 x 8 bits

General-purpose registers

32 x 8 bits

Internal high-speed RAM

1024 x 8 bits

Buffer RAM

64 x 8 bits

Reserved

VFD display RAM

80 x 8 bits

Reserved

Internal expansion RAM

1024 x 8 bits

Reserved

Internal ROM

61440 x 8 bits

SFR addressing

Short direct addressing

Direct addressing

Based addressing

Based indexed addressing

FFFFH

FF20H FF1FH

FF00H FEFFH

FEE0H FEDFH

FE20H FE1FH

FB00H FAFFH

FAC0H FABFH

FA80H FA7FH

FA30H FA2FH

F800H F7FFH

F400H F3FFH

F000H EFFFH

0000H

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

Figure 3-10. Data Memory Addressing (µPD78P0208)

0000H

Internal PROM

61440 x 8 bits

Internal high-speed RAM

1024 x 8 bits

Buffer RAM

64 x 8 bits

Reserved

F000H EFFFH

FFFFH

General-purpose registers

32 x 8 bits

Special-function registers (SFRs)

256 x 8 bits

FB00H FAFFH

FA30H FA2FH

FEE0H FEDFH

FF00H FEFFH

Internal expansion RAM

1024 x 8 bits

F800H F7FFH

F400H F3FFH

Reserved

FF20H FF1FH

Direct addressing

Based addressing

Based indexed addressing

FE20H FE1FH

SFR addressing

Short direct addressing

FA80H FA7FH

FAC0H FABFH

VFD display RAM

80 x 8 bits

Reserved

CHAPTER 3 CPU ARCHITECTURE

User’s Manual U11302EJ4V0UM

3.2 Processor Registers

The µPD780208 Subseries units incorporate the following processor registers.

3.2.1 Control registers

The control registers control the program sequence, statuses, and stack memory. The program counter (PC),

program status word (PSW), and stack pointer (SP) are control registers.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-11. Program Counter Format

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are automatically reset upon execution of the RETB, RETI, and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-12. Program Status Word Format

(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledgment operations of the CPU.

When IE = 0, the IE flag is set to the interrupt disabled (DI) status. All interrupts except non-maskable interrupts are disabled.

When IE = 1, the IE flag is set to the interrupt enabled (EI) status and interrupt request acknowledgment

is controlled by an in-service priority flag (ISP), an interrupt mask flag for each interrupt source, and a priority specification flag.

This flag is reset to (0) upon DI instruction execution or interrupt request acknowledgment and is set to

(1) upon EI instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

These are 2-bit flags used to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction

execution is stored.

15 0

PC15 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0PC14

IEPSW

Z RBS1 AC RBS0 0 ISP CY

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User’s Manual U11302EJ4V0UM

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0,

acknowledgment of a vectored interrupt request specified as lower priority by the priority specification flag

registers (PR0L and PR0H) (refer to 16.3 (3) Priority specification flag registers (PR0L, PR0H)) is disabled. Whether the interrupt request is actually acknowledged or not is controlled by the interrupt enable

flag (IE).

(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value

upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.

(3) Stack pointer (SP)

This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-speed

RAM area (FB00H to FEFFH) can be set as the stack area.

Figure 3-13. Stack Pointer Format

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from

the stack memory.

Each stack operation saves/resets data as shown in Figures 3-14 and 3-15.

Caution Because RESET input makes SP contents undefined, be sure to initialize the SP before

instruction execution.

15 0

SP15 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0SP14

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Figure 3-14. Data to Be Saved to Stack Memory

Figure 3-15. Data to Be Reset from Stack Memory

Interrupt and

BRK instruction

CALL, CALLF, and CALLT instructions

PUSH rp instruction

Lower

Higher

SP SP – 2

SP – 2

SP – 1

SP SP – 2

SP – 2

SP – 1

PC7 to PC0

PC15 to PC8

SP SP – 3

SP – 3

SP – 2

SP – 1

PC15 to PC8

PSW

PC7 to PC0

RETI and RETB instructions

PC15 to PC8

PSW

PC7 to PC0

SP SP + 3

SP + 1

SP + 2

PC15 to PC8

PC7 to PC0

SP SP + 2

SP + 1

Lower

SP SP + 2

SP + 1

Higher

RET instructionPOP rp instruction

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3.2.2 General-purpose registers

General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. They

consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register

(AX, BC, DE, and HL).

They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute

names (R0 to R7 and RP0 to RP3).

Register banks to be used for instruction execution are set using the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal

processing and a register for interrupts for each bank.

Figure 3-16. General-Purpose Register Configuration

(a) Absolute name

(b) Function name

BANK0

BANK1

BANK2

BANK3

FEFFH

FEF8H

FEF0H

FEE8H

FEE0H

RP3

RP2

RP1

RP0

15 0 7 0

16-bit processing 8-bit processing

BANK0

BANK1

BANK2

BANK3

FEFFH

FEF8H

FEF0H

FEE8H

FEE0H

15 0 7 0

16-bit processing 8-bit processing

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3.2.3 Special-function registers (SFRs)

Unlike a general-purpose register, each special-function register has a special function. The special-function

registers are allocated in the FF00H to FFFFH area.

Special-function registers can be manipulated, like general-purpose registers, with operation, transfer, and bit

manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special-function register type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Describe the symbol reserved in the assembler for the 1-bit manipulation instruction operand (sfr.bit).

This manipulation can also be specified with an address.

• 8-bit manipulation

Describe the symbol reserved in the assembler for the 8-bit manipulation instruction operand (sfr).

This manipulation can also be specified with an address.

• 16-bit manipulation

Describe the symbol reserved in the assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, describe an even address.

Table 3-3 gives a list of special-function registers. The meaning of items in the table is as follows.

• Symbol

Indicates symbols that specify the addresses of the special-function registers. The RA78K0 uses these symbols as reserved words, and the CC78K0 defines them in the header file “sfrbit.h”. Symbols can be used

as instruction operands if the RA78K0, ID78K0, or SD78K0 is used.

• R/W

Indicates whether the corresponding special-function register can be read or written.

R/W: Read/write enable R: Read only

W: Write only

• Manipulatable bit units

√ indicates manipulatable bit units (1, 8, and 16). – indicates unmanipulatable bit units.

• After reset

Indicates each register status upon RESET input.

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Table 3-3. Special-Function Register List (1/3)

Address Special-Function Register (SFR) Name Symbol R/W Manipulatable

Bit Unit

1 Bit 8 Bits 16 Bits

FF00H Port 0 P0 R/W √ √ – 00H FF01H Port 1 P1 √ √ – FF02H Port 2 P2 √ √ – FF03H Port 3 P3 √ √ – FF07H Port 7 P7 √ √ – FF08H Port 8 P8 W √ √ – FF09H Port 9 P9 √ √ – FF0AH Port 10 P10 R/W √ √ – FF0BH Port 11 P11 √ √ – FF0CH Port 12 P12 √ √ –

FF10H 16-bit compare register CR00 ––√ Undefined

FF11H FF12H 16-bit capture register CR01 R ––√

FF13H FF14H 16-bit timer register TM0 ––√ 0000H

FF15H FF16H 8-bit compare register 10 CR10 R/W – √ – Undefined FF17H 8-bit compare register 20 CR20 – √ – FF18H 8-bit timer register 1 TMS TM1 R – √ √ 00H FF19H 8-bit timer register 2 TMS TM2 – √ FF1AH Serial I/O shift register 0 SIO0 R/W – √ – Undefined FF1BH Serial I/O shift register 1 SIO1 – √ – FF1FH A/D conversion result register ADCR R – √ – FF20H Port mode register 0 PM0 R/W √ √ – 1FH FF21H Port mode register 1 PM1 √ √ – FFH FF22H Port mode register 2 PM2 √ √ – FF23H Port mode register 3 PM3 √ √ – FF27H Port mode register 7 PM7 √ √ – 1FH FF2AH Port mode register 10 PM10 √ √ – FFH FF2BH Port mode register 11 PM11 √ √ – FF2CH Port mode register 12 PM12 √ √ – FF40H Timer clock select register 0 TCL0 R/W √ √ – 00H FF41H Timer clock select register 1 TCL1 – √ – FF42H Timer clock select register 2 TCL2 – √ – FF43H Timer clock select register 3 TCL3 – √ – 88H FF47H Sampling clock select register SCS – √ – 00H FF48H 16-bit timer mode control register TMC0 √ √ – FF49H 8-bit timer mode control register TMC1 √ √ – FF4AH Watch timer mode control register TMC2 √ √ – FF4EH 16-bit timer output control register TOC0 √ √ – FF4FH 8-bit timer output control register TOC1 √ √ –

After Reset

TMS

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Table 3-3. Special-Function Register List (2/3)

Address Special-Function Register (SFR) Name Symbol R/W Manipulatable

Bit Unit

1 Bit 8 Bits 16 Bits

FF60H Serial operating mode register 0 CSIM0 R/W √ √ – 00H FF61H Serial bus interface control register SBIC √ √ – FF62H Slave address register SVA – √ – Undefined FF63H Interrupt timing specification register SINT √ √ – 00H FF68H Serial operating mode register 1 CSIM1 √ √ – FF69H Automatic data transmit/receive control register ADTC √ √ – FF6AH Automatic data transmit/receive address pointer ADTP – √ – FF6BH Automatic data transmit/receive interval specification ADTI √ √ –

FF80H A/D converter mode register ADM √ √ – 01H FF84H A/D converter input select register ADIS – √ – 00H

FFA0H Display mode register 0 DSPM0 ∆

Note

√ –

FFA1H Display mode register 1 DSPM1 – √ – FFA2H Display mode register 2 DSPM2 – √ – FFE0H Interrupt request flag register 0L xxxx IF0L √ √√ FFE1H Interrupt request flag register 0H xxxx IF0H √ √ FFE4H Interrupt mask flag register 0L xxx x MK0L √ √√ FFH FFE5H Interrupt mask flag register 0H MK0H √ √ FFE8H Priority order specification flag register 0L PR0L √ √√ FFE9H Priority order specification flag register 0H xxxx PR0H √ √ FFECH External interrupt mode register INTM0 – √ – 00H

After Reset

IF0

MK0

Note Only bit 7 can be manipulated, and only as a read operation.

PR0

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Table 3-3. Special-Function Register List (3/3)

Address Special-Function Register (SFR) Name Symbol R/W Manipulatable

Bit Unit

1 Bit 8 Bits 16 Bits

FFF0H Internal memory size switching register IMS R/W – √ –

Note

FFF4H Internal expansion RAM size switching register IXS W – √ –

Note

FFF7H Pull-up resistor option register PUO R/W √ √ –00H FFF9H Watchdog timer mode register WDTM √ √ – FFFAH Oscillation stabilization time select register OSTS – √ –04H FFFBH Processor clock control register PCC √ √ –

Note The value after resetting the internal memory size switching register (IMS) and internal expansion RAM

size switching register (IXS) depends on the product.

PD780204 µPD780204A

PD780205µPD780205AµPD780206

PD780208µPD78P0208

IMS C8H CFH CAH CFH CCH CFH CFH

IXS None 0AH

When using the µPD780204, 780205, 780206, and 780208, do not set any value other than that of IMS

and IXS after reset. When using the

PD780204A, 780205A, and 78P0208, the initial values of IMS are fixed to CFH,

regardless of the internal memory capacity. Therefore, set the values shown below for each product

before use.

PD780204A: C8H

PD780205A: CAH

PD78P0208: Value corresponding to mask ROM version

After Reset

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3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents. The PC contents are normally

incremented (+1 for each byte) automatically according to the number of bytes of the instruction to be fetched each

time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and the program is branched by the following addressing (for details of instructions, refer to the

78K/0 Series Instructions User’s Manual (U12326E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The displacement

value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit. In other words, the range of branch in relative addressing is between –128 and +127 of the start address of the following instruction.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15 0

876

15 0

jdisp8

When S = 0, all bits of α are 0. When S = 1, all bits of α are 1.

PC indicates the start address of the instruction after the BR instruction.

...

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3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.

CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces. CALLF !addr11 instruction

branches to the area from 0800H to 0FFFH.

[Illustration]

In the case of CALL !addr16 and BR !addr16 instructions

In the case of CALLF !addr11 instruction

15 0

CALL or BR

Low addr.

High addr.

15 0

10–8

11 10

00001

643

CALLF

7–0

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3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the

immediate data of an operation code are transferred to the program counter (PC) and branched.

Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can

refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.

[Illustration]

15 1

15 0

Low addr.

High addr.

Memory (table)

Effective address + 1

Effective address

00000000

65 0

111

765 10

4_0

Operation code

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User’s Manual U11302EJ4V0UM

3.3.4 Register addressing

[Function]

and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

15 0

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3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) which undergo manipulation

during instruction execution.

3.4.1 Implied addressing

[Function]

The register which functions as an accumulator (A and AX) in the general-purpose register area is automatically

(implicitly) addressed.

Of the

PD780208 Subseries instruction words, the following instructions employ implied addressing.

Instruction Register to Be Specified by Implied Addressing

MULU Register A for multiplicand and register AX for product storage

DIVUW Register AX for dividend and quotient storage

ADJBA/ADJBS Register A for storage of numeric values subject to decimal adjustment

ROR4/ROL4 Register A for storage of digit data which undergoes digit rotation

[Operand format]

Because implied addressing can be automatically employed with an instruction, no particular operand format

is necessary.

[Description example]

In the case of MULU X

With an 8-bit x 8-bit multiply instruction, the product of register A and register X is stored in AX. In this example,

the A and AX registers are specified by implied addressing.

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3.4.2 Register addressing

[Function]

A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified

by register bank select flags (RBS0 and RBS1) and the register specification code (Rn, RPn) in the operation code.

8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

[Operand format]

Identifier Description

r X, A, C, B, E, D, L, H

rp AX, BC, DE, HL

‘r’ and ‘rp’ can be described using function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) as well as absolute

names (R0 to R7 and RP0 to RP3).

[Description example]

MOV A, C; when selecting C register as r

INCW DE; when selecting DE register pair as rp

Operation code

01100010

Operation code

10000100

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3.4.3 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier Description

addr16 Label or 16-bit immediate data

[Description example]

MOV A, !0FE00H; when setting !addr16 to FE00H

[Illustration]

Operation code

10001110

00000000

11111110

Opcode

00H

FEH

addr16 (lower)

Opcode

Memory

addr16 (lower)

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3.4.4 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space to which this addressing is applied to is the 256-byte space from FE20H to FF1FH. An internal high-speed RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,

respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the total SFR area. In this area, ports which are frequently accessed in a program and compare and capture registers of the timer/event

counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to [Illustration] below.

[Operand format]

Identifier Description

saddr Label or immediate data indicating FE20H to FF1FH

saddrp Label or immediate data indicating FE20H to FF1FH (even address only)

[Description example]

MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H

[Illustration]

Operation code

00010001

00110000

01010000

15 0

Opcode

saddr-offset

Effective address

When 8-bit immediate data is 20H to FFH, α = 0

1111111

Short direct memory

When 8-bit immediate data is 00H to 1FH, α = 1

Opcode

30H (saddr-offset)

50H (immediate data)

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3.4.5 Special-function register (SFR) addressing

[Function]

A memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs

mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier Description

sfr Special-function register name

sfrp 16-bit manipulatable special-function register name (even address only)

[Description example]

MOV PM0, A; when selecting PM0 (FF20H) as sfr

[Illustration]

Operation code

11110110

00100000

15 0

Opcode

sfr-offset

Effective address

1111111

SFR

Opcode

20H (sfr-offset)

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3.4.6 Register indirect addressing

[Function]

The memory is addressed with the contents of the register pair specified as an operand. The register pair to

be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specification code in the instruction code. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

—

[DE], [HL]

[Description example]

MOV A, [DE]; when selecting [DE] as register pair

[Illustration]

Operation code

10000101

15 078

The contents of addressed memory are transferred

Memory address specified by register pair DE

Memory

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3.4.7 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is

used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to

16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

—

[HL+byte]

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Operation code

10101110

00010000

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3.4.8 Based indexed addressing

[Function]

The B or C register contents specified in an instruction word are added to the contents of the base register, that

is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1).

Addition is performed by expanding the contents of the B or C register as a positive number to 16 bits. A carry

from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

—

[HL+B], [HL+C]

[Description example]

In the case of MOV A, [HL+B] (select B register)

3.4.9 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/reset upon generation of an interrupt request.

Stack addressing can be used to address the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE (save DE register)

Operation code

10101011

Operation code

10110101

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

The µPD780208 Subseries units incorporate two input ports, 16 output ports, and 56 I/O ports. Figure 4-1 shows

the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out various control operations. Besides port functions, the ports can also serve as on-chip hardware I/O pins.

Figure 4-1. Port Types

Port 9

P90

P97

P100

P107

P110

P117

P120

P127

P04

P10

P17

P20

P27

P30

P37

P70

P74

P00

P80

P87

Port 10

Port 11

Port 12

Port 1

Port 0

Port 2

Port 3

Port 7

Port 8

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Table 4-1. Port Functions (1/2)

Pin Name Function Alternate

Function

P00 Input only. INTP0/TI0

P01 INTP1

P02 INTP2

P03 INTP3

P04 Input only. XT1

P10 to P17 Port 1. ANI0 to ANI7

8-bit I/O port. Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistors can be used by software settings.

P20 SI1

P21 SO1

P22 SCK1

P23 STB

P24 BUSY

P25 SI0/SB0

P26 SO0/SB1

P27 SCK0

P30 TO0

P31 TO1

P32 TO2

P33 TI1

P34 TI2

P35 PCL

P36 BUZ

P37 –

P70 to P74 Port 7. –

N-ch open-drain 5-bit I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of pull-up resistors can be specified in 1-bit units with the mask option.

P80 to P87 Port 8. FIP13 to FIP20

P-ch open-drain 8-bit high withstanding voltage output port. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to V

LOAD or VSS in 4-bit units).

P90 to P97 Port 9. FIP21 to FIP28

Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistors can be used by software settings.

Port 0. 5-bit I/O port.

Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistors can be used by software settings.

Port 3. 8-bit I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. If used as an input port, on-chip pull-up resistors can be used by software settings. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option.

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Table 4-1. Port Functions (2/2)

Alternate

Pin Name Function

Function

P100 to P107 Port 10. FIP29 to FIP36

P-ch open-drain 8-bit high withstanding voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to V

LOAD or VSS in 4-bit units).

P110 to P117 Port 11. FIP37 to FIP44

P120 to P127 Port 12. FIP45 to FIP52

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User’s Manual U11302EJ4V0UM

4.2 Port Configuration

A port consists of the following hardware.

Table 4-2. Port Configuration

Item Configuration

Control registers Port mode register (PMm: m = 0, 1, 2, 3, 7, 10, 11, 12)

Pull-up resistor option register (PUO)

Ports Total: 74 (2 input, 16 output, 56 I/O)

Pull-up resistors • Mask ROM versions

Total: 32 (software control: 27, mask option control: 5)

•µPD78P0208 ... Total: 27

Pull-down resistors • Mask ROM versions ... Total: 48 (mask option control: 48)

4.2.1 Port 0

Port 0 is a 5-bit I/O port with an output latch. The P01 to P03 pins can be set to input mode/output mode in 1-

bit units using port mode register 0 (PM0). The P00 and P04 pins are input-only port pins. When the P01 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected to them in 3-bit units using the pull-

up resistor option register (PUO).

Alternate functions include external interrupt request input, external count clock input to the timer, and crystal connection for subsystem clock oscillation.

RESET input sets port 0 to input mode.

Figures 4-2 and 4-3 show block diagrams of port 0.

Caution Because port 0 can also be used for external interrupt request input, when the port function

output mode is specified and the output level is changed, the interrupt request flag is set. Thus,

when the output mode is used, set the interrupt mask flag to 1.

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Figure 4-2. Block Diagram of P00 and P04

Figure 4-3. Block Diagram of P01 to P03

PUO: Pull-up resistor option register

PM: Port mode register

RD: Port 0 read signal WR: Port 0 write signal

P00/INTP0/TI0, P04/XT1

Internal bus

P-ch

PORT

PUO

P01/INTP1, P02/INTP2, P03/INTP3

Selector

PUO0

Output latch (P01 to P03)

PM01 to PM03

Internal bus

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4.2.2 Port 1

Port 1 is an 8-bit I/O port with an output latch. The P10 to P17 pins can be set to input mode/output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull-

up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO).

Alternate functions include A/D converter analog input.

RESET input sets port 1 to input mode.

Figure 4-4 shows a block diagram of port 1.

Caution A pull-up resistor cannot be connected to pins used for A/D converter analog input.

Figure 4-4. Block Diagram of P10 to P17

PUO: Pull-up resistor option register

PM: Port mode register

RD: Port 1 read signal WR: Port 1 write signal

P-ch

PORT

PUO

P10/ANI0

P17/ANI7

Selector

PUO1

Output latch (P10 to P17)

PM10 to PM17

Internal bus

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4.2.3 Port 2

Port 2 is an 8-bit I/O port with an output latch. The P20 to P27 pins can be set to input mode/output mode in 1-bit units using port mode register 2 (PM2). When the P20 to P27 pins are used as input port pins, on-chip pull-

up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO).

Alternate functions include serial interface data I/O, clock I/O, automatic transmit/receive busy input, and strobe output.

RESET input sets port 2 to input mode.

Figures 4-5 and 4-6 show block diagrams of port 2.

Cautions 1. If used as serial interface pins, set the I/O and output latch according to each function. Refer

to Figure 13-3 Format of Serial Operating Mode Register 0 and Figure 14-3 Format of Serial

Operating Mode Register 1 for the settings.

2. When reading the pin state in SBI mode, set the PM2n bit of PM2 to 1 (n = 5, 6) (refer to the

description of (10) Judging busy status of slave in 13.4.3 SBI mode operation).

Figure 4-5. Block Diagram of P20, P21, P23 to P26

PUO: Pull-up resistor option register

PM: Port mode register RD: Port 2 read signal

WR: Port 2 write signal

P-ch

PORT

PUO

P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0, P26/SO0/SB1

Selector

PUO2

Output latch

(P20, P21, P23 to P26)

PM20, PM21, PM23 to PM26

Alternate function

Internal bus

CHAPTER 4 PORT FUNCTIONS

User’s Manual U11302EJ4V0UM

Figure 4-6. Block Diagram of P22 and P27

PUO: Pull-up resistor option register

PM: Port mode register RD: Port 2 read signal

WR: Port 2 write signal

P-ch

PORT

PUO

P22/SCK1, P27/SCK0

Selector

PUO2

Output latch

(P22, P27)

PM22, PM27

Alternate function

Internal bus

CHAPTER 4 PORT FUNCTIONS

User’s Manual U11302EJ4V0UM

4.2.4 Port 3

Port 3 is an 8-bit I/O port with an output latch. The P30 to P37 pins can be set to input mode/output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P37 pins are used as input port pins, on-chip pull-

up resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO).

In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. The

PD78P0208 does not contain pull-down resistors.

Port 3 can drive LEDs directly.

Alternate functions include timer I/O, clock output, and buzzer output.

RESET input sets port 3 to input mode.

Figure 4-7 shows a block diagram of port 3.

Figure 4-7. Block Diagram of P30 to P37

PUO: Pull-up resistor option register

PM: Port mode register

RD: Port 3 read signal WR: Port 3 write signal

P-ch

PORT

PUO

Only mask ROM versions. The PD78P0208 has no pull-down resistors.

Selector

PUO3

Output latch (P30 to P37)

PM30 to PM37

Alternate function

Internal bus

P30/TO0 to P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37

Mask option

CHAPTER 4 PORT FUNCTIONS

User’s Manual U11302EJ4V0UM

4.2.5 Port 7

Port 7 is a 5-bit I/O port with an output latch. The P70 to P74 pins can be set to input mode/output mode in 1bit units using port mode register 7 (PM7). In mask ROM versions, use of pull-up resistors can be specified in 1-

bit units with the mask option. The

PD78P0208 does not contain pull-up resistors.

Port 7 can drive LEDs directly.

RESET input sets port 7 to input mode.

Figure 4-8 shows a block diagram of port 7.

Caution The low-level input leak current flowing to the P70 to P74 pins varies depending on the following

conditions.

[For mask ROM version]

• When a pull-up resistor is connected:

• –3

A (max.) regardless of operational conditions

• When a pull-up resistor is not connected:

• –200

A (max.) during 1.5 clock cycles after read instruction execution to port 7 (P7)

or port mode register 7 (PM7)

• –3

A (max.) under other conditions

[For PROM version]

• –200

A (max.) during 1.5 clock cycles after read instruction execution to port 7 (P7)

or port mode register 7 (PM7)

• –3 µA (max.) under other conditions

Figure 4-8. Block Diagram of P70 to P74

PM: Port mode register RD: Port 7 read signal

WR: Port 7 write signal

Internal bus

Output latch

(P70 to P74)

PORT

PM70 to PM74

Selector

Only mask ROM versions. The PD78P0208 has no pull-up resistors.

Mask option

P70 to P74

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User’s Manual U11302EJ4V0UM

4.2.6 Port 8

Port 8 is an 8-bit output-only port. In mask ROM versions, use of pull-down resistors can be specified in 1-bit

units with the mask option. Pull-down resistor connection to V

LOAD or VSS can be specified in 4-bit units. The

PD78P0208 does not contain pull-down resistors.

Port 8 can drive LEDs directly. Alternate functions include VFD controller/driver display output.

RESET input sets port 8 to output mode.

Figure 4-9 shows a block diagram of port 8.

Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10

Calculating Total Power Dissipation) is not exceeded.

Figure 4-9. Block Diagram of P80 to P87

WR: Port 8 write signal

Internal bus

Output latch

(P80 to P87)

PORT

Alternate function

Mask option

P80/FIP13

P87/FIP20

LOAD

P-ch open-drain

Only mask ROM versions. The PD78P0208 has no pull-down resistors.

CHAPTER 4 PORT FUNCTIONS

User’s Manual U11302EJ4V0UM

4.2.7 Port 9

Port 9 is an 8-bit output-only port. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to V

LOAD or VSS can be specified in 4-bit units. The

PD78P0208 does not contain pull-down resistors.

Port 9 can drive LEDs directly.

Alternate functions include VFD controller/driver display output.

RESET input sets port 9 to output mode.

Figure 4-10 shows a block diagram of port 9.

Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10

Calculating Total Power Dissipation) is not exceeded.

Figure 4-10. Block Diagram of P90 to P97

WR: Port 9 write signal

Internal bus

Output latch

(P90 to P97)

PORT

Alternate function

Mask option

P90/FIP21

P97/FIP28

LOAD

P-ch open-drain

Only mask ROM versions. The PD78P0208 has no pull-down resistors.

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User’s Manual U11302EJ4V0UM

4.2.8 Port 10

Port 10 is an 8-bit I/O port with an output latch. The P100 to P107 pins can be set to input mode/output mode in 1-bit units using port mode register 10 (PM10). In mask ROM versions, use of pull-down resistors can be specified

in 1-bit units with the mask option. Pull-down resistor connection to V

LOAD or VSS can be specified in 4-bit units.

The µPD78P0208 does not contain pull-down resistors.

Port 10 can drive LEDs directly.

Alternate functions include VFD controller/driver display output.

RESET input sets port 10 to input mode.

Figure 4-11 shows a block diagram of port 10.

Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10

Calculating Total Power Dissipation) is not exceeded.

Figure 4-11. Block Diagram of P100 to P107

PORT

Internal bus

Selector

Output latch

(P100 to P107)

PM100 to PM107

Alternate function

P100/FIP29

P107/FIP36

LOAD

Mask option Only mask ROM versions. The PD78P0208 has no pull-down resistors.

PM:

RD:

WR:

Port mode register

Port 10 read signal

Port 10 write signal

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User’s Manual U11302EJ4V0UM

4.2.9 Port 11

Port 11 is an 8-bit I/O port with an output latch. The P110 to P117 pins can be set to input mode/output mode in 1-bit units using port mode register 11 (PM11). In mask ROM versions, use of pull-down resistors can be specified

in 1-bit units with the mask option. Pull-down resistor connection to V

LOAD or VSS can be specified in 4-bit units.

The µPD78P0208 does not contain pull-down resistors.

Port 11 can drive LEDs directly.

Alternate functions include VFD controller/driver display output.

RESET input sets port 11 to input mode.

Figure 4-12 shows a block diagram of port 11.

Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10

Calculating Total Power Dissipation) is not exceeded.

Figure 4-12. Block Diagram of P110 to P117

PM: Port mode register RD: Port 11 read signal

WR: Port 11 write signal

Internal bus

PORT

PM110 to PM117

Selector

Mask option

P110/FIP37

P117/FIP44

Alternate function

LOAD

Only mask ROM versions. The PD78P0208 has no pull-down resistors.

Output latch

(P110 to P117)

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User’s Manual U11302EJ4V0UM

4.2.10 Port 12

Port 12 is an 8-bit I/O port with an output latch. The P120 to P127 pins can be set to input mode/output mode in 1-bit units using port mode register 12 (PM12). In mask ROM versions, use of pull-down resistors can be specified

in 1-bit units with the mask option. Pull-down resistor connection to V

LOAD or VSS can be specified in 4-bit units.

The µPD78P0208 does not contain pull-down resistors.

Port 12 can drive LEDs directly.

Alternate functions include VFD controller/driver display output.

RESET input sets port 12 to input mode.

Figure 4-13 shows a block diagram of port 12.

Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10

Calculating Total Power Dissipation) is not exceeded.

Figure 4-13. Block Diagram of P120 to P127

PM: Port mode register

RD: Port 12 read signal WR: Port 12 write signal

Internal bus

Output latch

(P120 to P127)

PORT

PM120 to PM127

Selector

Mask option

P120/FIP45

P127/FIP52

Alternate function

LOAD

Only mask ROM versions. The PD78P0208 has no pull-down resistors.

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User’s Manual U11302EJ4V0UM

4.3 Port Function Control Registers

The following two types of registers control the ports.

• Port mode registers (PM0, PM1, PM2, PM3, PM7, PM10, PM11, PM12)

• Pull-up resistor option register (PUO)

(1) Port mode registers (PM0, PM1, PM2, PM3, PM7, PM10, PM11, PM12)

These registers are used to set port input/output in 1-bit units. PM0, PM1, PM2, PM3, PM7, PM10, PM11, and PM12 are independently set with a 1-bit or 8-bit memory

manipulation instruction.

RESET input sets PM0 and PM7 to 1FH, and the other registers to FFH. When a port pin is used as an alternate-function pin, set the port mode register and the output latch according

to Table 4-3.

Cautions 1. Pins P00 and P04 are input-only pins.

2. Pins P80 to P87 and P90 to P97 are output-only pins.

3. As port 0 has an alternate function as external interrupt request input, when the port

function output mode is specified and the output level is changed, the interrupt request flag

is set. When the output mode is used, therefore, the interrupt mask flag should be set to

1 beforehand.

Table 4-3. Port Mode Register and Output Latch Setting When Alternate Function Is Used

Pin Name Alternate Function PMxx Pxx Pin Name Alternate Function PMxx Pxx

P00 INTP0 Input 1 (fixed) None P33, P34 TI1, TI2 Input 1 X

TI0 Input 1 (fixed) None P35 PCL Output 0 0

P01, P02 INTP1, INTP2 Input 1 X P36 BUZ Output 0 0

P03 INTP3 Input 1 X P100 to P107 FIP29 to FIP36 Output 0 0

Note 2

P04

Note 1

XT1 Input 1 (fixed) None P110 to P117 FIP37 to FIP44 Output 0 0

Note 2

P10 to P17

ANI0 to ANI7 Input 1 X P120 to P127 FIP45 to FIP52 Output 0 0

Note 2

P30 to P32 TO0 to TO2 Output 0 0

Notes 1. If a read instruction is executed to these ports in the alternate-function mode, the read data will be

undefined.

2. Key scan data can be set while the VFD controller/driver is operating.

Caution When port 2 is used as serial interface pins, I/O and the output latch should be set according

to the function. For the settings, refer to Figure 13-3 Format of Serial Operating Mode Register

0 and Figure 14-3 Format of Serial Operating Mode Register 1.

Remark X: don’t care

PMxx: Port mode register Pxx: Port output latch

Note 1

I/O

Function Name

CHAPTER 4 PORT FUNCTIONS

User’s Manual U11302EJ4V0UM

Figure 4-14. Format of Port Mode Register

PM0

PM1

PM2

PM37

PM127 PM126 PM125 PM124 PM123 PM122

PM121 PM120

0 0 1 PM03 PM02 PM01 1

76543210Symbol

PM16 PM15 PM14 PM13 PM12 PM11

PM26 PM25 PM24 PM23 PM22 PM21

PM36 PM35 PM34 PM33 PM32 PM31

PM17 PM10

PM27

PM3

PM20

PM30

PM12

PMmn

Pmn pin I/O mode selection (m = 0, 1, 2, 3, 7, 10, 11, 12 : n = 0 to 7)

Output mode (output buffer on)

Input mode (output buffer off)

FF20H

FF2CH

FF21H

FF22H

FF23H

1FH

FFH

R/W

Address After reset R/W

0 PM72 PM710 0 PM74 PM73

PM70

PM7

FF27H 1FH R/W

PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110PM11 FF2BH FFH R/W

PM107 PM102 PM101PM106 PM105 PM104 PM103

PM100

PM10

FF2AH FFH R/W

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User’s Manual U11302EJ4V0UM

(2) Pull-up resistor option register (PUO)

The PUO register enables or disables the on-chip pull-up resistor for each port pin. To enable the on-chip pullup resistor of a port pin, the pin must be in the input mode and the corresponding bit in the PUO register must

be set to 1. For any pin specified as output mode or used as an analog input pin, the on-chip pull-up resistors

cannot be used, regardless of the PUO register setting. PUO is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Cautions 1. The P00 and P04 pins do not incorporate a pull-up resistor.

2. When port 1 is used as analog input for the A/D converter, an on-chip pull-up resistor cannot

be used even if 1 is set in PUO1.

Figure 4-15. Format of Pull-up Resistor Option Register

PUO 0

PUOm

Pm on-chip pull-up resistor selection (m = 0, 1, 2, 3)

On-chip pull-up resistor not used

On-chip pull-up resistor used

FFF7H 00H R/W

Symbol

7654

<3> <2> <0>

<1>

0 0 0 PUO3 PUO2 PUO1 PUO0

Address After reset R/W

CHAPTER 4 PORT FUNCTIONS

User’s Manual U11302EJ4V0UM

4.4 Port Function Operations

Port operations differ depending on whether the input or output mode is set, as shown below.

4.4.1 Writing to I/O port

(1) Output mode

A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

Once data is written to the output latch, it is retained until data is written to the output latch again.

(2) Input mode

A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status

does not change. Once data is written to the output latch, it is retained until data is written to the output latch again.

Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated,

the port is accessed in 8-bit units. Therefore, on a port with a mixture of input and output

pins, the output latch contents for pins specified as input are undefined except for the

manipulated bit.

4.4.2 Reading from I/O port

(1) Output mode

The output latch contents are read by a transfer instruction. The output latch contents do not change.

(2) Input mode

The pin status is read by a transfer instruction. The output latch contents do not change.

4.4.3 Operations on I/O port

(1) Output mode

An operation is performed on the output latch contents, and the result is written to the output latch. The output

latch contents are output from the pins.

Once data is written to the output latch, it is retained until data is written to the output latch again.

(2) Input mode

The output latch contents become undefined. However, the pin status does not change because the output buffer is turned off.

Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated,

the port is accessed in 8-bit units. Therefore, on a port with a mixture of input and output

pins, the output latch contents for pins specified as input are undefined except for the

manipulated bit.

CHAPTER 4 PORT FUNCTIONS

User’s Manual U11302EJ4V0UM

4.5 Selection of Mask Option

The following mask option is provided in mask ROM versions. The µPD78P0208 has no mask option.

Table 4-4. Comparison Between Mask Option of Mask ROM Version and

PD78P0208

Pin Name Mask Option of Mask ROM Version

PD78P0208

Can incorporate pull-down resistors in 1-bit units.

Can incorporate pull-up resistors in 1-bit units.

Can incorporate pull-down resistors in 1-bit units.

Can incorporate pull-down resistors in 1-bit units. The pull-down resistors can be specified to be connected to VLOAD or VSS in 4-bit units from P80.

Does not incorporate pull-down resistors.

Does not incorporate pull-up resistors.

Incorporates pull-down resistors (connected to VLOAD).

Does not incorporate pull-down resistors.

P30/TO0 to P32/TO2, P33/ TI1, P34/TI2, P35/PCL, P36/ BUZ, P37

P70 to P74

FIP0 to FIP12

P80/FIP13 to P87/FIP20, P90/FIP21 to P97/FIP28, P100/FIP29 to P107/FIP36, P110/FIP37 to P117/FIP44, P120/FIP45 to P127/FIP52

100

User’s Manual U11302EJ4V0UM

CHAPTER 5 CLOCK GENERATOR

5.1 Clock Generator Functions

The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two

types of system clock oscillators are available.

(1) Main system clock oscillator

This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).

(2) Subsystem clock oscillator

The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock

oscillator is not used, the internal feedback resistor can be disabled by the processor clock control register

(PCC). This decreases the power consumption in the STOP mode. The noise eliminator operates automatically to reduce the effect of switching noise during VFD display.

5.2 Clock Generator Configuration

The clock generator consists of the following hardware.

Table 5-1. Clock Generator Configuration

Item Configuration

Control registers Processor clock control register (PCC)

Display mode register 0 (DSPM0) Display mode register 1 (DSPM1)

Oscillator Main system clock oscillator

Subsystem clock oscillator

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