NEC mPD75512 Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD75512

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

The µPD75512 is a 4-bit single-chip microcomputer which employs 75X series architecture, and its perform-

ance is comparable to that of an 8-bit microcomputer.

µ

In addition to its high-speed processing capabilities, the
of 1, 4, or in 8-bits. With its internally provided A/D converter and serial interface, the
highest performance in its class.

Detailed functions are described in the following user‘s manual. Be sure to read it for designing.

µ

PD75516 User‘s Maual: IEM-5049

PD75512 is also capable of processing data in units

µ

PD75512 provides the

FEATURES

• Adequate I/O lines: 64

(can be provided pull-up/pull-down resistors: 47)

• Built-in 8-bit serial interface: 2-ch

NEC standard serial bus interface (SBI) internally provided

• Built-in 8-bit A/D converter: 8-ch

• Variable instruction execution time function which is convenient for high-speed operation and power saving

µ

· 0.95

· 122

• Program memory (ROM) size: 12,160 × 8 bits

• Data memory (RAM) size: 512 × 4 bits

• High-performance timer function: 4-ch

· 8-bit timer/event counter

· Clock timer

· 8-bit basic interval timer

· Timer/pulse generator: Capable of outputting 14-bit PWM

• Clock operation for reduced power consumption possible

(5

• PROM version (

APPLICATIONS

VCRs, CD players, telephones, cameras, etc.

s/1.95 µs/15.3 µs (at 4.19 MHz operation),

µ

s (at 32.768 kHz operation)

µ

A TYP. at 3 V operation)

µ

PD75P516) available

The information in this document is subject to change without notice.

Document No. IC-2569D

(O. D. No. IC-7833E)
Date Published November 1993 P
Printed in Japan

The mark ★ shows major revised points.

 NEC Corporation 1990

µ

PD75512

ORDERING INFORMATION

Part Number Package Quality Grade

µ

PD75512GF-xxx-3B9 80-pin plastic QFP Standard

(14 × 20mm)

Remarks: xxx is ROM code number.

Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC

Corporation to know the specification of quality grade on the devices and its recommended applications.

µ

PD75512 FUNCTIONS

Item Function

Internal ROM 12160 × 8 bits
Memory
Size RAM 512 × 4 bits

Genearl-Purpose Register (4 bits × 8 or 8 bits × 4) × 4 banks

Instruction Cycle • 0.95 µs/1.91 µs/15.3 µs (Main system clock: at 4.19 MHz)

Total 64 lines

CMOS Inputs 16 lines (also serve as INT, SIO, PPO, analog input; can be pulled up by software: 7

Input/
Output CMOS 28 lines (capable of driving LED: 4 lines)
Ports Input/Outputs • Can be pulled up by software: 16 lines

N-ch Open-Drain 20 lines (capable of driving LED: 8 lines; 10 V withstand voltage; pins that can be
Input/Outputs pulled up by mask option: 20)

A/D Converter 8-bit resolution × 8 channels (successive approxmation type)

Timer/Counter 4 channels

Serial Interface 2 channels

Vector Interrupt External: 3, Internal: 4

Test Input External: 1, Internal: 1

Instruction Set • 4-bit data transfer/operation/increment/decrement /compare instructions

• 122 µs (Subsystem clock: at 32.768 kHz)

lines)

• Can be pulled down by mask option: 4 lines

• Operation voltage: VDD = 3.5 to 6.0 V

• Timer/event counter



• Basic interval timer



• Timer/pulse generator (capable of outputting 14-bit PWM)



• Watch timer



• NEC standard serial bus interface (SBI)/3-line SIO: 1 channel




• Normal clock synchronized serial interface (3-line SIO): 1 channel

• Bit data set/reset/test/boolean operation instruction

• 8-bit data transfer/operation/increment/decrement /compare instructions

System Clock Generator

Operation Voltage VDD = 2.7 V to 6.0 V
Package 80-pin plastic QFP (14 × 20mm)

• Ceramic/crystal oscillator for main system clock: 4.19 MHz

• Crystal oscillator for subsystem clock: 32.768 kHz

2

µ

PD75512

CONTENTS

1. PIN CONFIGURATION ..................................................................................................................... 5

2. TYPICAL SYSTEM CONFIGURATION ............................................................................................ 6

3. INTERNAL BLOCKDIAGRAM .......................................................................................................... 7

4. PIN FUNCTIONS .............................................................................................................................. 8

4.1 PORT PINS ............................................................................................................................................. 8

4.2 NON-PORT PINS ................................................................................................................................... 10

4.3 PIN INPUT/OUTPUT CIRCUITS ............................................................................................................ 11

4.4 RECOMMENDED CONDITIONS FOR UNUSED PINS.......................................................................... 14

4.5 MASK OPTION SELECTION ................................................................................................................. 15

5. MEMORY CONFIGURATION .......................................................................................................... 16

6. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 19

6.1 PORT ...................................................................................................................................................... 19

6.2 CLOCK GENERATOR CIRCUIT ............................................................................................................. 20

6.3 CLOCK OUTPUT CIRCUIT..................................................................................................................... 21

6.4 BASIC INTERVAL TIMER ...................................................................................................................... 22

6.5 WATCH TIMER ...................................................................................................................................... 23

6.6 TIMER/EVENT COUNTER ..................................................................................................................... 23

6.7 TIMER/PULSE GENERATOR................................................................................................................. 25

6.8 SERIAL INTERFACE............................................................................................................................... 26

6.9 A/D CONVERTER ................................................................................................................................... 30

6.10 BIT SEQUENTIAL BUFFER ................................................................................................................... 31

7. INTERRUPT FUNCTIONS ................................................................................................................ 31

8. STANDBY FUNCTIONS ................................................................................................................... 33

9. RESET FUNCTION ........................................................................................................................... 34

10. INSTRUCTION SET .......................................................................................................................... 36

11. ELECTRICAL SPECIFICATIONS....................................................................................................... 44

12. PERFORMANCE CURVES ............................................................................................................... 57

3

µ

PD75512

13. PACKAGE DRAWINGS .................................................................................................................... 63

14. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 64

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 65

APPENDIX B. RELATED DOCUMENTS ................................................................................................ 66

4

1. PIN CONFIGURATION

AN0

AV

REF

V

DD

*

V

DD

P113
P112
P111
P110
P103
P102
P101
P100

P93
P92
P91
P90

SI1/P83

SO1/P82

SCK1/P81

PPO/P80

KR7/P73
KR6/P72

KR5/P71
KR4/P70

1
2

3

4
5

6
7
8

9
10
11

12
13
14
15
16
17
18

19

20

21
22

23

24

80

25 26

SS

AN2

AN4/P150

AN3

AN5/P151

AN6/P152

AN7/P153

AV

P120

P121

P122

P123

P130

P131

AN1

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

µ

PD75512GF– –3B9×××

27 28 29 30 31 32 33 34 35 36 37 38 39

P132

40

P133

64
63
62
61
60
59
58
57
56
55
54
53
52

51
50
49

48
47
46

45
44
43
42
41

µ

P140
P141
P142
P143
RESET

X2
X1

IC
XT2
XT1

SS

V

P00/INT4
P01/SCK0

P02/SO0/SB0

P03/SI0/SB1
P10/INT0

P11/INT1
P12/INT2
P13/TI0

P20/PTO0
P21
P22/PCL

P23/BUZ

P30

PD75512

KR3/P63

*: Power must be supplied to both VDD pins.

P52

P51

P50

P53

KR1/P61

KR2/P62

KR0/P60

IC: Internally Connected (Connect directly to VSS)

P43

P42

P41

P40

P33

SS

V

P32

P31

5

2. TYPICAL SYSTEM CONFIGURATION

VTR (Voltage synthesizer tuner)

µ

PD75512

µ

PD75512

Mechanism

Remote control

IC

Servo IC

Key matrix

Mechanism

control

INT0

Input port

Mechanical

Output

port

Port4, 5

KR0-KR7

System clock

controller/

Timer

Clock for clock

SIO

Analog

input

PPO

SIO

OSD

LPF

FIP driver

Tuner

FIP

6

µ

PD75512

7

3. INTERNAL BLOCKDIAGRAM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

PORT 8

PORT 9

PORT10

PORT11

PORT12

PORT13

PORT14

PORT15

44P10-P13

P00-P03

4 P20-P23

4

4 P30-P33

4 P40-P43*

4 P50-P53*

4 P60-P63

4 P70-P73

P80-P83

4 P90-P93

4 P100-P103

4 P110-P113

4 P120-P123*

4 P130-P133*

4 P140-P143*

P150-P153

4

SP (8)

BANK

GENERAL REG.

CY

ALU

PROGRAM
COUNTER (14)

ROM

PROGRAM

MEMORY

12160 × 8 BITS

DECODE

AND

CONTROL

RAM

DATA MEMORY

512 x 4 BITS

TI0/P13

TIMER/EVENT

COUNTER

#0

INTT0

PTO0/P20

BUZ/P23

WATCH
TIMER

INTW

INTCSI

SERIAL

INTERFACE0

SI0/SB1/P03

SO0/SB0/P02

SCK0/P01

INT0/P10
INT1/P11
INT2/P12
INT4/P00

KR0/P60
–KR7/P73

8

INTERRUPT
CONTROL

BIT SEQ.

BUFFER (16)

BASIC
INTERVAL
TIMER

INTBT

PPO/P80

TIMER/PULSE
GENERATOR

INTTPG

SERIAL

INTERFACE1

SI1/P83

SO1/P82

SCK1/P81

A/D

CONVERTER

AV

REF

AV

SS

AN0-AN3

AN4

/P150-AN7/P15

f /2

X

N

VDDV

SS

RESET

PCL/P22 XT1 XT2 X1 X2

SUB MAIN

CLOCK
OUTPUT
CONTROL

CLOCK
DIVIDER

CLOCK
GENERATOR

STAND BY
CONTROL

CPU CLOCK

4

Φ

*: PORTs 4, 5, and 12 to 14 are 10 V middle voltage, N-ch open-drain input/output ports.

4. PIN FUNCTIONS

4.1 PORT PINS (1/2)

µ

PD75512

Pin Input/ Shared Function 8-bit When Reset Output

Input/

Name Output Pin I/O Circuit

Type*

P00 INT4 4-bit input port (PORT0). B

For P01 to P03, built-in pull-up

P01 SCK0 resistors can be specified in 3-bit F -A

Input units by software. x Input

P02 SO0/SB0 F -B

P03 SI0/SB1 M -C

P10 INT0 With noise

elimination function

P11 INT1

Input 4-bit input port (PORT1). x Input B -C

P12 INT2 Built-in pull-up resistors can be

specified by software in 4-bit units.

P13 TI0

P20 PTO0

4-bit input/output port (PORT2).

P21 Input/ — Built-in pull-up resistors can be

output specified by software in 4-bit units. x Input E-B

P22 PCL

P23 BUZ

2

P30*

P31*

P32*

P33*

2

Input/ — Input/output can be specified in
output bit units. x Input E-C

2

2

— Programmable 4-bit input/output

port (PORT3).

— Built-in pull-up resistors can be

specified by software in 4-bit unit.

—

1

N-ch open-drain 4-bit input/output High level
port (PORT4). (when pull-up

P40 to Input/ — A pull-up resistor can be provided resistor is M

2

P43*

output in bit units (mask option). provided) or

10V withstanding voltage in the high impedance
open-drain mode.

O
N-ch open-drain 4-bit input/output High level
port (PORT5). (when pull-up

P50 to Input/ — A pull-up resistor can be provided resistor is M

2

P53*

output in bit units (mask option). provided) or

10V withstanding voltage in the high impedance
open-drain mode.

P60 KR0 Programmable 4-bit input/ output

port (PORT6).

P61 Input/ KR1 Input/output can be specified in

output bit units. O Input F -C

P62 KR2 Built-in pull-up resistors can be

specified by software in 4-bit units.

P63 KR3

*1: The number enclosed with a circle indicates Schmitt trigger input.
*2: Capable of direct driving on LED.

8

4.1 PORT PINS (2/2)

µ

PD75512

Pin Input/ Shared Function 8-bit When Reset Output

Input/

Name Output Pin I/O Circuit

Type*

P70 KR4

4-bit input/output port (PORT7).

P71 Input/ KR5 Built-in pull-up resistor can be

output specified in 4-bit units by software. O Input F-A

P72 KR6

P73 KR7

P80 PPO E

P81 SCK1 F

Input 4-bit input port (PORT8). x Input

P82 SO1 E

P83 SI1 B

Low level

4-bit input/output port (PORT9). (when pull­P90 to Input/ — Built-in pull-up resistors can be x down resistor V
P93 output specified in bit units by mask is provided)

option. or high

impedance

P100 to Input/ — 4-bit input/output port (PORT10). Input E
P103 output

x
P110 to Input/ — 4-bit input/output port (PORT11). Input E
P113 output

1

N-ch open-drain 4-bit input/output High level

P120 to Input/ — A pull-up resistor can be provided resistor is M
P123 output in bit units (mask option). x provided) or

P130 to Input/ — A pull-up resistor can be provided x resistor is M
P133 output in bit units (mask option). provided) or

P140 to Input/ — A pull-up resistor can be provided x resistor is M
P143 output in bit units (mask option). provided) or

P150 to Input AN4 to AN7 4-bit input port (PORT15). x Input Y-A
P153

port (PORT12). (when pull-up

10V withstanding voltage in the high impedance
open-drain mode.

N-ch open-drain 4-bit input/output High level
port (PORT13). (when pull-up

10V withstanding voltage in the high impedance
open-drain mode.

N-ch open-drain 4-bit input/output High level
port (PORT14). (when pull-up

10V withstanding voltage in the high impedance
open-drain mode.

*1: The number enclosed with a circle indicates Schmitt trigger input.

9

4.2 NON-PORT PINS

µ

PD75512

Pin Input/ Shared Function When Reset Output
Name Output Pin Circuit

TI0 Input P13 The external event pulse input pin for the timer/ — B -C

event counter.

PTO0 Output P20 Timer/event counter output pin Input E-B

PCL Output P22 Clock output pin Input E-B

BUZ Output P23 Fixed frequency output pin (for buzzer output or Input E-B

system clock trimming)

SCK0 Input/ P01 Serial clock input/output pin output Input F -A

output

SO0/SB0 Input/ P02 Serial data output pin Input F -B

output Serial bus input/output pin

SI0/SB1 Input/ P03 Serial data input pin Input M -C

output Serial bus input/output pin

INT4 Input P00 Edge detection vector interrupt input pin (both — B

rising edge and falling edge detection)

INT0 P10 Edge detection vector Synchronized

interrupt input pin with clock

Input (detection edge selectable) — B -C

INT1 P11 Asynchronous

INT2 Input P12 Edge detection testable input Asynchronous — B -C

pin(rising edge detection)

Input/

Type*

KR0-KR3 Input P60-P63 Parallel falling edge detection testable input pin Input F -C

KR4-KR7 Input P70-P73 Parallel falling edge detection testable input pin Input F -A

SCK1 Input/ P81 Serial clock input/output pin Input F

SO1 Output P82 Serial data output pin Input E

SI1 Input P83 Serial data input pin Input B

AN0-AN3 — Y

AN4-AN7 P150-P153 Y-A

AVREF Input — A/C converter reference voltage input pin — Z

AVSS — — A/D converter reference ground pin — —

X1, X2 Input — inputting the external clock, input the external — —

XT1 Input Pins for connecting the crystal oscillator to the

XT2 —

RESET Input — System reset input pin — B

PPO Output P80 Timer/pulse generator pulse output pin Input E

output

Input A/D converter analog input pin —

Pins for connecting the crystal ceramic oscillator
to the main system clock generator. When

clock to pin X1, and the reverse phase of the
external clock to pin X2.

— subsystem clock generator. When the external — —

clock is used, inputs the external clock to pin
XT1. In this case, pin XT2 must be left open.

IC — — Internally Connected. Connect directly to VSS.——

VDD — — Positive power supply pin — —

VSS — — GND — —

*: The number enclosed with a circle indicates Schmidt trigger input.

10

4.3 PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the

µ

PD75512.

µ

PD75512

TYPE A

DD

V

P–ch

IN

N–ch

Input buffer of CMOS standard

TYPE B

IN

TYPE D

VDD

data

output
disable

Push-pull output that can be set in a output
high-impedance state (both P-ch and N-ch are off)

P–ch

N–ch

TYPE E

data

Type D

output
disable

IN/OUT

OUT

Schmitt trigger input with hysteresis characteristics

TYPE B–C

DD

V

P.U.R.

P–ch

IN

P.U.R. : Pull-Up Resistor

Schmitt trigger input with hysteresis characteristics

P.U.R.
enable

Type A

This input/output circuit consists of D-type push-pull
outputs and Type A input buffers.

TYPE E

–

B

P.U.R.
enable

data

Type D

output
disable

Type A

P.U.R. : Pull-Up Resistor

V

DD

P.U.R.

P–ch

IN/OUT

Fig. 4-1 Pin Input/Output Circuits (1/3)

11

µ

PD75512

Type E-C

V

DD

Type F-B

P.U.R.

P.U.R.
enable

P–ch

output
disable

(P-ch)

data

Type D

output
disable

IN/OUT

data

output
disable
output

Type A

disable

(N-ch)

P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor

Type F Type F-C

data

Type D

output
disable

Type B

IN/OUT

P.U.R.
enable

data

output
disable

P.U.R.
enable

Type D

V

Type B

DD

P-ch

N-ch

V

DD

V

DD

P.U.R.

P–ch

IN/OUT

P.U.R.

P–ch

IN/OUT

This input/output circuit consists of D-type push-pull
outputs and Type B Schmitt trigger inputs.

V

Type F-A Type M

DD

P.U.R.

P.U.R.
enable

data

Type D

output
disable

Type A

P–ch

IN/OUT

data

output
disable

P.U.R. : Pull-Up Resistor

Fig. 4-1 Pin Input/Output Circuits (2/3)

Type B

P.U.R. : Pull-Up Resistor

V

DD

P.U.R.

(Mask Option)

N-ch

(can withstand
up to +10 V)

Middle-voltage input buffer
(can withstand up to +10 V)

P.U.R. : Pull-Up Resistor

IN/OUT

12

µ

PD75512

Type M-C

data

output
disable

P.U.R.
enable

N-ch

P.U.R. : Pull-Up Resistor

V

DD

P.U.R.

P–ch

IN/OUT

Type Y-A

IN

V DD

Type V Type Z

AV

data

output
disable

Type D

IN/OUT

REF

P–ch
N–ch

AV

SS

input
enable

Sampling

C

Reference voltage
(from a voltage tap of series
resistor string)

IN instruction

V DD

+

–

AVSS

IN

Type Y

V DD

P.U.R. : Pull-Up Resistor

P–ch
N–ch

Sampling

AV

SS

Input
enable

Type A

P.D.R
(Mask Option)

V DD

+

–

C

AVSS
Reference voltage
(from a voltage tap of series
resistor string)

AV

Reference voltage

SS

Fig. 4-1 Pin Input/Output Circuits (3/3)

13

4.4 RECOMMENDED CONDITIONS FOR UNUSED PINS

Table 4-1 Recommended Conditions for Unused Pins

Pin Recommended Conditions

P00/INT4 Connect to VSS

SCK0

P01/

P02/SO0/SB0 Connect to VSS or VDD

P03/SI1/SB1

µ

PD75512

P10/INT0-P12/INT2

P13/TI0

P20/PTO0

P21

P22/PCL

P23/BUZ

P30-P33

P40-P43

P50-P53

P60/KR0-P63/KR3

P70/KR4-P73/KR7

P80/PPO

SCK1

P81/

P82/SO1

P83/SI1

P90-P93

Connect to VSS

Input state: Connect to VSS or VDD

Output state: Open

Connect to VSS or VDD

P100-P103

P110-P113 Input state: Connect to VSS or VDD

P120-P123 Output state: Open

P130-P133

P140-P143

P150/AN4-P153/AN7

AN0-AN3

XT1 Connect to VSS or VDD

XT2 Open

AVREF

AVSS Connect to VSS

IC

14

Connect to VSS

4.5 MASK OPTION SELECTION

The following mask options are provided with the pins.

(1) Pull-up/pull-down resistor selection

Table 4-2 Pull-up/Pull-down Resistor Selection

Pins Mask Option

P40-P43 (1) With pull-up resistor (2) Without pull-up resistor
P50-P53 (Can be specified in bit units) (Can be specified in bit units)
P120-P123
P130-P133
P140-P143

P90-P93 (1) With pull-down resistor (2) Without pull-down resistor

(Can be specified in bit units) (Can be specified in bit units)

µ

PD75512

(2) Feedback resistor selection for the subsystem clock oscillation

Table 4-3 Feedback Resistor Selection

Pins Mask Option

XT1, XT2 (1) With feedback resistor (2) Without feedback resistor

Note: The operation is not affected if the feedback resistor is selected when the subsystem

clock is not used. However, the supply current I

(When the subsystem clock (When the subsystem clock
is used) is not used)

DD is increased.

15

µ

5. MEMORY CONFIGURATION

• Program memory (ROM) ... 12160 words × 8 bits (0000H-2F7FH)

• 0000H, 0001H : Vector table to which address from which program is started is written after reset

• 0002H-000DH : Vector table to which address from which program is started is written after interrupt

• 0020H-007FH : Table area referenced by GETI instruction

• Data memory

• Data area .... 512 words × 4 bits (000H–1FFH)

• Peripheral hardware area .... 128 words × 4 bits (F80H–FFFH)

PD75512

16

Address

0000H

0002H

76

MBE

RBE

MBE

RBE

Internal reset start address (upper 6 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 6 bits)

INTBT/INT4 start address (lower 8 bits)

µ

PD75512

0

0004H

0006H

0008H

000AH

0020H

007FH
0080H

007FH
0800H

MBE

MBE

MBE

MBE

MBE

RBE

RBE

RBE

RBE

RBE

INT0 start address (upper 6 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 6 bits)

INT1 start address (lower 8 bits)

INTCSIO0 start address (upper 6 bits)

INTCSIO0 start address (lower 8 bits)

INTT0 start address (upper 6 bits)

INTT0 start address (lower 8 bits)

INTTPG start address (upper 6 bits)000CH

INTTPG start address (lower 8 bits)

GETI instruction reference table

CALLF

!faddr

instruction

entry

address

instruction

BRCB

!caddr

branch

address

CALL !addr

instruction
subroutine

entry address

BR !addr

instruction

branch address

BR $addr

instruction

relational

branch address

(–15 to –1,
+2 to +16)

Branch destination

subroutine entry

GETI instruction

address and

address for

0FFFH
1000H

1FFFH
2000H

2F7FH

Remarks: In addition to the above, branching to an address, for which only the lower 8 bits of the PC are

modified, is possible by the BR PCDE and BR PCXA instructions.

BRCB
!caddr

instruction

branch

address

BRCB

!caddr

instruction

branch

address

Fig. 5-1 Program Memory Map

17

µ

PD75512

Data area
Static RAM
(512× 4)

Stack
area

General
purpose
register
area

000H

01FH
008H

0FFH
100H

1FFH

Data memory

(32 × 4)

256× 4

256× 4

Memory bank

0

1

Peripheral hardware area

Unmapped

F80H

128× 4

FFFH

Fig. 5-2 Data Memory Map

15

18

6. PERIPHERAL HARDWARE FUNCTIONS

6.1 PORT

I/O ports are classified into following kinds:

• CMOS input (PORTS 0, 1, 8, 15) : 16

• CMOS input/output (PORTS 2, 3, 6, 7, 9, 10, 11) : 28

• N-ch open-drain input/output (PORTS 4, 5, 12, 13, 14) : 20
Total : 64

Table 6-1 Port Functions

µ

PD75512

Port

(Pin Name)

PORT0

PORT1

PORT2

PORT3*

PORT4*

PORT5*

PORT6

PORT7

PORT8

PORT9 4-bit I/O Can be specified for I/O in 4-bit units.

Function Operation/Feature Remarks

4-bit input mode of the shared pin.

4-bit I/O BUZ pins.

4-bit I/O Whether or not the internal
(N-ch Can be specifiedfor pull-up resistor is provided
open-drain, I/O in 4-bit units can be specified for each bit
can sustain by mask option
with 10V)

4-bit I/O be paired to I/O

4-bit Can be read or tested regardless of the operation Also serves as PPO,
input mode of the shared pin. SO1, and SI1 pins.

Can be read or tested regardless of the operation SO0/SB0, and SI0/SB1 pins

Can be specified for I/O in 4-bit units Also serves as PTO0, PCL and

Can be specified for I/O in 1/4-bit units. —

Ports 4 and 5 can
be paired to I/O
data in 8-bit units

Can be specified
for I/O in 1/4-bit units Ports 6 and 7 can Also serves as KR0-3.

Can be specified data in 8-bit units
I/O in 4-bit Also serves as KR4-7.
units

SCK1

SCK0

,

Also serves as the INT4,

Also serves as INT0 to 2, and
TIO pins

Whether or not the internal
pull-up resistor is provided
can be specified for each bit
by mask option.

,

PORT10

4-bit I/O Can be specified for I/O in 4-bit units. —

PORT11

PORT12 4-bit I/O Whether or not the internal

(N-ch pull-up resistor is provided

PORT13 open-drain, Can be specified for I/O in 4-bit units. can be specified for each

can sustain bit by mask option.

PORT14 with 10V)

PORT15 4-bit Can be read or tested regardless of the operation Also serves as AN4-7 pins.

Input mode of the shared pins

*: Can directly drive LED

19

µ

PD75512

6.2 CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and

system clock control register (SCC).

This circuit can generate two types of clocks: main system clock and subsystem clock.

In addition, it can also change the instruction execution time.

µ

• 0.95

• 122

s, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)

µ

s (subsystem clock: 32.768 kHz)

VDD

VDD

XT1

XT2

X1

X2

Subsystem

clock

oscillator

Main system

clock

oscillator

XT

f

fX

Watch timer

Timer/pulse
generator

1/2 1/16

· Basic interval timer (BT)

· Timer/event counter

· Serial interface

· Watch timer

· Clock output circuit

· A/D converter

· INT0 noise rejecter circuit

1/8 to 1/4096

Frequency divider

WM.3

SCC

SCC3

SCC0

PCC

4

HALT*

STOP*

PCC0

PCC1

PCC2

PCC3

PCC2, PCC3

clear signal

Internal bus

Oscillator

disable

signal

STOP F/F

QS

R

Selector

HALT F/F

S

R

Frequency

Selector

Q

Wait release
signal from BT

RESET signal
Standby release

signal from interrupt
control circuit

divider

1/4

Φ

· CPU

· INT0 noise
rejecter circuit

· Clock output
circuit

*: instruction execution.

Remarks 1: f

X = Main system clock frequency
XT = Subsystem clock frequency

2: f
3: Φ= CPU clock
4: PCC: Processor clock control register
5: SCC: System clock control register

★

6: One clock cycle (tCY) of Φ is one machine cycle of an instruction. For tCY, refer to AC

characteristics in 11. ELECTRICAL SPECIFICATIONS.

20

Fig. 6-1 Clock Generator Block Diagram

µ

PD75512

6.3 CLOCK OUTPUT CIRCUIT

The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote control

output, peripheral LSIs, etc.

• Clock output (PCL): Φ, 524, 262, 65.5 kHz (operating at 4.19 MHz)

• Buzzer output (BUZ): 2 kHz, (operating at 4.19 MHz, or 32.768 kHz)

From the

clock

generator

Φ

3

f

X

/2

4

fX/2

6

fX/2

CLOM3 CLOM2 CLOM1 CLOM0 CLOM

Selector

P22 output
latch

Output
buffer

Port 2 input/
output mode
specification
bit

PCL/P22

Bit 2 of PMGBPORT2.2

Remarks:

4

Internal bus

Fig. 6-2 Clock Output Circuit Configuration

A measures to prevent outputting narrow width pulse when selecting clock output enable/
disable is taken.

21

6.4 BASIC INTERVAL TIMER

µ

PD75512 is provided with the 8-bit basic interval timer. The basic interval timer has these functions:

The

• Interval timer operation which generates a reference time interrupt

• Watchdog timer application which detects a program runaway

• Selects the wait time for releasing the standby mode and counts the wait time

• Reads out the count value

From the
clock generator

5

fX/2

Clear

µ

PD75512

Clear

7

fX/2

MPX

9

fX/2

12

fX/2

3

BTM3 BTM2 BTM1 BTM0 BTM

SET1*

4

*: Instruction execution

Fig. 6-3 Basic Interval Timer Configuration

Basic interval timer

(8-bit frequency divider circuit)

8

Internal bus

Set
signal

BT

Wait release signal
for standby release

BT

interrupt

request flag

IRQBT

Vector
interrupt
request
signal

22

µ

PD75512

6.5 WATCH TIMER

µ

PD75512 has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4.

The

• Sets the test flag (IRQW) with 0.5 sec interval.

The standby mode can be released by IRQW.

• 0.5 second interval can be generated either from the main system clock or subsystem clock.

• Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient

for program debugging, test, etc.

• Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock

frequency trimming.

• The frequency divider circuit can be cleared so that zero second watch start is possible.

W

f

(256 Hz: 3.91 ms)

7

2

INTW
(IRQW
set signal)

P23/BUZ

From the
clock
generator

f

X

128

(32.768 kHz)

f

XT

(32.768 kHz)

f

Selector Frequency divider

W

(32.768
kHz)

f
16

W

(2.048
kHz)

Clear

f

W

14

2

(2 Hz

0.5 sec)

Selector

Output buffer

WM PORT2.3 Bit 2 of PMGB

WM70000WM2WM1WM0

Bit test

8

instruction

Internal bus

P23
output
latch

Port 2
input/output
mode

Remarks: ( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.

Fig. 6-4 Watch Timer Block Diagram

6.6 TIMER/EVENT COUNTER

The

µ

PD75512 has a built-in 1-ch timer/event counter. The timer/event counter has these functions:

• Programmable interval timer operation

• Outputs square-wave signal of an arbitrary frequency to the PTO0 pin.

• Event counter operation

• Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation).

• Supplies serial shift clock to the serial interface circuit.

• Count condition read out function

23

µ

PD75512

24

Internal bus

88 SET1*

TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00

TM0

PORT1.3

Input

buffer

P13/TI0

From the
clock
generator

MPX

*:Instruction execution

Timer operation start signal

CP

8

8

Modulo register (8)

Comparator (8)

Count register (8)

Clear

T0

TMOD0

Reset

TOE0 PORT2.0

Bit 2 of PGMB

To serial interface

P20/PTO0

INTT0
IRQT0
set signal

()

RESET
IRQT0

clear signal

Output
buffer

TOUT
F/F

TO
enable
flag

P20
output
latch

Port 2
input/
output
mode

Coinci­dence

8

Fig. 6-5 Timer/Event Counter Block Diagram

(Refer to Fig. 4-11.)

µ

PD75512

6.7 TIMER/PULSE GENERATOR

µ

PD75512 contains a timer/pulse generator, that can be used as the timer or the pulse generator. Timer/pulse

The

generator has the following functions.

(a) Function, when used in the timer mode

• 8-bit interval timer operation (IRQTPG generation), for which the clock source can be changed in 5
steps.

• Square waveform output to the PPO pin

(b) Function, when used in the PWM pulse generation mode

• 14-bit accuracy PWM pulse output to PPO pin (can be used as a D/A converter for electronics tuning).

15

• Fixed time interval interrupt generation (2

/fX = 7.81ms: fX = 4.19 MHz)

When no pulse output is required, the PPO pin can be used as 1-bit output port.

Note: When setting the STOP mode, if the timer pulse generator is in operating mode, erroneous operation

may occur. Therefore, the timer/pulse generator must be set in no-operation state by the mode
register, before setting the STOP mode.

TPGM3
(Set to1)

Frequency
divider

1/2

f

x

TPGM1

Internal bus

8

MODL

Modulo register L (8) Modulo register H (8)

CP

Prescaler select latch (5)

Clear

8

Modulo latch H (8)

8

Comparator (8)

8

Count register (8)

Clear

MODH

Coincidence

T F/F

Set

Selector

TPGM4 TPGM5 TPGM7

INTTPG
(IRQTPG
set signal)

Output buffer

PPO

Fig. 6-6 Timer/Pulse Generator Block Diagram (Timer Mode)

25

Internal bus

µ

PD75512

TPGM3

TPGM1
f

x

1/2

Frequency divider

Fig. 6-7 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode)

MODH

Modulo register H (8)

MODH(8) MODL (6)

Modulo latch (14)

PWM pulse generator

INTTPG TPGM5

IRQTPG set signal

Modulo register L (8)

15

2

( = 7.8 ms: f at 4.19MHz)

f

x

7-2

MODL

Output buffer

Selector

TPGM7

x

PPO

6.8 SERIAL INTERFACE

µ

PD75512 is provided with two serial interface channels. Table 4-8 indicates differences between channel

The

0 and channel 1.

Table 6-2 Differences Between Channel 0 and Channel 1

Serial Transfer Mode, Funciton Channel 0 Channel 1

Clock Selection fX/24, fX/23, TOUT F/F, external clock fX/24, fX/23 external clock

3-Line Transfer Method MSB first/LSB first selectable MSB first
Serial I/O

2-Line Serial I/O

Serial Bus Interface (SBI)

(1) Serial interface function (Channel 0)

Transfer Completion Serial transfer completion interrupt Serial transfer completion flag (EOT)
Flag request flag (IRQCSI0)

Usable Unprovided

µ

PD75512 is equipped with the following four modes:

The

• Operation stop mode

• Three-line serial I/O mode

• Two-line serial I/O mode

• SBI mode (serial bus interface mode)

26

µ

PD75512

27

Internal bus

8/4

8

88

P03/SI/SB1

P02/SO/SB0

P01/SCK0

P01
output
latch

Selector Selector

Bit
test

Slave address register

(SVA)

Address comparator

Shift register (SIO0)

SET CLR

Bit manipulation

(8)

(8)

Coincidence

signal

SBIC

RELT

CMDT

SO0 latch

Bit test

ACKT

ACKE

BSYE

Busy/
acknowledge
output
circuit

Bus release/
command/
acknowledge
detector
circuit

RELD
CMDD
ACKD

Serial clock
counter

Serial clock
control
circuit

INTCSI0
control
circuit

MPX

I

NTCSI0
IRQCSI0
set signal

(

)

DQ

f

X

/2

3

fX/2

4

fX/2

6

TOUT F/F
(from timer/
event counter)

External SCK0

(8)

Fig. 6-8 Serial Interface (Channel 0) Block Diagram

CSIM0

(2) Serial interface (Channel 1) configuration

µ

PD75512 serial interface (channel 1) has following two modes.

• Operation stop mode

• 3-line serial I/O mode

µ

PD75512

28

µ

PD75512

29

Fig. 6-9 Serial Interface (Channel 1) Block Diagram

Bit
manipulation

0

CSIM1

Clear

Set

Serial transfer
completion flag
(EOT)

f /2

x

3

f /2

x

4

MPX

8

Bit
manipulation

bit 7

Serial operation mode (8)
register 1 (8)

Internal bus

8

SIO1 write signal (serial start signal)

SIO1

7bit 0

Shift register 1 (8)

P83/SI1

P82/SO1

P81/SCK1

Serial clock
counter (3)

Overflow

Clear

QRS

6.9 A/D CONVERTER

µ

PD75512 is provided with an 8-bit resolution analog-to-digital (A/D) converter with eight channels of

The

analog inputs (AN0-AN7).

This A/D converter is of a successive approximation type.

8

Internal bus

µ

PD75512

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AV

REF

0

ADM6 ADM5 ADM4 SOC EOC

Sample hold circuit

Multiplexer

Tap decoder

R/2 R/2RR R

ADM1 0 ADM

Control circuit

+

–

Comparator

8

SA register (8)

8

AV

SS

Fig. 6-10 Block Diagram of A/D Converter

30

µ

PD75512

6.10 BIT SEQUENTIAL BUFFER ..... 16 BITS

The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this
buffer is very useful for processing long data in bit units.

Address bit

Symbol

L register

Remarks:

L = F L = C L = B L = 8 L = 7 L = 4 L = 3 L = 0

For the pmem.@L addressing, the specification bit is shifted according to the L register.

FC3H FC2H FC1H FC0H

3210321032103210

BSB3 BSB2 BSB1 BSB0

DECS L

INCS L

Fig. 6-11 Bit Sequential Buffer Format

7. INTERRUPT FUNCTIONS

The µPD75512 has 7 different interrupt sources and multiplexed interrupt with priority order.

µ

In addition to that, the
of edge detection testable inputs.

The interrupt control circuit of the µPD75512 has these functions:

• Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by

using the interrupt flag (IExxx) and interrupt master enable flag (IME).

• The interrupt start address can be arbitrarily set.

• Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of

software).

• Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).

PD75512 is also provided with two types of test sources, of which INT2 has two types

31

µ

PD75512

32

Internal bus

222

IM2 IM1 IM0

IRQBT

INT4
/P00

INT0
/P10

INT1
/P11

INT2
/P12

KR0/P60

KR7/P73

Noise

elimination

circuit

INT
BT

INTCSI0

INTT0

INTTPG

Selector

Both edge

detection

circuit

Edge

detection

circuit

Edge

detection

circuit

Rising edge

detection

circuit

Falling edge

detection

circuit

IRQ4

IRQ0

IRQ1

IRQCSI0

IRQT0

IRQTPG

IM2

Interrupt enable flag (IExxx)

(IME)

VRQn

Decoder

IST

Priority control

circuit

Vector table

address

generator

Standby
release signal

Fig. 7-1 Interrupt Control Block Diagram

IRQ2

INTW

IRQW

4

2

IPS

µ

PD75512

8. STANDBY FUNCTIONS

In order to fully exploit the µPD75512 low power dissipation, CPU operation can be stopped by setting the unit

µ

to the standby mode, thus, further reducing power dissipation. The

PD75512 features two standby modes, a STOP

mode and a HALT mode.

Table 8-1 Status in Standby Mode

Item
Instruction for Setting STOP instrtuction HALT instruction
System Clock at the Time of

Setting

Clock Oscillator Only the main system clock can stop

Basic Interval
Timer

Serial Interface
(Channel 0)

Serial Interface
(Channel 1)

Operation
Status

Timer/Event
Counter

Clock Timer Operates when fXT is selected as the

A/D Converter Does not operate

Timer/Pulse
Generator

Timer/Pulse
Generator

Mode

Can be set only when operating on
the main system clock

its operation.
Does not operate Operates (Sets IRQBT with the

Can operate only when the external
SCK0 input is selected as the serial
clock

Can operate only when the external
SCK1 input is selected as the serial
clock

Can only operate when the TI0 pin
input is selected as system clock

count clock

Does not operate

STOP Mode

Can be set when operating either on
the main system clock or the subsys­tem clock

Only the CPU clock Φ stops its
operation. (oscillation continues)

reference time interval)
Operates when the timer system

clock is operating or external SCK0 is
selected

Operates only when the main system
clock is operating

Operates only when the main system
clock is operating

Can operate

Operates only when the main system
clock is operating

Operates only when the main system
clock is operating

INT1, INT2, and INT4 can operate, but INT0 cannot operate

HALT Mode

CPU Does not operate

Release Signal

An interrupt request signal from a piece of hardware, whose operation is
enabled by the interrupt enable flag, or the RESET signal input

33

9. RESET FUNCTION

µ

PD75512

When the

RESET

signal is input, the µPD75512 is reset and each hardware is initialized as indicated in Table

9-1. Fig. 9-1 shows the reset operation timing.

Wait

(31.3ms/4.19MHz)

RESET input

Operation mode
or standby mode

Internal reset operation

HALT mode Operation mode

Fig. 9-1 Reset Operation by RESET Input

Table 9-1 Status of Each Hardware after Reset (1/2)

Hardware RESET Input in Standby Mode RESET Input during Operation

Program Counter (PC) The contents of the lower 6 bits

PSW Carry Flag (CY) Retained Undefined

Skip Flag (SK0-2) 0 0
Interrupt Status Flag (IST0, 1) 0 0
Bank Enable Flag (MBE, RBE) The contents of bit 6 of address

Stack Pointer (SP) Undefined Undefined
Data Memory (RAM) Retained * Undefined

General-Purpose Register
(X, A, H, L, D, E, B, C)

Bank Selection Register (MBS, RBS) 0, 0 0, 0
Basic Interval

Timer

Timer/Event
Counter

Timer/Pulse
Generator

Watch Timer

Counter (BT) Undefined Undefined

Mode Register (BTM) 0 0

Counter (T0) 0 0
Modulo Register

(TMOD0)
Mode Register (TM0) 0 0

TOE0, TOUT F/F 0, 0 0, 0

Modulo Register

Mode Register (WM) 0

of address 0000H of the program
memory are set to PC13-8, and
the contents of address 0001H
are set to PC7-0.

0000H of the program memory
are set to RBE and those of bit 7
are set to MBE.

Retained Undefined

FFH

Retained

0

Same as left

Same as left

FFH

Retained

0Mode Register 0

*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a

34

RESET

signal is input.

Table 9-1 Status of Each Hardware after Reset (2/2)

Hardware RESET Input during OperationRESET Input in Standby Mode

Serial
Interface
(Channel 0)

A/D Converter Mode Regiseter (ADM), 04H (EOC = 1) 04H (EOC = 1)

Clock Processor Clock Control 0 0
Generator, Register (PCC)
Clock Output
Circuit

Serial Shift Register Retained Undefined
Interface (SIO1)
(Channel 1)

Interrupt Interrupt Request Flag Reset (0) Reset (0)
Function (IRQxxx)

Digital Port Output Buffer Off Off

Bit Sequential Buffer (BSB0-3) Retained Undefined

Shift Register (SIO0) Retained Undefined
Operation Mode 0 0

Register (CSIM0)
SBI Control Register 0 0

(SBIC)
Slave Address Register Retained Undefined

(SVA)
P01/SCK0 Output 1 1

Latch

EOC
SA Register 7FH 7FH

System Clock Control 0 0
Register (SCC)

Clock Output Mode 0 0
Register (CLOM)

Operation Mode 0 0
Register 1 (CSIM1)

Serial Transfer End 0 0
Flag (EOT)

Interrupt Enable Flag 0 0
(IExxx)

Interrupt Master Enable 0 0
Flag (IME)

INT0, INT1, INT2 Mode 0, 0, 0 0, 0, 0
Registers (IM0, 1, 2)

Output Latch Clear (0) Clear (0)
Input/Output Mode 0 0

Register (PMGA, B, C)
Pull-Up Resistor 0 0

Specification Register
(POGA)

µ

PD75512

35

µ

10. INSTRUCTION SET

(1) Operand representation and description

Describe one or more operands in the operand field of each instruction according to the operand
representation and description methods of the instruction (for details, refer to RA75X Assembler Package
User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from
several operands. The uppercase characters, +, and – are keywords and must be described as is.

Describe an appropriate numeric value or label as immediate data.

Representation Description

reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L

rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rp' XA, BC, DE, HL, XA', BC', DE', HL'
rp'1 BC, DE, HL, XA', BC', DE', HL'

rpa HL, HL+, HL–, DE, DL
rpa1 DE, DL

n4 4-bit immediate data or label
n8 8-bit immediate data or label

mem 8-bit immediate data or label*
bit 2-bit immediate data or label

fmem FB0H to FBFH,FF0H to FFFH immediate data or label
pmem FC0H to FFFH immediate data or label

addr 0000H to 1F7FH immediate data or label
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label

taddr 20H to 7FH immediate data (where bit0 = 0) or label
PORTn PORT0 to PORT15

IExxx IEBT, IECSI0, IET0, IE0, IE1, IE2, IE4, IEW, IETPG
RBn RB0-RB3
MBn MB0, MB1, MB15

PD75512

*: Only even addresses can be described in mem when processing

8-bit data.

36

(2) Legend of operation field

A : A register; 4-bit accumulator
B : B register; 4-bit accumulator
C : C register; 4-bit accumulator
D : D register; 4-bit accumulator
E : E register; 4-bit accumulator
H : H register; 4-bit accumulator
L : L register; 4-bit accumulator
X : X register; 4-bit accumulator
XA : Register pair (XA); 8-bit accumulator
BC : Register pair (BC); 8-bit accumulator
DE : Register pair (DE); 8-bit accumulator
HL : Register pair (HL); 8-bit accumulator
XA' : Expanded register pair (XA')
BC' : Expanded register pair (BC')

µ

PD75512

DE' : Expanded register pair (DE')
HL' : Expanded register pair (HL')
PC : Program counter
SP : Stack pointer
CY : Carry flag; or bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn : Port n (n = 0 to 15)
IME : Interrupt mask enable flag
IPS : Interrupt priority selector register
IExxx : Interrupt enable flag
RBS : Memory bank selector register
MBS : Memory bank selector register
PCC : Processor clock control register

.

(xx) : Contents addressed by xx
xxH : Hexadecimal data

: Delimiter of address and bit

37

(3) Symbols in addressing area field

µ

PD75512

*1 MB = MBE . MBS

*2 MB = 0
*3 MBE = 0 : MB = 0 (00H-7FH) Data memory

*4 MB = 15, fmem = FB0H-FBFH,

*5 MB = 15, pmem = FC0H-FFFH
*6 addr = 0000H-2F7FH
*7 addr = (Current PC) – 15 to (Current PC) – 1

*8 caddr = 0000H-0FFFH (PC13, 12 = 00B) or memory

*9 faddr = 0000H-07FFH

*10 taddr = 0020H-007FH

(MBS = 0, 1, 15)

MB = 15 (80H-FFH) addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

FF0H-FFFH

(Current PC) + 2 to (Current PC) + 16

1000H-1F7FH (PC13, 12 = 01B) or addressing
2000H-2F7FH (PC13, 12 = 10B)

Program

Remarks 1: MB indicates memory bank that can be accessed.

2: In *2, MB = 0 regardless of MBE and MBS.
3: In *4 and *5, MB = 15 regardless of MBE and MBS.
4: *6 to *10 indicate areas that can be addressed.

(4) Machine cycle field

In this field, S indicates the number of machine cycles required when an instruction having a skip

function skips. The value of S varies as follows:

• When no instruction is skipped ····························································· S = 0

• When 1-byte or 2-byte instruction is skipped······································ S = 1

• When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ······· S = 2

Note

: The GETI instruction is skipped in one machine cycle.

One machine cycle equals to one cycle of the CPU clock Φ, (=tCY), and can be changed in three steps

depending on the setting of the processor clock control register (PCC).

38

µ

PD75512

Ma- Ad­Instruc- Mne­tions monics Cyc- ing Conditions

Transfer MOV A, #n4 1 1 A ← n4 String effect A

XCH A, @HL 1 1 A ↔ (HL) *1

Table MOVT XA, @PCDE 1 3 XA ← (PC13-8+DE)ROM
Reference

Operand Bytes

reg1, #n4 2 2 reg1 ← n4
XA, #n8 2 2 XA ← n8 String effect A
HL, #n8 2 2 HL ← n8 String effect B
rp2, #n8 2 2 rp2 ← n8
A, @HL 1 1 A ← (HL) *1
A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L = 0
A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH
A, @rpa1 1 1 A ← (rpa1) *2
XA, @HL 2 2 XA ← (HL) *1
@HL, A 1 1 (HL) ← A*1
@HL, XA 2 2 (HL) ← XA *1
A,mem 2 2 A ← (mem) *3
XA, mem 2 2 XA ← (mem) *3
mem, A 2 2 (mem) ← A*3
mem, XA 2 2 (mem) ← XA *3
A, reg 2 2 A ← reg
XA, rp' 2 2 XA ← rp
reg1, A 2 2 reg1 ← A
rp'1, XA 2 2 rp1 ← XA

A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L = 0
A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH
A, @rpa1 1 1 A ↔ (rpa1) *2
XA, @HL 2 2 XA ↔ (HL) *1
A, mem 2 2 A ↔ (mem) *3
XA, mem 2 2 XA ↔ (mem) *3
A, reg1 1 1 A ↔ reg1
XA, rp' 2 2 XA ↔ rp'

XA, @PCXA 1 3 XA ← (PC13-8+XA)ROM

chine

les Area

Operation

dress- Skip

39

µ

PD75512

Instruc- Mne­tions monics Cyc- ing Conditions

Bit
Transfer

MOV1 bit

Arithme­tic
Opera­tion

ADDS A,@HL 1 1+S A ← A+(HL) *1 carry

ADDC XA,rp’ 2 2 XA,CY ← XA+rp’+CY

SUBS XA,rp’ 2 2+S XA ← XA-rp’ borrow

SUBC XA,rp’ 2 2 XA,CY ← XA-rp’-CY

AND A,@HL 1 1 A ← A ∧ (HL) *1

OR A,@HL 1 1 A ← A ∨ (HL) *1

XOR A,@HL 1 1 A ← A ∨ (HL) *1

Operand Bytes

CY, fmem.bit 2 2 CY ← (fmem.bit) *4
CY, pmem.@L 2 2 CY ← (pmem7-2+L3-2.bit(L1-0)) *5
CY, @H+mem. 2 2 CY ← (H+mem3-0.bit) *1

fmem.bit, CY 2 2 (fmem.bit) ← CY *4
pmem.@L, CY 2 2 (pmem7-2+L3-2.bit(L1-0)) ← CY *5
@H+mem.bit, 2 2 (H+mem3-0.bit) ← CY *1

CY
A,#n4 1 1+S A ← A+n4 carry
XA,#n8 2 2+S XA ← XA+n8 carry

XA,rp’ 2 2+S XA ← XA+rp’ carry
rp’1,XA 2 2+S rp’1 ← rp’1+XA carry
A,@HL 1 1 A,CY ← A+(HL)+CY *1

rp’1,XA 2 2 rp’1,CY ← rp’1+XA+CY
A,@HL 1 1+S A ← A-(HL) *1 borrow

rp’1,XA 2 2+S rp’1 ← rp’1-XA borrow
A,@HL 1 1 A,CY ← A-(HL)-CY *1

rp’1,XA 2 2 rp’1,CY ← rp’1-XA-CY
A,#n4 2 2 A ← A ∧ n4

XA,rp’ 2 2 XA ← XA-rp’
rp’1,XA 2 2 rp’1 ← rp’1 ∧ XA
A,#n4 2 2 A ← A ∨ n4

XA,rp’ 2 2 XA ← XA ∨ rp’
rp’1,XA 2 2 rp’1 ← rp’1 ∨ XA
A,#n4 2 2 A ← A ∨ n4

XA,rp’ 2 2 XA ← XA ∨ rp’
rp’1,XA 2 2 rp’1 ← rp’1 ∨ XA

Ma- Ad-

chine

les Area

Operation

dress- Skip

40

µ

PD75512

Ma- Ad-

Instruc- Mne­tions monics Cyc- ing Conditions

Accumu­lator
Manipu­lation

Incre- reg 1 1+S reg ← reg+1 reg = 0
ment/ INCS rp1 1 1+S rp1 ← rp1+1 rp1 = 00H
Decre- @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0
ment mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0

Compari- reg,#n4 2 2+S Skip if reg = n4 reg = n4
son @HL,#n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4

Carry
Flag
Manipu­lation

RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An

NOT A 2 2 A ←

DECS reg 1 1+S reg ← reg-1 reg = FH

SKE A,@HL 1 1+S Skip if A = (HL) *1 A = (HL)

SET1 CY 1 1 CY ← 1
CLR1 CY 1 1 CY ← 0
SKT CY 1 1+S Skip if CY = 1 CY = 1
NOT1 CY 1 1 CY ←

Operand Bytes

rp’ 2 2+S rp’ ← rp’-1 rp’ = FFH

XA,@HL 2 2+S Skip if XA = (HL) *1 XA = (HL)
A,reg 2 2+S Skip if A = reg A = reg
XA,rp’ 2 2+S Skip if XA = rp’ XA = rp’

chine

les Area

A

CY

Operation

dress- Skip

41

µ

PD75512

Instruc- Mne­tions monics Cyc- ing Conditions

Memory/ SET1 mem.bit 2 2 (mem.bit) ← 1 *3
Bit fmem.bit 2 2 (fmem.bit) ← 1 *4
Manipu- pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 1*5
lation @H+mem.bit 2 2 (H + mem3-0.bit) ← 1*1

CLR1 mem.bit 2 2 (mem.bit) ← 0*3

SKT mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1

SKF mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0

SKTCLR

AND1 CY,fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4

OR1 CY,fmem.bit 2 2 CY

XOR1 CY,fmem.bit 2 2 CY

Branch BR addr — — PC13-0 ← addr *6

BRCB !caddr 2 2 PC13-0 ← PC13,12+caddr11-0 *8

Operand Bytes

fmem.bit 2 2 (fmem.bit) ← 0*4
pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 0*5
@H+mem.bit 2 2 (H+mem3-0.bit) ← 0*1

fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1
pmem.@L 2 2+S
@H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 1 *1

fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0
pmem.@L 2 2+S
@H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 0 *1
fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1
pmem.@L 2 2+S Skip if (pmem7-2+L3-2.bit *5 (pmem.@L) = 1

@H+mem.bit 2 2+S

CY,pmem.@L 2 2
CY,@H+mem.bit

CY,pmem.@L 2 2
CY,@H+mem.bit

CY,pmem.@L 2 2
CY,@H+mem.bit

!addr 3 3 PC13-0 ← addr *6
$addr 1 2 PC13-0 ← addr *7

Ma- Ad-

chine

les Area

Skip if (pmem

Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0

(L1-0)) = 1 and clear

Skip if (H+mem3-0.bit) = 1 and clear

CY ← CY ∧ (pmem7-2+L3-2.bit(L1-0))

2 2 CY

CY ← CY ∨ (pmem7-2+L3-2.bit (L1-0))

2 2 CY

CY ← CY ∨ (pmem7-2+L3-2.bit (L1-0))

2 2 CY

(The most suitable instruction
is selectable from among BR
!addr, BRCB !caddr, and BR
$addr depending on the
assembler.)

Operation

7-2+L3-2

.bit (L

1-0

←

CY ∧ (H+mem3-0.bit) *1

←

CY ∨ (fmem.bit) *4

←

CY ∨ (H+mem3-0.bit) *1

←

CY ∨ (fmem.bit) *4

←

CY ∨ (H+mem3-0.bit) *1

)) = 1

dress- Skip

*5 (pmem.@L) = 1

(@H+mem.bit) = 1

*5 (pmem.@L) = 0

(@H+mem.bit) = 0

*1

*5

*5

*5

(@H+mem.bit) = 1

42

µ

PD75512

Instruc- Mne­tions monics Cyc- ing Conditions

Subrou­tine/
Stack
Control

Inter- EI 2 2 IME (IPS.3) ← 1
rupt IExxx 2 2 IExxx ← 1
Control DI 2 2 IME (IPS.3) ← 0

I/O IN *1A,PORTn 2 2 A ← PORTn (n = 0-15)

CPU HALT 2 2 Set HALT Mode (PCC.2 ← 1)
Control STOP 2 2 Set STOP Mode (PCC.3 ← 1)

Special RBn 2 2 RBS ← n (n = 0-3)

CALL !addr 3 3 (SP-4)(SP-1)(SP-2) ← PC11-0 *6

CALLF !faddr 2 2 (SP-4)(SP-1)(SP-2) ← PC11-0 *9

RET 1 3 MBE, RBE, PC13,12 ← (SP+1)

RETS 1 3+S MBE, RBE, PC13,12 ← (SP+1) Undefined

RETI 1 3 PC13,12 ← (SP+1)

PUSH rp 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2

POP rp 1 1 rp ← (SP+1)(SP), SP ← SP+2

OUT *1PORTn,A 2 2 PORTn ← A (n = 2-7, 9-14)

NOP 1 1 No Operation

SEL

GETI *2taddr 1 3

Operand Bytes

BS 2 2

BS 2 2

IExxx 2 2 IExxx ← 0

XA,PORTn 2 2

PORTn,XA 2 2 PORTn+1,PORTn ← XA (n = 4, 6)

MBn 2 2 MBS ← n (n = 0, 1, 15)

Ma- Ad-

chine

les Area

(SP-3) ← MBE, RBE, PC13,12
PC13-0 ← addr, SP ← SP-4

(SP-3) ← MBE, RBE, PC13,12
PC13-0 ← 00, faddr, SP ← SP-4

PC11-0 ← (SP)(SP+3)(SP+2)
SP ← SP+4

PC11-0 ← (SP)(SP+3)(SP+2)
SP ← SP+4,

PC11-0 ← (SP)(SP+3)(SP+2)
PSW ← (SP+4)(SP+5), SP ← SP+6

(SP-1) ← MBS, (SP-2) ← RBS, SP ← SP-2

MBS ← (SP+1), RBS ← (SP), SP ← SP+2

XA

←

.

Where TBR instruction, *10
PC13-0 ← (taddr)4-0+(taddr+1)

......................................................... .............................

.

Where TCALL instruction,
(SP-4)(SP-1)(SP-2) ← PC11-0
(SP-3) ← MBE, RBE, PC13,12
PC13-0 ← (taddr)5-0+(taddr+1)
SP ← SP-4

......................................................... .............................

.

Except for TBR and TCALL Depends on
instructions, referenced
Instruction execution of instruction
(taddr)(taddr+1)

Operation

then skip unconditionally

PORTn+1,PORTn

(n = 4, 6)

dress- Skip

*1: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.
*2: The TBR, and TCALL instructions are the assembler pseudo-instructions for the table definition of

GETI instruction.

43

11. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)

Parameter Symbol Conditions Ratings Unit

Supply Voltage VDD -0.3 to +7.0 V

VI1 Other than ports 4, 5, 12-14 -0.3 to VDD+0.3 V

Input Voltage VI2 Ports 4, 5, 12-14 w/pull-up -0.3 to VDD+0.3

Output Voltage VO -0.3 to VDD+0.3 V
High-Level Output IOH 1 pin -15 mA

Current

Low-Level Output IOL* 1 pin Peak 30 mA
Current rms 15 mA

Operating Temperature Topt -40 to +85 °C
Storage Temperature Tstg -65 to +150 °C

All pins -30 mA

Total of ports 0, 2, 3, 4 Peak 100 mA

Total of ports 5-11 Peak 100 mA

Total of ports 12-14 Peak 40 mA

*: rms = Peak value x √Duty

resistor
Open drain -0.3 to +11 V

rms 60 mA

rms 60 mA

rms 25 mA

µ

PD75512

V

OPERATING SUPPLY VOLTAGE

Parameter Symbol Conditions MIN. MAX. Unit

A/D Converter Supply voltage VDD 3.5 6.0 V

Ambient temperature Ta -10 +70 °C

Timer/Pulse Supply voltage VDD 4.5 6.0 V
Generator Ambient temperatuare Ta -40 +85 °C
Other Circuits Supply voltage VDD 2.7 6.0 V

Ambient temperatuare Ta -40 +85 °C

CAPACITANCE (Ta = 25°C, VDD = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input Capacitance CI f = 1 MHz 15 pF
Output Capacitance CO Pins other than thosemeasured are at 0 V 15 pF
Input/Output CIO

Capacitance

15 pF

44

MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS

a = -40 to +85°C, VDD = 2.7 to 6.0 V)

(T

µ

PD75512

Oscillator

Ceramic Oscillation VDD = osccillation

Crystal Oscillation

External Clock X1 input frequency

Recommended

Constants

X1 X2

C1 C2

X1 X2

C1 C2

X1 X2

Item Conditions MIN. TYP. MAX. Unit

frequency(fX)*
Oscillation stabiliza- After VDD came to

tion time*

1

voltage range

2

MIN. of oscillation
voltage range

frequency (fX)*
Oscillation stabiliza- VDD = 4.5 to 6.0 V 10 ms

tion time*

1

(fX)*

1

2

X1 input high-,
low-level widths

µ

PD74HCU04

(tXH, tXL) 100 500 ns

SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS

a = -40 to +85°C, VDD = 2.7 to 6.0 V)

(T

1.0 5.0

1.0 4.19 5.0

1.0 5.0

3

*

MHz

4ms

3

*

MHz

30 ms

3

*

MHz

Oscillator

Crystal Oscillation*

External Clock XT1 input frequency

Recommended

Constants

XT1 XT2

R

C3 C4

XT1 XT2

Open

Item Conditions MIN. TYP. MAX. Unit

1

frequency (fXT)
Oscillation stabiliza- VDD = 4.5 to 6.0 V 1.0 2 s

tion time*

2

32 32.768 35 kHz

10 s

(fXT)*

1

32 100 kHz

XT1 input high-,
low-level widths 5 15

µ

s

(tXTH, tXTL)

*1: Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC

Characteristics.

2: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage

range or the STOP mode has been released.

3: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction

µ

execution time: otherwise, one machine cycle is set to less than 0.95

µ

minimum value of 0.95

s.

s, falling short of the rated

45

µ

PD75512

★

Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion

enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity:

• Keep the wiring length as short as possible.

• Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines
through which a high alternating current flows.

• Always keep the ground point of the capacitor of the oscillator circuit at the same potential as V

DD.

Do not connect the power source pattern through which a high current flows.

• Do not extract signals from the oscillation circuit.

The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the
current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more
easily than the main system clock oscillation circuit. When using the subsystem clock, therefore,
exercise utmost care in wiring the circuit.

RECOMMENDED OSCILLATION CIRCUIT CONSTANTS

MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (Ta = -40 to +85°C)

Manufacturer Product Remarks

External Capacitor (pF) Oscillation Voltage Range (V)

C1 C2 MIN. MAX.

Kyocera KBR-1000H 100 100

Murata CSA 2.00MG

Toko CRHF 3.00 27 27 3.0 6.0

KBR-2.0MS 47 47 2.7 6.0
KBR-4.0MS 33 33

CSA 4.00MGU 30 30 2.7
CSA 4.19MG093
CSA 4.91MGU

CSA 4.91MG 30 30 3.0 6.0

CST 2.00MG
CST 4.00MGU Internally Internally 2.7
CST 4.19MG093 provided provided
CST 4.91MGU

CST 4.91MG Internally Internally 3.0

provided provided

CRHF 4.19

MAIN SYSTEM CLOCK: CRYSTAL OSCILLATOR (Ta = -20 to +70°C)

Manufacturer Product Remarks

External Capacitor (pF) Oscillation Voltage Range (V)

C1 C2 MIN. MAX.

Kinseki HC-49/U 27 27 2.7 6.0

46

DC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

High-Level Input VIH1 Ports 2, 3, 9-11, P80, P82 0.7VDD VDD V
Voltage

Low-level Input VIL1 Ports 2-5, 9-14, P80, P82 0 0.3VDD V
Voltage VIL2 Ports 0, 1, 6, 7, 15, P81, P83,

High-Level Output VOH VDD = 4.5 to 6.0 V, IOH = -1 mA VDD-1.0 V
Voltage IOH = -100 µAVDD-0.5 V
Low-Level Output VOL Ports 3, 4, and 5 VDD = 4.5 to 6.0 V, 0.4 2.0 V

Voltage IOL = -15 mA

High-Level Input ILIH1 VI = VDD Other than below 3
Leakage Current

Low-Level Input ILIL1 VI = 0 V Other than below -3
Leakage Current

High-Level Output ILOH1 VO = VDD Other than below 3
Leakage Current

Low-Level Output ILOL VO = 0 V
Leakage Current

Internal Pull-Up Resistor RU1

Internal Pull-Down RD VO = 2 V Port 9 20 70 140 kΩ
Resistor

VIH2 Ports 0, 1, 6, 7, 15, P81, P83,
VIH3 Ports 4, 5, 12-14 w/pull-up resistor 0.7VDD VDD V

Open-drain 0.7VDD 10 V

VIH4 X1, X2, XT1 VDD-0.5 VDD V

VIL3 X1, X2, XT1 0 0.4 V

VDD = 4.5 to 6.0 V, IOL = 1.6 mA 0.4 V
IOL = 400 µA 0.5 V
SB0, 1 Open-drain Pull-up

resistor ≥ 1 kΩ

ILIH2 X1, X2, XT1 20
ILIH3 VI = 9 V Ports 4, 5, 12-14

(open-drain)

ILIL2 X1, X2, XT1 -20

ILOH2 VO = 9 V Ports 4, 5, 12-14

(open-drain)

Ports 0, 1, 2, 3, 6, 7
(except P00) VI = 0V

RU2 Ports 4, 5, 12-14 VDD = 5.0 V±10% 15 40 70 kΩ

VO = VDD-2.0 V

VDD = 5.0 V±10% 15 40 80 kΩ
VDD = 3.0 V±10% 30 300 kΩ

VDD = 3.0 V±10% 10 60 kΩ

RESET

RESET

0.8VDD VDD V

0 0.2VDD V

0.2VDD V

20

20

-3

µ

PD75512

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

47

µ

PD75512

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply Current *1IDD1 4.19 MHz*2 crystal Ooperation VDD = 5 V±10%*

IDD2

IDD3 32.768 kHz*5 crystal Operation VDD = 3 V±10%

IDD4 HALT mode VDD = 3 V±10% 5 15
IDD5 XT1 = 0 V VDD = 5 V±10% 0.5 20

oscillator mode
C1 = C2 = 22pF

oscillator mode

STOP mode

HALT mode VDD = 5 V±10% 600 1800

VDD

= 3 V±10%

VDD = 3 V±10%*

VDD = 3 V±10% 200 600

Ta = 25°C5

3

4

39mA

0.55 1.5 mA

µ

A

µ

A

40 120

0.3 10

µ

A

µ

A

µ

A

µ

A

µ

A

*1: Currents for the built-in pull-up resistor are not included.

2: Including when the subsystem clock is operated.
3: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.
4: When operated in the low-speed mode with the PCC set to 0000.
5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to

stop the main system clock operation.

48

AC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V)

(1) Basic Operation

Parameter Symbol Conditions MIN. TYP. MAX. Unit

1

CPU Clock Cycle Time*
(Minimum Instruction
Execution Time
= 1 Machine Cycle

TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz

TI0 Input High-, tTIH,VDD = 4.5 to 6.0 V 0.48
Low-Level Widths t

Interrupt Input High-, tINTH, INT0 *2
Low-Level Widths t

RESET Low-Level Width tRSL 10

tCY w/main system clock VDD = 4.5 to 6.0 V 0.95 64

3.8 64

w/sub-system clock 114 122 125

0 275 kHz

TIL

INTL

INT1, 2, 4 10
KR0-7 10

1.8

*1: The CPU clock (Φ) cycle time is

determined by the oscillation frequency

tCY vs V

of the connected oscillator, system clock
control register (SCC), and processor
clock control register (PCC). The figure
on the right is cycle time t
voltage V

DD characteristics at the main

CY vs. supply

system clock.

2: 2tCY or 128/fX depending on the setting

of the interrupt mode register (IM0).

70

64
60

6
5

Guaranteed operating range

4

DD

(with main system clock)

µ

PD75512

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

3

µ

[ s]

CY

2

Cycle time t

1

0.5
0123 456

Supply voltage V

DD

[V]

49

(2) Serial Transfer Operation

(a) Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK Cycle Time tKCY1 VDD = 4.5 to 6.0 V 1600 ns

3800 ns

SCK High-, Low-Level tKL1 VDD = 4.5 to 6.0 V (tKCY1/2)-50 ns
Widths

SI Set-Up Time (vs. SCK ↑) tSIK1 150 ns

SI Hold Time (vs. SCK ↑ )tKSI1 400 ns
SCK ↓→ SO Output tKSO1 RL = 1 kΩ,VDD = 4.5 to 6.0 V 250 ns

Delay Time CL = 100 pF*

tKH1 (tKCY1/2)

-150

*: RL and CL are load resistance and load capacitance of the SO output line.

(b) Two-Line and Three-Line Serial I/O Modes (SCK: external clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK Cycle Time tKCY2 VDD = 4.5 to 6.0 V 800 ns

3200 ns

SCK High-, Low-Level tKL2 VDD = 4.5 to 6.0 V 400 ns
Widths

SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns

SI Hold Time (vs. SCK ↑)tKSI2 400 ns
SCK ↓→ SO Output tKSO2 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 300 ns

Delay Time

tKH2 1600 ns

*: RL and CL are load resistance and load capacitance of the SO output line.

µ

PD75512

ns

1000 ns

1000 ns

50

µ

PD75512

(c) SBI Mode (SCK: internal clock output (master))

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK Cycle Time tKCY3 VDD = 4.5 to 6.0 V 1600 ns

3800 ns

SCK High-, Low-Level tKL3 VDD = 4.5 to 6.0 V tKCY3/2-50 ns
Widths t

SB0, 1 Set-Up Time tSIK3
(vs. SCK ↑ )

SB0, 1 Hold Time tKSI3
(vs. SCK ↑ )

SCK ↓→ SB0, 1 Output tKSO3 RL = 1 kΩ,VDD = 4.5 to 6.0 V 0 250 ns
Delay Time CL = 100 pF*

SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns
SB0,1 ↓→ SCK tSBK tKCY3 ns
SB0, 1 Low-Level Width tSBL tKCY3 ns
SB0, 1 High-Level Width tSBH tKCY3 ns

KH3

tKCY3/2-150 ns

150 ns

tKCY3/2 ns

0 1000 ns

*: RL and CL are load resistance and load capacitance of the SO output line.

(d) SBI Mode (SCK: external clock input (slave))

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK Cycle Time tKCY4 VDD = 4.5 to 6.0 V 800 ns

3200 ns

SCK High-, Low-Level tKL4 VDD = 4.5 to 6.0 V 400 ns
Widths tKH4

SB0, 1 Set-Up Time tSIK4
(vs. SCK ↑ )

SB0, 1 Hold Time tKSI4
(vs. SCK ↑ )

SCK ↓→ SB0, 1 Output tKSO4 RL = 1 kΩ,VDD = 4.5 to 6.0 V 0 300 ns
Delay Time CL = 100 pF*

SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns
SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns
SB0, 1 Low-Level Width tSBL tKCY4 ns
SB0, 1 High-Level Width tSBH tKCY4 ns

1600 ns

100 ns

tKCY4/2 ns

0 1000 ns

*: RL and CL are load resistance and load capacitance of the SO output line.

51

µ

PD75512

(3) A/D Converter (Ta = -10 to +70°C, VDD = 3.5 to 6.0 V, AVSS = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 bit
Absolute Accuracy*
Conversion Time*
Sampling Time*

4

1

3

tCONV 168/fXµs

2.5 V ≤ AVREF ≤ VDD*

tSAMP 44/fX

2

±1.5 LSB

Analog Input Voltage VIAN AVSS AVREF V
Analog Input Impedance RAN 1000 MΩ
AVREF Current IREF 1.0 2.0 mA

*1: Absolute accuracy excluding quantization error (±1–2LSB)

2: Set ADM1 as follows, in respect to the reference voltage of the AD converter (AV

REF).

µ

s

2.5 V 0.6 V

REF

AV

DD

0.65 V

DD

VDD(3.5 to 6.0 V)

ADM1=0

ADM1=1

ADM1 can be set to either 0 or 1 when 0.6V

DD ≤ AVREF ≤ 0.65VDD

3: Time since execution of conversion start instruction until EOC = 1 (40.1 µs: fX = 4.19 MHz)

µ

4: Time since execution of conversion start instruction until end of sampling (10.5

s: fX = 4.19 MHz)

52

AC TIMING TEST POINT (excluding X1 and XT1 inputs)

0.8 V

0.2 V

DD

DD

Test points

CLOCK TIMING

1/f

X

t

XL

µ

PD75512

0.8 V

DD

0.2 V

DD

t

XH

TI0 TIMING

X1 input

XT1 input

V

DD

–0.5V

0.4 V

1/f

XT

t

XTL

t

XTH

V

DD

–0.5V

0.4 V

1/f

TI

TI0

t

TIL

t

TIH

53

SERIAL TRANSFER TIMING

THREE-LINE SERIAL I/O MODE:

SCK

µ

PD75512

t

KCY1

t

KL1

t

SIK1

t

KH1

t

KSI1

SI

SO

TWO-LINE SERIAL I/O MODE:

SCK

t

KSO1

tKL2

Input data

Output data

tKCY2

tKH2

tKSO2

SB0,1

54

tSIK2 tKSI2

SERIAL TRANSFER TIMING

BUS RELEASE SIGNAL

SCK

t

KSB

SB0,1

µ

PD75512

t

KCY3,4

t

KL3,4

t

t

t

SBL

SBH

SBK

t

KH3,4

t

KSO3,4

t

SIK3,4

t

KSI3,4

COMMAND SIGNAL TRANSFER:

SCK

t

KSB

SB0,1

INTERRUPT INPUT TIMING:

INT0, 1, 2, 4

KR0-7

t

KCY3,4

t

KL3,4

t

SBK

t

INTL

t

KH3,4

t

KSO3,4

t

INTH

t

SIK3,4

t

KSI3,4

RESET INPUT TIMING:

RESET

t

RSL

55

LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE

a = –40 to +85°C)

(T

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data Retention Supply VDDDR
Voltage

Data Retention Supply IDDDR VDDDR = 2.0 V
Current*

1

2.0 6.0 V

0.1 10

Release Signal Set Time tSREL 0
Oscillation Stabilization tWAIT Released by RESET 217/fX ms
Wait Time*

2

Released by interrupt *3 ms

*1: Does not include current flowing through internal pull-up resistor

2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent

unstable operation when oscillation is started.

3: Depends on the setting of the basic interval timer mode register (BTM) as follows:

BTM3 BTM2 BTM1 BTM0 WAIT time ( ): fX = 4.19 MHz

–0002
–0112
–1012
–1112

20

/fX (approx. 250 ms)

17

/fX (approx. 31.3 ms)

15

/fX (approx. 7.82 ms)

13

/fX (approx. 1.95 ms)

µ

PD75512

µ

A

µ

s

DATA RETENTION TIMING (releasing STOP mode by RESET)

Internal reset operation

HALT mode

STOP mode

Data retention mode

DD

V

V

DDDR

t

SREL

STOP instruction
execution

RESET

t

WAIT

DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)

HALT mode

STOP mode

Data retention mode

Operation
mode

Operation
mode

DD

V

STOP instruction execution

Standby release signal

(interrupt request)

56

V

DDDR

t

SREL

t

WAIT

12. PERFORMANCE CURVES

µ

PD75512

IDD vs VDD (Main system clock: Crystal oscillator)

5000

High-speed mode
PCC=0011

Middle-speed mode
PCC=0010

Low-speed mode
PCC=0000

1000

Main system clock
HALT mode

500

µ

DD

100

Subsystem clock
Operation mode

(T = 25°C)

a

50

Operating current I [ A]

10

5

1

0123456 7

C1

Operating voltage V [V]

DD

Main system clock
STOP mode + 32 kHz
oscillation and
subsystem clock
HALT mode

X1 X2 XT1 XT2

Crystal
oscillator

4.19 MHz

C2 C3

Crystal
oscillator

32.768 kHz

R

C4

57

µ

PD75512

IDD vs VDD (Main system clock: Ceramic oscillator)

a

(T = 25°C)

5000

High-speed mode
PCC=0011

Middle-speed mode
PCC=0010

Low-speed mode
PCC=0000

1000

Main system clock
HALT mode

500

µ

DD

100

Subsystem clock
Operation mode

50

Operating current I [ A]

10

5

1

01234567

C1

Operating voltage V [V]

DD

Main system clock
STOP mode + 32 kHz
oscillation and
subsystem clock
HALT mode

X1 X2 XT1 XT2

Ceramic
oscillator

4.19 MHz

C2 C3 C4

Crystal
oscillator

32.768 kHz

R

*: When compared to crystal oscillation, increased by approximately 10%.

58

5000

1000

500

IDD vs VDD (Main system clock: Ceramic oscillator)

µ

(T = 25°C)

a

High-speed mode
PCC=0011

Middle-speed mode
PCC=0010

Low-speed mode
PCC=0000

Main system clock
HALT mode

PD75512

µ

DD

100

50

Operating current I [ A]

10

5

Subsystem clock
Operation mode

Main system clock
STOP mode + 32 kHz
oscillation and
subsystem clock
HALT mode

X1 X2 XT1 XT2

C1

Ceramic
oscillator

2.0 MHz

C2 C3

Crystal
oscillator

32.768 kHz

R

C4

1

0123456 7

Operating voltage V [V]

DD

59

µ

PD75512

IDD vs VDD (Main system clock: Ceramic oscillator)

a

(T = 25°C)

5000

High-speed mode
PCC=0011
Middle-speed mode
PCC=0010
Low-speed mode

1000

500

µ

DD

100

PCC=0000

Main system clock
HALT mode

Subsystem clock
Operation mode

50

Operating current I [ A]

10

5

1

0123456 7

C1

Operating voltage V [V]

DD

Main system clock
STOP mode + 32 kHz
oscillation and
subsystem clock
HALT mode

X1 X2 XT1 XT2

Ceramic
oscillator

1.0 MHz

C2 C3

Crystal
oscillator

32.768 kHz

R

C4

60

µ

PD75512

I

DD

[mA]

x

f

DD

vs

3

I

(V = 5V, T = 25°C)

DD

2

High-speed mode
PPC = 0011

a

X1

X2

Middle-speed

0.5

High-speed mode
PPC = 0011

0.4

(V = 3V, T = 25°C)

x

f

DD

vs

I

DD

Middle-speed
mode
PPC = 0010

a

X1

X2

mode
PPC = 0010

0.3

I

1

Low-speed mode

DD

[mA]

0.2

Low-speed mode
PPC = 0000

PPC = 0000

Main system clock

0.1

HALT mode

0

123

x

f [MHz]

4

5

0

12345

Main system clock
HALT mode

x

f [MHz]

I

OL

[mA]

40

30

20

10

0

V = 6V

DD

VOLvs I

V = 5V

OL

DD

(Port 0, 2, 6, 7)

V = 3V

DD

V = 2.7V

DD

(T = 25°C)

a

V = 4V

DD

12345

V [V]

OL

OL

I

[mA]

40

30

20

10

0

V = 6V

DD

VOLvs I

V = 5V

DD

OL

V = 4V

DD

(Port 3, 4, 5)

V = 3V

DD

V = 2.7V

DD

a

(T = 25°C)

12345

V [V]

OL

61

20

V

OH vs

µ

PD75512

I

OH

(T = 25°C)

a

OH

I

[mA]

15

10

V = 6V

DD

5

0

12345

V = 5V

DD

V = 2.7VDD

OH

V - V [V]

DD

DD

V = 3V

V = 4V

DD

62

13. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14×20)

µ

PD75512

A

B

64

65

80

F

1

G

H

M

I

P

N

NOTE

Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.

41

40

detail of lead end

C

D

S

Q

25

24

J

K

M

L

P80GF-80-3B9-2

ITEM MILLIMETERS INCHES

M

A
B
C

D

F
G
H

I

J

K

L

N

23.6±0.4


20.0±0.2

14.0±0.2

17.6±0.4

1.0

0.8

0.35±0.10

0.15



0.8 (T.P.)



1.8±0.2

0.8±0.2

+0.10

0.15

–0.05

0.15

0.929±0.016

+0.009

0.795

–0.008

+0.009

0.551

–0.008

0.693±0.016

0.039

0.031

+0.004

0.014

–0.005

0.006

0.031 (T.P.)

+0.008

0.071

–0.009
+0.009

0.031

–0.008

+0.004

0.006

–0.003

0.006
P 2.7 0.106
Q

0.1±0.1

0.004±0.004
S 3.0 MAX. 0.119 MAX.

5°±5°



63

µ

PD75512

★

14. RECOMMENDED SOLDERING CONDITIONS

It is recommended that µPD75512 be soldered under the following conditions.
For details on the recommended soldering conditions, refer to Information Document "Semiconductor

Devices Mounting Manual" (IEI-616).

The soldering methods and conditions are not listed here, consult NEC.

Table 14-1 Soldering Conditions

µ

PD75512GF-xxx-3B9: 80-pin plastic QFP (14 × 20 mm)

Soldering Method Soldering Conditions

Infrared Reflow Package peak temperature: 230°C, IR30-00-1

time: 30 seconds max. (210°C min.),
number of times: 1

VPS Package peak temperature: 215°C, VP15-00-1

time: 40 seconds max. (200°C min.),
number of times: 1

Wave Soldering Soldering bath temperature: 260°C max., WS60-00-1

time: 10 seconds max., number of times: 1,
pre-heating temperature: 120°C max. (package surface
temperature)

Pin Partial Heating Pin temperature: 300°C max., —

time: 3 seconds max. (per side)

Symbol for Recommended
Condition

Caution: Do not use two or more soldering methods in combination (except the pin partial heating

method).

Notice

A model that can be soldered under the more stringent conditions (infrared reflow peak
temperature: 235°C, number of times: 2, and an extended number of days) is also available.
For details, consult NEC.

64

µ

PD75512

APPENDIX A. DEVELOPMENT TOOLS

The following development support tools are readily available to support development of systems using

µ

PD75512:

Hardware IE-75000-R *

IE-75001-R
IE-75000-R-EM *
EP-75516GF-R Emulation prove for µPD75512, provided with 80-pin conversion socket

PG-1500 PROM programmer
PA-75P516GF PROM programmer adapter solely used for µPD75P516GF. It is connected

Software IE Control Program

PG-1500 Controller
RA75X Relocatable

Assembler

1

2

EV-9200G-80

In-circuit emulator for 75X series

Emulation board for IE-75000-R and IE-75001-R

EV-9200G-80.

to PG-1500.

Host machine

• PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3)

• IBM PC/ATTM (PC DOSTM Ver.3.1)

*1: Maintenance product

2: Not provided with IE-75001-R.
3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software.

Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).

65

µ

PD75512

★

APPENDIX B. RELATED DOCUMENTS

66

µ

PD75512

GENERAL NOTES ON CMOS DEVICES

1 STATIC ELECTRICITY (ALL MOS DEVICES)

Exercise care so that MOS devices are not adversely influenced by static electricity while being

handled.

The insulation of the gates of the MOS device may be destroyed by a strong static charge.
Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,
or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use
grounding when assembling the MOS device system. Do not leave the MOS device on a plastic
plate and do not touch the pins of the device.

Handle boards on which MOS devices are mounted similarly .

2 PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)

Fix the input level of CMOS devices.

Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow
through the device, causing the device to malfunction. Therefore, fix the input level of the device
by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an
output pin (whose timing is not specified), each pin should be connected to V
a resistor.

Refer to “Processing of Unused Pins” in the documents of each devices.

DD or GND through

3 STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)

The initial status of MOS devices is undefined upon power application.

Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The
output status of pins, I/O setting, and register contents upon power application are not guaranteed.
However, the items defined for reset operation and mode setting are subject to guarantee after
the respective operations have been executed.

When using a device with a reset function, be sure to reset the device after power application.

67

[MEMO]

µ

PD75512

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which
may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties b y or arising from use of a device described herein or any
other liability arising from use of such device. No license, either express, implied or otherwise, is granted
under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,
nuclear reactor control systems and life support systems. If customers intend to use NEC devices for
above applications or they intend to use "Standard" quality grade NEC devices for the applications not
intended by NEC, please contact our sales people in advance.
Application examples recommended by NEC Corporation

Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products,etc.

Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime system, etc.

M4 92.6

MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.

68